This document is a resume for S.Ameenulla, an M.Tech graduate in VLSI Design Engineering with skills in Verilog HDL, Cadence tools, and low power design. It summarizes his education qualifications including an M.Tech from VIT-Vellore and B.Tech from Sreenivasa Institute of Technology. It also lists his projects in low power test pattern generation, ASIC implementation of ADPLL, FPGA implementation of a cryptographic technique, and design of a low power high speed multiplier. Additionally, it provides his contact information, achievements including a GATE rank, and personal details.

1. S.Ameenulla
E-mail: ameenulla903@gmail.com Phone:+ 91 –
9032967684
M.Tech.(VLSI-Design)
Result oriented, proactive and hardworking professional with M.Tech in VLSI-Design Engineering from VIT-Vellore, one
of the prestigious college in India. Understanding of all aspects governing Digital IC Design field in which creative and
innovative ideas can be utilized. Effective focus on Low power designs. Outstanding communication skills, verbal as
well as written coupled with exceptional presentation skills. Strong team builder with proven ability to motivate team
members.
Skills and tools Include
 Hardware/Software language :Verilog HDL,C  Synthesis :Cadence RTL Compiler
 Schematic Design :Cadence virtuoso
 Physical design :Cadence Soc encounter
 Simulation :Mentor Graphics Modelsim,
Quatrus,NC-Sim
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EDUCATION
M.Tech. VLSI-Design – 7.78/10
Vellore Institute of Technology – Vellore, Vellore campus
B.Tech ECE – 62.9%
Sreenivasa Institute of Technology and Management Studies – Chittoor
Intermediate public Examinations – 89.8%
Sri Chaitanya Jr. college (A.P. State Board) – Tirupati
Xth Class – 86.84%

2. Khadri High School (A.P. State Board) - Kadiri
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PROJECTS DONE
1. Low Power Test Pattern Generation
Low power test pattern is generated by increasing the correlativity and decreasing the transition between the
successive test patterns and identify the dead lock states of the test pattern generator and if found a new seed
will be inserted into the test pattern generator by using the re-seeding generator, the generated test pattern is
fed into ISCAS’89 bench mark circuits.
2. ASIC Implementation of ADPLL
The All-Digital phase locked loop is a phase lock loop implemented in purely digital circuitry and operating on
finite precision digital words. The design was simulated and synthesized with constraints. Physical design was
carried out and GDS-II file was generated.
3. FPGA Implementation Of Cryptographic Technique
Secrete message encoded into image bits, the position of secrete message bit is determined by using LFSR
and secrete seed value. The embedded image is sent from a transmitter and the secrete message is recovered
by using the LFSR and secrete seed value at the receiver.
4. Design of low power high speed multiplier using modified booth algorithm
High speed low power consumption multiplier is implemented by using dynamic range detection unit and for
multiplication purpose modified booth radix-2 algorithm is used and then design was simulated and
synthesized with constraints. Physical design was carried out and GDS-II file was generated.
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3. Achievements and other Distinctions
 Secured an all INDIA rank of 4928 in GATE( Graduate Aptitude Test for Master’s Degree
Entrance)
 Elected as a coordinator in Alumni community in the Engineering.
 Functioned as an Event organizer in all school and college annual day functions and other technical
Events.
 Participated in presentation in eco-friendly theme fest conducted in SITAMS Chittoor
Personal profile
Date of Birth : 9
th
December 1990
Languages known : English, Hindi and Telugu
Hobbies : listening music
Address : 1-363-15-7A,
Gandhi nagar, kadiri,
Anantapur district,
Andhrapradesh