Amrut S. Jigajinni is seeking a challenging position in ASIC front design and verification. He has a Master's in VLSI Design from Manipal University and a B.E. in Electronics and Communication Engineering. He currently works as an ASIC Digital Design Engineer at Synopsys India PVT LTD, where he has worked since 2014. His responsibilities have included RTL design using Verilog HDL, synthesis, CDC analysis, linting, UPF flows, and BFM for verification. He is proficient in Synopsys VCS, Design Compiler, and Spyglass EDA tools as well as USB 2.0, UTMI, and AMBA AXI protocols. Notable
Hi mam/sir
This is ravi i have completed M.tech(vlsi design )in 2015 from SVCET engineering college.i am looking for VLSI/ASIC design &verification engineer & i have knowledge on physical design also ,so I have been 9 month experience project intern at maven silicon .If any opportunity is there in your industry means please kindly inform me.
Protocal knowns.
Router1x3,AHB-APB (AMBA protocols),UART,SPI,AXI.
mobile no:08884608550
Thank you.
HARDWARE SOFTWARE CO-SIMULATION OF MOTION ESTIMATION IN H.264 ENCODERcscpconf
This paper proposes about motion estimation in H.264/AVC encoder. Compared with standards
such as MPEG-2 and MPEG-4 Visual, H.264 can deliver better image quality at the same
compressed bit rate or at a lower bit rate. The increase in compression efficiency comes at the
expense of increase in complexity, which is a fact that must be overcome. An efficient Co-design
methodology is required, where the encoder software application is highly optimized and
structured in a very modular and efficient manner, so as to allow its most complex and time
consuming operations to be offloaded to dedicated hardware accelerators. The Motion
Estimation algorithm is the most computationally intensive part of the encoder which is simulated using MATLAB. The hardware/software co-simulation is done using system generator tool and implemented using Xilinx FPGA Spartan 3E for different scanning methods.
Microcontroller Based Testing of Digital IP-CoreVLSICS Design
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.
1. AMRUT S.JIGAJINNI
Email ID: amrutjigajinni@gmail.com Contact No: +91- 9738544359
Place: Bangalore
Professional Objective
Seeking a challenging and rewarding opportunities in ASIC Front Design & Verification
Masters in VLSI Design with CGPA of 9.13 in 2012-2014 from Manipal University
B.E (Electronics and Communication Engineering) with CGPA of 8.47 in 2007-2011
from Basaveshwar Engineering College, Bagalkot under VTU Belgaum.
Company Name Period Position
Synopsys India PVT LTD June 2014 – till date
ASIC Digital Design Engineer
Synopsys India PVT LTD June 2013 – June 2014 Intern Technical (IP R&D Team)
Design & Verification: RTL Design using Verilog HDL, Synthesis, CDC, Linting, UPF Flow,
BFM for verification using VTB
EDA Tools: Synopsys VCS, Design Compiler, Spyglass
Protocols: USB 2.0, UTMI and AMBA AXI
1) UTMI to UTMI Bridge
Description: UTMI to UTMI (U2U) Bridge eliminates analog components in USB2.0
protocol, by providing an alternative method to connect a device controller to a host
controller. It emulates the PHY functionality at the device and host UTMI interface
Responsibilities:
Modification in the existing behavioral logic in RTL and functional RTL debugging
Coded logic for basic assertion checks by instantiating OVL libraries in design
Synthesis Activities, CDC, Linting, STA checks
Educational qualification
Experience Summary
Technical Skills
Projects
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2. 2) USB 2.0 HSOTG Controller
Description: HSOTG is a Dual Role Device (DRD) controller that supports both device
and host functions and complies with USB 2.0 specification. It supports for high speed, full
speed and low speed devices.
Responsibilities:
RTL modification for replacing the CDC synchronizer modules with standard CDC
synchronizer libraries across the IP and RTL support in the form of bug fixes
Complete ownership of debugging the Spyglass CDC violations
Debugging of functional failures with Mis-sampling enabled synchronizers
Debugging of functional failures with VCS XPROP simulator.
Synthesis Activities, Linting, STA checks, UPF Flow and Low Power Analysis, RTL
coverage Analysis and RAL testing
3) Error detection for decoded JPEG image
Description: After a JPEG image has been decoded, transmission errors which leads to
corruption of data blocks are detected using an AID algorithm. Here Average Inter Sample
Difference (AID) algorithm is designed to detect the transmission errors of decoded JPEG
image, which corrupts the data block.
Responsibilities:
Solely responsible for the RTL Design & functional verification of the AID algorithm
Customer Support on debugging the functional issues of the existing JPEG core
4) DMA Controller for 10- Gigabit Ethernet MAC
Description: The DMA designed here helps to achieve the required throughput of
10- Gigabit Ethernet MAC (XGMAC). DMA handles the Ethernet data packet
transfer between the XGMAC core and the host system using the descriptors
provided by the host application.
Responsibilities:
Responsible for RTL design
Implemented the task based Bus Function Models in Verilog, for module level
verification
Synthesis, Linting, and RAL Testing
Declaration
I hereby declare that the information furnished above is true to the best of my knowledge.
Place: Bangalore AMRUT S.JIGAJINNI
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