This document discusses smart memory architectures. It describes smart memory chips as modular computers containing an array of processor tiles and on-die DRAM memories connected by a packet-based, dynamically-routed network. Each processor tile contains two integer clusters, one floating point cluster, locally connected memory, and a crossbar to connect different memory mats to processor ports. The smart memory architecture reduces I/O bandwidth needs by locating processors and memory on the same die and connecting them with an efficient network. It allows both the processors and memory to be programmed for high performance and low latency computing.

1. Presented by
K.V.HARSHINI

2. CONTENTS
1.INTRODUCTION
2. SMART MEMORIES OVERVIEW
3.MEMORY SYSTEM
4. INTERCONNECTION
5.PROCESSOR
6. I/O Technology Choice in Smart Memory
7.ADVANTAGES
8.DISADVANTAGES
9.CONCLUSION
10.REFERENCES

3. INTRODUCTION
 The continued scaling of integrated circuit fabrication
technology will dramatically affect the architecture of
future computing systems. Scaling will make computation
cheaper, smaller, and lower power, thus enabling more
sophisticated computation in a growing number of
embedded applications. This spread of low-cost, low power
computing can easily be seen in today’s wirede.g. gigabit
Ethernet or DSL) and wireless communication devices,
gaming consoles, and handheld PDAs. These new
applications have different characteristics from today’s
standard workloads, often containing highly data- Parallel
streaming behaviour.

4. SMART MEMORIES OVERVIEW
 At the highest level, a Smart Memories chip is a
modular computer. It contains an array of processor
tiles and on-die DRAM memories connected by a
packet-based, dynamically-routed network (Figure).
 The network also connects to high-speed links on
the pins of the chip to allow for the construction of
multi-chip systems. Most of the initial hardware
design works in the Smart Memories project has
been on the processor tile design and evaluation, so
this paper focuses on these aspects.

6. MEMORY SYSTEM

7. INTERCONNECT
 To connect the different memory mats to the desired
processor or quad interface port, the tile contains a
dynamically routed crossbar, which supports up to 8
concurrent references.

8. PROCESSOR
 The processor portion of a Smart Memories tile is a
64-bit processing engine with reconfigurable
instruction format/decode. The computation
resources of the tile consist of two integer clusters
and one floating point (FP) cluster. The arrangement
of these units and the FP cluster unit mix .
 Each integer cluster consists of an ALU, register file,
and load/store unit.

9. I/O TECHNOLOGY CHOICE IN SMART MEMORY
 Smart Memory reduces the chip I/O
bandwidth significantly
 How to further optimize it?
Based on MoSys data
Bandwidth, latency and I/O bandwidth gap is growing
On-chip bandwidth is much higher than memory I/O
Smart Memory use serial I/O
-4X throughput than RLDRAM and QDR
-3X fewer pins than DDR3 and DDR4
-2.5X reduces I/O power

10. ADVANTAGES
 Reduced chip I/O bandwidth
 High performance and low latency
 Feature rich, flexible and programmable
 Lower cost
 One chip for several functions

11. DISADVANTAGES
•Packet Processing Bottlenecks
Data away from compute
I/O and memory bandwidth
•Smart Memory
Keep compute close to data
Keep locking close to data
Provide inter-memory connect

12. CONCLUSION
 Smart Memories addresses this issue by extending
the notion of a program. In conventional computing
systems the memories and interconnect between
the processors and memories is fixed, and what the
programmer modifies is the code that runs on the
processor. While this model is completely general,
for many applications it is not very efficient. In
Smart Memories, the user can program the wires
and the memory, as well as the processors.

13. REFERENCES
 www.google.com
 www.wikipedia.org
 www.studymafia.org

14. Thank You