8. directly captures a large raw signal and a smalle
There is a trade-off between having a larger L va
8
nergy con-
ction 6 de-
To Sensor Node
cluding re-
Error
PPS
Figure 2. Schematic for wireless power line clock synchronization module.
vely in the
sented the
dering in a
hence losing energy.
for order-
OPA333
ng devices.
a common
most com-
Time Pro-
Gain
averaging
Amp
vers to set
es a clock- Figure 1. AC power-line EM receiver (Syntonistor
from AC power lines. The primary challenge in
n was amplifying a signal, which is typically on the
ens of micro-volts while rejecting noise. The cir-
ins contin- to a coin.
OPA2369-2
10K
Vbias
tly behind
10µF
o seconds
e a similar Global Positioning System (GPS) uses precise clock
wly adjust chronization derived from satellite transmissions for
INA333
Vcc
ge time of ization. GPS time receivers have commonly been u
50K
50K
sources for NTP servers. The Radio Data System (RDS
15µF
k synchro- the sidebands on standard FM radio transmissions to e
networks. data including the time. These receivers typically con
470mH
urate syn- too much energy for use on a node-by-node basis in
y overhead sor network and in the case of GPS and WWVB requ
Vcc
nchroniza- rect line of sight with the sky. The RT-Link [20] pr
2M
2M
d between uses a carrier current AM radio transmitter to send
s. This ap- time beacons to sensor nodes. The system uses a buil
g jitter as- wiring infrastructure as an antenna to broadcast an AM
9. directly captures a large raw signal and a smalle
There is a trade-off between having a larger L va
9
nergy con-
ction 6 de-
To Sensor Node
cluding re-
Error
PPS
Figure 2. Schematic for wireless power line clock synchronization module.
vely in the
sented the
dering in a
hence losing energy.
for order-
OPA333
ng devices.
a common
most com-
Time Pro-
Gain
averaging
Amp
vers to set
es a clock- Figure 1. AC power-line EM receiver (Syntonistor
from AC power lines. The primary challenge in
n was amplifying a signal, which is typically on the
ens of micro-volts while rejecting noise. The cir-
ins contin- to a coin.
OPA2369-2
10K
Vbias
tly behind
10µF
o seconds
e a similar Global Positioning System (GPS) uses precise clock
wly adjust chronization derived from satellite transmissions for
INA333
Vcc
ge time of ization. GPS time receivers have commonly been u
50K
50K
sources for NTP servers. The Radio Data System (RDS
15µF
k synchro- the sidebands on standard FM radio transmissions to e
networks. data including the time. These receivers typically con
470mH
urate syn- too much energy for use on a node-by-node basis in
y overhead sor network and in the case of GPS and WWVB requ
Vcc
nchroniza- rect line of sight with the sky. The RT-Link [20] pr
2M
2M
d between uses a carrier current AM radio transmitter to send
s. This ap- time beacons to sensor nodes. The system uses a buil
g jitter as- wiring infrastructure as an antenna to broadcast an AM
10. directly captures a large raw signal and a smalle
There is a trade-off between having a larger L va
10
nergy con-
ction 6 de-
To Sensor Node
cluding re-
Error
PPS
Figure 2. Schematic for wireless power line clock synchronization module.
vely in the
sented the
dering in a
hence losing energy.
for order-
OPA333
ng devices.
a common
most com-
Time Pro-
Gain
averaging
Amp
vers to set
es a clock- Figure 1. AC power-line EM receiver (Syntonistor
from AC power lines. The primary challenge in
n was amplifying a signal, which is typically on the
ens of micro-volts while rejecting noise. The cir-
ins contin- to a coin.
OPA2369-2
10K
Vbias
tly behind
10µF
o seconds
e a similar Global Positioning System (GPS) uses precise clock
wly adjust chronization derived from satellite transmissions for
INA333
Vcc
ge time of ization. GPS time receivers have commonly been u
50K
50K
sources for NTP servers. The Radio Data System (RDS
15µF
k synchro- the sidebands on standard FM radio transmissions to e
networks. data including the time. These receivers typically con
470mH
urate syn- too much energy for use on a node-by-node basis in
y overhead sor network and in the case of GPS and WWVB requ
Vcc
nchroniza- rect line of sight with the sky. The RT-Link [20] pr
2M
2M
d between uses a carrier current AM radio transmitter to send
s. This ap- time beacons to sensor nodes. The system uses a buil
g jitter as- wiring infrastructure as an antenna to broadcast an AM
11. directly captures a large raw signal and a smalle
There is a trade-off between having a larger L va
11
nergy con-
ction 6 de-
To Sensor Node
cluding re-
Error
PPS
Figure 2. Schematic for wireless power line clock synchronization module.
vely in the
sented the
dering in a
hence losing energy.
for order-
OPA333
ng devices.
a common
most com-
Time Pro-
Gain
averaging
Amp
vers to set
es a clock- Figure 1. AC power-line EM receiver (Syntonistor
from AC power lines. The primary challenge in
n was amplifying a signal, which is typically on the
ens of micro-volts while rejecting noise. The cir-
ins contin- to a coin.
OPA2369-2
10K
Vbias
tly behind
10µF
o seconds
e a similar Global Positioning System (GPS) uses precise clock
wly adjust chronization derived from satellite transmissions for
INA333
Vcc
ge time of ization. GPS time receivers have commonly been u
50K
50K
sources for NTP servers. The Radio Data System (RDS
15µF
k synchro- the sidebands on standard FM radio transmissions to e
networks. data including the time. These receivers typically con
470mH
urate syn- too much energy for use on a node-by-node basis in
y overhead sor network and in the case of GPS and WWVB requ
Vcc
nchroniza- rect line of sight with the sky. The RT-Link [20] pr
2M
2M
d between uses a carrier current AM radio transmitter to send
s. This ap- time beacons to sensor nodes. The system uses a buil
g jitter as- wiring infrastructure as an antenna to broadcast an AM
12. which uses resonance to amplify the inherently sm
directly captures a large raw signal and a smalle
There is a trade-off between having a larger L va
12
s energy con-
To Sensor Node
Section 6 de-
Error
PPS
Figure 2. Schematic for wireless power line clock synchronization module.
concluding re-
ensively in the
hence losing energy.
presented the
ordering in a
OPA333
hod for order-
mong devices.
ng a common
he most com-
Gain
Amp
ork Time Pro-
elay averaging
servers to set
from AC power lines. The primary challenge in
n was amplifying a signal, which is typically on the
ens of micro-volts while rejecting noise. The cir-
needs to strike the right balance between energy
OPA2369-2
10K
P uses a clock- Figure 1. AC power-line EM receiver (Syntonis
Vbias
emains contin- to a coin.
10µF
lightly behind
ks to seconds
INA333
ilize a similar Global Positioning System (GPS) uses precise c
Vcc
slowly adjust chronization derived from satellite transmissions
50K
50K
e edge time of ization. GPS time receivers have commonly bee
15µF
sources for NTP servers. The Radio Data System (R
lock synchro- the sidebands on standard FM radio transmissions
470mH
nsor networks. data including the time. These receivers typically
accurate syn- too much energy for use on a node-by-node basis
Vcc
ergy overhead sor network and in the case of GPS and WWVB r
2M
2M
synchroniza- rect line of sight with the sky. The RT-Link [20
nged between uses a carrier current AM radio transmitter to se
elays. This ap- time beacons to sensor nodes. The system uses a
13. directly captures a large raw signal and a smalle
There is a trade-off between having a larger L va
13
nergy con-
ction 6 de-
To Sensor Node
cluding re-
Error
PPS
Figure 2. Schematic for wireless power line clock synchronization module.
vely in the
sented the
dering in a
hence losing energy.
for order-
OPA333
ng devices.
a common
most com-
Time Pro-
Gain
averaging
Amp
vers to set
es a clock- Figure 1. AC power-line EM receiver (Syntonistor
from AC power lines. The primary challenge in
n was amplifying a signal, which is typically on the
ens of micro-volts while rejecting noise. The cir-
ins contin- to a coin.
OPA2369-2
10K
Vbias
tly behind
10µF
o seconds
e a similar Global Positioning System (GPS) uses precise clock
wly adjust chronization derived from satellite transmissions for
INA333
Vcc
ge time of ization. GPS time receivers have commonly been u
50K
50K
sources for NTP servers. The Radio Data System (RDS
15µF
k synchro- the sidebands on standard FM radio transmissions to e
networks. data including the time. These receivers typically con
470mH
urate syn- too much energy for use on a node-by-node basis in
y overhead sor network and in the case of GPS and WWVB requ
Vcc
nchroniza- rect line of sight with the sky. The RT-Link [20] pr
2M
2M
d between uses a carrier current AM radio transmitter to send
s. This ap- time beacons to sensor nodes. The system uses a buil
g jitter as- wiring infrastructure as an antenna to broadcast an AM
14. A similar operation is performed if no input signal is de-
tected for a long enough duration. The primary output from initialization messages.
the PLL is a PPS signal with a 50% duty-cycle that toggles 4.1 The Protocol
whenever an internal counter is reached. This error signal The protocol begins when a master node broa
could be due to a change in the building’s magnetic field and message at its rising PPS edge that contains its wa
time. The message is flooded across the network u
CC2420 radio timestamped at the lowest level to
uncertainty as described in [18],[16] and [17]. A
!" timestamp to the message immediately before trans
( removes timing uncertainty from potential radio pac
)*+ #$ %&' lisions. Each sensor node maintains a timer contai
#, •
amount of time that has expired since its last PPS risi
When a node receives a clock synchronization me
•
notes the timestamp of the message from the master
as the current timestamp computed from the previo
Figure 5. Block diagram for PLL clock recovery system. The receiving node must then record its current ph
&$'("
.+*77*/,0123/4
&$'(
5,6*13
&$'$%
&$'$$
&$'$#
&$'$"
! "! #! $! %! &!! &"!
)*+,-./,0123/4
&!
.+*77*/,0123/4
59:/,-;6616
8
!
!8
14
!&!
! "! #! $! %! &!! &"!
)*+,-./,0123/4
15. 100 68 2.8 43 20.2
Table 1. The performance of various LC combinations.
Component Typical Power (µW ) Max Power (µW )
INA333 40 90
OPA2369 0.84 1.0
OPA333 10 30
MCP4012 1.2 10
PIC12F683 5 19.8
Total 57.04 150.8
Table 2. This table shows a breakdown of average power
consumed by the main hardware components.
ducing the outputs that are passed on to the host sensor node.
The PIC12F683 also operates as an auto-gain system trying
to maintain a peak-to-peak voltage coming out of the ampli-
15
17. Θ =460 Θ =13
Θ =230
Θ = 16 Θ = 400
Θ =15
Θ = 900
(a) (b) (c)
Figure 7. Operation of initialization phase of phase offset calculation. (a) shows a set of nodes. (b) shows a spanning tree
used to determine offsets from a master clock.(c) Phase offset values between sets of nodes that can be used for error
1. TPSN
checking.
2.
set from its local PPS signal and subtract the communication
the nodes are able to estimate phase offset of their local PPS
delay that was accumulated during the flooding. Figure 9 signal to that of the master. The timing diagram of the phase
3.
shows how message propagation delay can be reduced by
removing constant header offsets from packets and trigger-
calculation for the topology in Figure 7(a) is shown in Fig-
ure 8. The phase offset between the master and node i is
phase
offset
ing on the start of frame delimiter provided by the CC2420
hardware. Figure 10 shows a distribution of radio pulse times
given by Θi . For example, the phase-offset between the mas-
ter M and node d is Θd = 230 ms as shown in Figure 8. This
recorded between a transmitter and two receivers. We see a synchronization flooding is only required at network initial-
worst-case jitter of approximately 6µs per hop. This is con- ization time. If new nodes join the network, they can com-
sistent with values seen by other in-band message passing municate with existing infrastructure nodes to obtain a phase
protocols. offset. However, if a new node attempts to synchronize based
After the flood has propagated across the network, each
node should maintain a synchronization time point as well as
on a node which was not synchronized from the master, then
the jitter from the EM receiver (which is significantly larger
than that of the radio) will begin to accumulate. In this case,
17
18. Protocol (2 of 2)
! Simple
! MAC protocol independent
18
20. —
—
—
ew set of flooding time synchronization
h to low transition naturally happens the
powered on. One possible optimization
—
!"#$ *+,#$,%&#$)
%&$'(#$)
request the phase offset based on their -.. /#
ice this works well, however over time !"#$
*+,#$,%&#$)
nodes drifting with respect to the master %&$'(#$)
o in and out of synchronization in lock- 2!341
01 5652789:
!"#$
"
al Evaluation %&$'(#$)
*+,#$,%&#$)
* # %#
we will evaluate the performance of our
*#;"
on hardware solution. We examine the <$=, >$ 51 2%,;
ons of timing jitter in the system which >)(,&/$)?;)
on synchronization accuracy. We eval-
ss of our software PLL with respect to
and coping with noise. Using data col-
Figure 11. Experimental Setup. 20
21. .+*
!8
5
!&!
! "! #! $!
)*+,-./,0123/4
$! %! &!! &"!
Figure 14. PLL output value a
)*+,-./,0123/4
PLL output value and error
20
15
Percent
10
5
0
15 15.5 16 16.5 17 17.5 18 18.5
Period (milliseconds)
(a)
40
18.5 Figure 1
35
below fo
30
25
Figure 13. Raw input signal with filtered output signal
Percent
20 the conv
below for two different nodes. an initia
15
plot in F
10
cal clock
the convergence of the PLL. We see that the error starts from 5 higher w
lines. Th
an initial offset of -5 ms and converges closely to 0. The first 0
15 15.5 16 16.5 17 17.5 18 18.5
adjustme
plot in Figure 14 shows an example of how the PLL’s lo-
Period (Milliseconds)
(b) for the o
cal clock converges which was initialized to a period slightly presente
higher with respect to the 16.66 ms signal from the power Figure 12. Jitter in the raw induced signal shown in (a). gence tim
lines. This phenomena captures the nature of the global rate Jitter after the PLL shown in (b). of the P
adjustment that happens on each receiver. Convergence plots
21
18.5
the upda
for the other nodes in the system were similar to the one we verged o
presented with slightly different starting offsets and conver-
22. 6
Max. Error
Avg Error
5
Mean
4
(milliseconds)
Phase
3
2
1
0
0 2000 4000 6000 8000 10000 12000 14000 16000
Time (Minutes)
Figure 17. Average and max synchronization error over an 11 day period. 22
23. decrease the synchronization interval. As described by the
original authors, the following equation shows how to com-
200
Ideal Non−Adjusted
180
LPL−CSMA Rate Adjusted
160 Syntonistor Hardware
Average Power (uW)
140
120
100
80
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10
Synchronization Accuracy (ms)
23
Figure 18. Energy comparison between hardware syn-
27. wide range of possible inductor and capacitor MCP4012
s PIC12F683
Total
Table 2. This table show
consumed by the main
not saturating in the presence of
1
r=
processor mustffilter the incoming
√ (1)
le pulse per second (PPS) output
2π LC
use for synchronization purposes.
y output so as to not unnecessar- ducing the outputs that ar
node. Finally, the processor must The PIC12F683 also ope
1 L
ects that the signal is no longer re-
to maintain a peak-to-pe
Q=
f this section, we will discuss the (2)
achieve these goals. R C fier well below saturatio
ference from the environment values. The peak-to-peak
nt of noise in the raw signal re-
1
vide an in-depth evaluation of this of change in auto-gain
fc =
nds to suffer from jitter as well as (3) determining the strength
2πRC
reception. Filtering such a signal
over a clock is commonly solved from the second stage am
gnal is further amplified through a second stage
op (PLL). A PLL will generate its amp configured as a zero
A369 micro-power op-amp. A second OPA369 attached to a FireFly node. the OP
eriod that increases or decreases
Figure 6. The Syntonistor sumes less power,
hase difference between its local
he samewhich package) is used to create a low-
The rate at
IC the local clock is the zero-crossing detecto
oltage to center theprob- Hz hence should be used toto the protocol that it may an op-amp i
t signal is a classical control 60 signal helping alert
n the linear operating range of the amplifier.
plemented a proportional-integral 27
slew rate of need to
re-synchronize with the network. sumption where lower p
28. L C R Q Test Signal
(mH) (µF) (Ohms) Factor Response (mV )
15000 0.47 1000 5.67 464
1500 4.7 40 14.1 202
320 22 10 12.1 113
220 30 15 5.7 18
470 15 600 0.5 20
100 68 2.8 43 20.2
Table 1. The performance of various LC combinations.
Component Typical Power (µW ) Max Power (µW )28
29. Figure 3. A wide range of possible inductor and capacitor29
30. of the OPA369 to one of 64 different levels. The output spon
from the OPA369 is passed directly to an analog input on a high
PIC12F683 micro-controller. The PIC12F683 runs all of the timi
firmware, described in the next section, responsible for pro- fina
cess
sum
the
−4
x 10
1.2
base
100 mH
470 mH
1 stren
GPI
0.8 the n
Voltage (Volts)
0.6
3.2
T
0.4
trem
just
0.2
scar
activ
0
at 2
0 100 200 300 400 500 600 700 800 900 1000
sible
Frequency (Hz)
adju
Figure 4. Two different frequency responses 30
ensu
31. from the PPS signal at each node, which should not accumu
late over each hop. The phase offset of a node at the nth hop
φn , is given by:
φn = Θn + δEM + (n · δradio ) + (n · trelay · ρ)
(4
⇒ εn = δEM + (n · δradio ) + (n · trelay · ρ)
where Θn denotes the actual phase offset of the node from
the master, trelay is the time taken by each node to forward
the beacon, ρ is the clock drift rate, and δEM and δradio are
31
32. 30
%/()3 %/
25
%'()* %+',
%'()- %.,/ 20
Percent
%0()1 %'2 15
%0()5 %06/ 10
%6()4 %+.//
5
%6()7 %+8//
0
−15 −10 −5 0 5 10 15
%6()9 %'6 Jitter (microseconds)
Figure 10. Jitter time between four CC2420 receivers
capturing the same transmission.
hase of var-
• Scalability: 32
33. nodes
as the maximum pair-wise error between any two nodes. We hardw
see the average error bound to within 2 ms and the worst- CC24
case error bound to within 6 ms. These data are also cap- We
tured in Figure 16 showing the distribution of error. During of me
drifte
To ac
100
that e
Average
Peak sage a
80
tion in
the m
60
aging
Percent
As the
40
must
shows
20 tocol
and a
0
0 1 2 3 4 5 6
Phase (milliseconds)
Figure 16. CDF of the average and max synchronization
error. Fig
33
