1. A DC-Invariant Gain Control Technique for CMOS Differential
Variable-Gain Low-Noise Amplifiers
Muh-Dey Wei#*1, Sheng-Fuh Chang#2 and Renato Negra*3
#
Department of Electrical Engineering, Department of Communications Engineering, Center for
Telecommunication Research, National Chung Cheng University
Chiayi, 62102, Taiwan
*Mixed-Signal CMOS Circuits, UMIC Research Centre,
Department of Electrical Engineering, RWTH Aachen University
Aachen, 52056, Germany
Email: 1muh-dey.wei@rwth-aachen.de, 2ieesfc@ccu.edu.tw, 3nerga@ieee.org
Abstract — A DC-invariant gain control technique is 3.5 GHz VG-LNA in 0.18 μm CMOS technology was
introduced for differential CMOS variable-gain low-noise implemented to validate the proposed technique.
amplifiers (VG-LNA). Such technique provides an advantage of
invariant DC bias current when the RF power gain is tuned over VDD
the gain control range. Therefore, the transconductance of
NMOS transistor is unchanged, which minimizes the input match
detuning. Consequently, the optimal design for noise, gain and C3 C6
OUT- C2 C5 OUT+
power linearity becomes easier to achieve. The implemented LL
0.18 μm CMOS VG-LNA shows a nearly constant DC current of
7.8±0.5 mA from a 1.5 V supply when the RF power gain is tuned VB2 R2 R3 R6 R5 VB2
from 0 to 12.3 dB at 3.5 GHz. Over this gain tuning range, the Cg1 Cg2
M2 M5
input return loss is almost unchanged around 11.5 dB. The
minimum noise figure is 2.59 dB and the input-referred P1dB is VC
DC-Invariant Gain
−4.5 dBm corresponding to the high gain (12.3 dB) situation. The Control Circuit
in-band gain flatness is as flat as ±0.2 dB. A very high FOM of
VB1 R1 R4 VB1
20.6 is obtained. A B
M3 C M6
IN+ C1 L1 L2 C4 IN-
M1 M4
I. INTRODUCTION
Cex LS Cex
Variable gain low-noise amplifiers (VG-LNA) are
indispensable to RF receivers for ever-growing high-data-rate
wireless communications, which have nature of a high
(a)
dynamic range of received signal strength. Various techniques iCA iCB
have been proposed for CMOS low-noise amplifiers to have VC
gain variation feature to accommodate the wide range of M3 M6
received signal strength. These include the control of bias A B
voltage [1]-[4], the change of output load or interstage
impedance [5]-[7], and the cascade of extra resistive-feedback
amplifier stage at output [8]-[9]. In the first two techniques, C
(b)
the bias current of the MOSFET amplification stage is
Fig. 1. Circuit schematic diagrams, (a) the proposed VG-LNA
changed when the gain is varied. This causes a change of (DC-bypass capacitors not shown) (b) DC-Invariant gain control
transconductance, which complicates the noise and gain match circuit.
over the entire gain control range. The third technique avoids
the DC current variation of the primary amplification stage by
incorporating the gain control on the third stage. II. CIRCUIT DESIGN
In this paper, a DC-invariant gain control technique is The schematic diagram of the proposed VG-LNA is shown
proposed, where a pair of NMOS transistors is connected in Fig. 1(a), which is a differential cascoded amplifier. The
across the differential nodes of cascoded LNA. As a result, the first cascoded pair of NMOS transistors M1 and M2 and the
DC bias current is unchanged over the gain control range. A second cascoded pair of M4 and M5 constitute the differential
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. amplification topology. The capacitor Cex across the gate- 15 10
source node reduces the gate-induced current noise [10] and
allows the simultaneous power-constrained noise and gain
match [11]. Due to using a triple-well process, the resistors R3 10 8
and R6 are connected to the body terminals of M2 and M5 to
Noise Figure (dB)
increase power gain [12]. The center-tapped spiral inductor Ls
Gain (dB)
W=60 μm
is used for source degeneration. The drain network, formed by 5 6
W=100 μm
the center-tapped spiral inductor LL with capacitors C3 and C6, W=140 μm
provides a shunt peaking effect for the enhancement of the W=180 μm
operation bandwidth and in-band gain flatness. W=220 μm
0 4
The DC-invariant gain control circuit is composed of the
MMOS transistor M3 and M6. If M3 and M6 are biased in the
deep triode region, they can be considered as variable
-5 2
conductors, written as 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Control Voltage (V)
Wv
Gds = K n (VGS − VTH ) (1) Fig. 2. Simulated gain and noise figure of a 3.5 GHz CMOS VG-
Lv LNA with respect to the gain control voltage.
where Kn is the device parameter, VGS is the gate-source The input return loss is 13 dB and the maximal power gain is
voltage, VTH is the threshold voltage, Wv and Lv are the gate 12.3 dB at 3.5 GHz. The in-band gain flatness is as flat as
width and gate length of the transistor. The conductance Gds is ±0.2 dB from 3.2 to 3.8 GHz and measured noise figure is
controllable by the gate voltage of M3 and M6. As illustrated 2.6-3.3 dB.
in Fig. 1(b), the DC voltages at node A and B are identical On the gain control and related performance, Fig. 6 and Fig.
due to the circuit symmetry so that no DC current flows 7 depict the measured results. The DC current is almost
through M3 and M6. This indicates that the gain control circuit constant at 7.8±0.45 mA when the control voltage VC is
is DC floating and hence consumes zero DC power. From the changed from 0.6 to 1.8 V. Reflection coefficient S11 is
RF signal point of view, the RF signals at node A and B are −11.5 dB±0.8 dB over the voltage control range. The small
180o out of phase and node C is indicated as a RF virtual variation of DC current and input return loss confirms the
ground. The amount of differential input signals can be decoupling of the RF gain control to the input impedance
shorted to the virtual ground by controlling the match. At 3.5 GHz the power gain is controllable from 0 to
transconductances of M3 and M5. Therefore, the total power 12.3 dB corresponding to VC = 0.6 to 1.8 V. The noise figure
gain can be controlled by VC without disturbing the DC bias is increased from 2.6 to 8.1 dB due to gain reduction. The
current. In turn, the transconductances of the cascoded NMOS measured input P1dB is −4.5 dBm and +7 dBm at the highest
transistors are unchanged while the gain is tuned. Therefore, and lowest gain, respectively.
the gain control is decoupled from the input impedance match. The measured results are summarized in Table I, and
This ensures that the conventional cascoded LNA design compared with other CMOS 0.18 μm VG-LNAs. A figure of
method is applicable over the entire gain tuning range. merit (FOM) for a fixed-gain LNA is defined by [13] as:
The size of M3 and M6 determines the gain variation range.
Different gate widths from Wv=60 to 220 μm are simulated. Gain[dB] ⋅ P dB [mW] ⋅ f [GHz ]
FOM = 1
(2)
The simulation results are shown in Fig. 2, where the gain PDC [mW] ⋅ ( F − 1)
variation range is increased with the gate width. For the case
of Wv =180 μm, the gain variation range is 12.5 dB. In this To better evaluate the variable-gain LNA, we propose a
range, the noise figure is changed from 2.5 dB to 7.8 dB, modified definition of FOMM with the inclusion of the gain
resulting from the gain reduction. control range and chip size, given as:
Gain[dB] ⋅ P dB [mW] ⋅ f [GHz ]
FOM M = 1
⋅ GR[ dB] (3)
III. MEASUREMENT RESULTS PDC [mW] ⋅ ( F − 1)
The designed 3.5 GHz VG-LNA was implemented in where GR denotes the gain control range. In Table I, both
0.18 μm CMOS technology. The microphotograph is definitions of FOM are calculated. Our VG-LNA has the
illustrated in Fig. 3, where the chip area is 1.2 mm2. The RF highest fixed-gain FOM of 1.67 and variable-gain FOMM of
performance was measured with a four-port vector network 20.6.
analyzer. The measured frequency responses are shown in
Fig. 4 and Fig. 5.

3. TABLE I
SUMMARY OF 0.18 μm CMOS VARIABLE-GAIN LNAS
P1dB Power
Freq. S11 Gain Vari. NF Chip Size FOM FOMM
Ref. Topology HG / LG Consump.
(GHz) (dB) Range (dB) (dB) (mm2)
(dBm) (mW)
[2] Single-ended 5.2 -13 0–20 3.5 -15 / N.A. 17 1.2 0.156 3.12
[4] Single-ended 5.5 -15 -19 − 19 3.1 -18* / N.A. 27 0.56 0.06 2.2
[5] Single-ended 5.75 < -7 10.9–21.4 4.4 -27.5 / -15.5* 16.2 0.3 0.007 0.008
[7] Fully-Differential 5.7 <-15 3.6 – 12.5 3.7 -11 / N.A. 14.4 1.4 0.29 2.6
[14] Fully-Differential 0.7 N.A. -6.5 – 15.5 5.8 -5.3 / +15* 6.5 0.03 0.35 7.8
This Work Fully-Differential 3.5 < -10 0 – 12.3 2.6 -4.5 / +7 11.2 1.2 1.67 20.6
*
calculated P1dB=IIP3-9 for evaluation
13.0 5.0
VC VDD
12.5 4.5
VB2 VB2
LL 12.0 4.0
Noise Figure (dB)
Out Out
Gain (dB)
Sim.
11.5 Gain (Meas.) 3.5
NF(Meas.)
11.0 3.0
L1 L2
10.5 2.5
LS
VB1 In+ Gnd In- VB1
10.0 2.0
3.2 3.3 3.4 3.5 3.6 3.7 3.8
Fig. 3. Microphotograph (1.16 × 1.05 mm2) Frequency (GHz)
Fig. 5. Simulated and measured noise figure and in-band gain
flatness.
15
10 0
10 S21 Sim.
Current (Meas.)
9 S11 (Meas.) -3
5
S-Parameters (dB)
Sim.
0 S21 (Meas.)
Current (mA)
8 -6
S11 (dB)
S11 (Meas.)
-5
S11 7 -9
-10
-15 6 -12
-20
5 -15
2.5 3.0 3.5 4.0 4.5
Frequency (GHz) 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Control Voltage (V)
Fig. 4. Simulated and measured S-parameters.
Fig. 6. Simulated and measured DC current and S11 versus
control voltage.

4. 15 10 Implementation Center (CIC), Taiwan, for chip
implementation.
10 8
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