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  1. 1. Radha Sree.K, Dr.R.Seyezhai / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.1416-1420 Design and Computation of Energy Factor Parameters for an Interleaved Boost Converter 1 Radha Sree.K, 2Dr.R.Seyezhai 1 Student, Department of EEE, 2 Associate Professor, Department of EEE SSN College of Engineering, Kalavakkam, Chennai - 603110Abstract Energy factor and the sub-sequential distortion (THD), ripple factor etc. They give a clearparameters best describe the characteristics of the picture of system stability, reference response andDC-DC converter and they are mainly used in interference recovery. They aid in converterstability studies as well as controller design. In this characteristics foreseeing and also in system design.paper, the computation of these parameters for a In this paper, energy factor and the other sub-3-phase interleaved boost converter (IBC) has sequential factors have been defined along with theirbeen described in detail. Also, the design of IBC significance. The parameters have been computed forhas been given importance. The values of the a 3-phase IBC and the values obtained are tabulated.parameters computed have been tabulated. The From, these parameters the Transfer function of thesimulation of the 3-phase IBC has been carried out converter can be devised, which is useful for studyingusing MATLAB/SIMULINK. the response of the system.Keywords – IBC, ripple, energy factor, transfer II. INTERLEAVED BOOST CONVERTERfunction.I. INTRODUCTION In order to overcome the drawbackassociated with the conventional converters such aslow voltage gain, some new topologies wereproposed as mentioned in [1]-[4]. One such topologyis the IBC, in which the input current is shared amongthe phases. This feature in turn results in highreliability and high efficiency. Besides characteristicssuch as efficiency and reliability the other systemcharacteristics such as maintenance, repair, faulttolerance [5] etc also improved. By virtue of IBC, thevoltage stresses on the switches are alleviated withsubsequent reduction in the input current ripple. IBC are employed in wide range ofapplications such as power factor correction circuits,fuel cell systems, photovoltaic arrays etc [6]-[8]. In Fig.1. Circuit of IBCthis paper, the design methodology of IBC has beenelucidated. The computation of the inductance and The circuit of the interleaved boost converterthe filter capacitance of the IBC have been done. The is shown in Fig.1.The interleaved boost converter isdesign of IBC has been carried out with the ultimate popular as the configuration, minimizes the currentobjective of reducing the ripple in the output voltage ripple thereby reducing the size of the input filter.and the input current. The input current also gets divided in the n-parallel The analysis of DC-DC converters was paths and this leads to reduction in stresses also.confusing because of the non-availability of the Higher efficiency is also realized. Moreover, theparameters to best describe the characteristics of the interleaving technique facilitates the reduction in theconverters. Study of energy storage in the converters size of the inductors employed.has gained a lot of attention in the recent years. To The gating pattern of the IBC is shown inmake the analysis simpler and to describe the Fig.2. The IBC is made up of N-parallel boostconverters characteristics, a new concept called the converters [9]. The operation of IBC is similar to thatenergy factor was introduced. With the introduction of the conventional boost converter. The number ofof energy factor and other sib-sequential parameters, inductors and diodes is same as the number of phases.the modeling of the converter has become simpler. The switching frequency of the 3-phase IBC is These parameters are entirely different from identical but the gating pattern of each phase isthe conventional ones such as total harmonic shifted by an angle 360/N, n denotes the number of 1416 | P a g e
  2. 2. Radha Sree.K, Dr.R.Seyezhai / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.1416-1420 phases [10]. In case of 3-phase IBC, the angle is 120º. where, Vs and Vo represent the input and the output 3-phase IBC is mostly preferred as the current ripple voltage respectively, D is the duty ratio, F is the can be reduced considerably. Interleaving technique switching frequency, R is the load resistance reduces the Electromagnetic interference (EMI); employed and ΔVo is the ripple in the output voltage. therefore, the size of the EMI filter also gets reduced Similarly, the inductance can be computed using [11]. equation (2), Gating pulse of switch S1 1 Vs DF (2) L= 0.5 ∆Il 0 0 1 -4 2 Where, ΔIl represents the ripple in the inductor x 10 current. 1Amplitude(V) D. Selection of power device 0.5 IGBT was used as the power device. IGBT 0 combines the gate-drive characteristics of MOSFET 0 1 2 -4 x 10 and also the high current low saturation voltage Gating pulse for switch S3 capability of bipolar transistors. Their high pulse 1 ratings and affordability makes them very popular. The conduction losses associated with the device is 0.5 less when compared to MOSFET. In general, they are 0 0 1 2 used in high voltage, high current and low switching Time(s) -4 x 10 frequency applications.Fig.2. Gating pattern of IBC. IV. ENERGY FACTOR AND SUB- III. DESIGN ASPECTS SEQUENTIAL PARAMETERS FOR IBC The design of IBC generally involves the The energy factor and the sub-sequential selecting the number of phases, duty ratio, inductors, parameters are elucidated in detail in this section. For power switches etc [12]-[13]. This requires a good the computation of these parameters the instantaneous knowledge of the peak currents. The inductors and input voltage and the current and the average values the diodes in all channels should be kept identical. are assumed to be v1(t), i1(t), V1, I1. Similarly the Designing the components in the power path is instantaneous output voltage and current and the similar to that of the single boost converter with average values are taken to be v2(t), i2(t), V2, I2. The which operates at 1/n times the power. various parameters are given by equations (3) to (14) [19]. A. Selection of number of phases It has been observed that the ripple in the A. Pumping Energy, PE input current decreases with increase in the number of In IBC, the transfer of energy from the phases. On the other hand, the cost and complexity of source to energy storage elements like inductor and the circuit also increases. So, a compromise had to be capacitor takes place with the help of the pumping made between them. In this paper, the number of circuit. Pumping energy is used to count the input phases was chosen to be three to reduce the ripple energy in a switching period T. content without increasing the cost drastically. T PE = Pin t dt (3) B. Selection of duty ratio 0 Duty ratio also aids in ripple reduction and T hence it has to be selected carefully. From the plot of = V1 i1 t dt 0 the input current ripple versus the duty ratio, it can be = V1 I1 T found that for an N-phase IBC, the ripple can be zero at particular values of duty ratio [14]-[16]. For a 3- B. Stored energy, SE phase converter, the ideal duty ratio at which the The energy stored in the inductor and capacitor is ripple is zero is 0.7. given by (4) and (5) respectively as: C. Selection of inductance and Capacitance 2 WL = 0.5 ∗ L IL (4) The value of the filter capacitor [17]-[18] to be employed can be computed using the equation (1), 2 Wc = 0.5 ∗ C VC (5) Vs DF (1) C= The total stored energy if there are n L inductors and R∆Vo nC capacitors is depicted in (6) 1417 | P a g e
  3. 3. Radha Sree.K, Dr.R.Seyezhai / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.1416-1420 nL nC SE = WL j + WC j (6) 2T ∗ EF (13) τ= (1 + CIR j=1 j=1 1 + CIR 1−ŋ ∗ )C. Capacitor – inductor stored energy ratio, CIR ŋThe DC-DC converters are composed of inductorsand capacitors. Therefore, CIR can be defined as: If there is no power loss in the converter, the nC j=1 WC j (7) efficiency, ŋ can be taken as one. CIR = n L j=1 WL j H. Damping time constant, τd The damping time constant also describesD. Stored energy variation on inductors and the transient process of the DC-DC converter. The capacitors, VE oscillation response for unit step or impulseConsidering the ripple in the inductor current, the interference can be estimated using this parameter. Itvariation of stored energy on the inductor is given by, is given as: ∆WL = LIL ∆iL (8) τd 2T ∗ EF CIR (14) Where, ∆𝑖 𝐿 is the ripple in the inductor = ∗ 1 + CIR ŋ + CIR(1 − ŋ)current. As the voltage across the capacitor hasvariation (ripple) ∆vC, the variation of the stored Ŋ=1 if there are no power losses in the converter.energy across the capacitor is: I. Time constant ratio, ξ ∆WC = CVC ∆vC (9) Also, used to analyze the transient process of the converter and is given as:Hence the total variation in the stored energy is: τd CIR VE ξ= = nL nC τ 1−ŋ (15) (10) ŋ(1 + CIR ŋ )2 = ∆WL j + ∆WC j j=1 j=1 CIR>1 and hence, when the power loss is higher, the time constant ratio gets smaller.E. Energy factor, EF Energy factor can be defined as the ratio of V. SIMULATION RESULTSstored energy (SE) over pumping energy (PE). Being The simulation of the three phase interleavedthe most important factor of the converter, it is boost converter was carried out usingindependent of k and is inversely proportional to the MATLAB/SIMULINK. The parameters of the circuitswitching frequency, f. are shown in table I. SE TABLE-I EF = (11) nL PE nC Parameters of the Interleaved boost converter j=1 WL j + j=1 WC j Parameters Values = V1 I1 T Inductance, L 1mH Capacitance, C 1000uFF. Variation energy factor, EFV Load Resistance, R 5 Ohms Energy factor and the variation energy Switching Frequency, f 10kHzfactors are mainly used to analyze the characteristics Duty Ratio, k 0.7of the converter. The variation energy factor can be Input Voltage, Vs 30Vdefined as the ratio of variation of stored energy over Output Voltage, Vo 99.13Vthe pumping energy. Voltage transfer gain, M 3.33 Inductor current, IL 21.11A VE (12) EFV = Input Current, I1 66.35A nL nC PE Load Current, I2 19.83A j=1 ∆WL j + j=1 ∆WC j = V1 I1 T The output voltage of the three phase IBC is shown in Fig.3. Voltage of magnitude 99.18V wasG. Time constant, τ obtained with k=0.7. The ripple in the output voltage The transient process of the converter can be was 0.111%described using the time constant. It is given as: 1418 | P a g e
  4. 4. Radha Sree.K, Dr.R.Seyezhai / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.1416-1420 140 The energy factor and the sub-sequential parameters 120 were computed for the proposed three phase IBC and the values obtained are shown in Table – II 100 TABLE-IIAmplitude(V) 80 Energy factor and sub-sequential parameters 60 Parameters Values 40 Pumping Energy, PE 0.19905J Stored energy in the 668.4mJ 20 inductor 0 Stored energy in the 5J capacitor -20 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Total stored energy, SE 5.6684J Time(s) Capacitor-Inductor 7.481 Fig.3. Output voltage of IBC stored energy ratio, CIR The ripple in the input current has been Time constant 733.6us analyzed for k>0.5 and k<0.5. The ripple in the input Damping time constant 4.65ms current for k<0.5 is shown in Fig.4. The input current Time constant ratio 6.3386 ripple for duty cycle of 0.4 was computed to be Variation in stored 0.1203J 0.9472%. energy in the inductor In order to minimize the ripple in the input Variation in stored `0.0110J current, k was chosen to be 0.7 for the three phase energy in the capacitor IBC. The percentage of ripple was computed to be Total variation in 0.37191J 0.2714. The input current ripple for k>0.5 is shown in stored energy, VE Fig.5. 27.65 Energy factor, EF 28.477 Variation energy 1.868 27.6 factor, EFV 27.55 VI. CONCLUSION In this paper, a 3-phase interleaved boostCurrent(A) 27.5 27.45 converter was designed with the aim of reducing the input current ripple. The results obtained revealed 27.4 that the current ripple was almost zero when IBC was operated with a duty ratio of 0.7. The energy 27.35 parameters were also computed for the 3-phase IBC. 27.3 The transfer function of the converter can be obtained using the computed values and further the response of 27.25 0.2998 0.2999 0.3 the converter for a step input can also be studied. Time(s) Fig.4. Ripple in the input current for k<0.5 REFERENCES 110.7 [1] Yungtaek Jang and Milan M. Jovanovic, “A New Two-Inductor Boost Converter with 110.65 Auxiliary Transformer”, IEEE Transactions on Power Electronics, vol.19, no.1, pp. 169- 110.6 175, January 2004. [2] P. J. Wolfs, “A Current Sourced DC-DC Current(A) 110.55 Converter derived via the Duality Principle from the Half-bridge Converter”, IEEE 110.5 Transactions Industrial Electronics, vol. 40, 110.45 no. 1, pp. 139-144, February 1993. [3] Roger Gules, L. Lopes Pfitscher and L. 110.4 Claudio Franco, “An Interleaved DC-DC Boost Converter with Large Conversion 110.35 Ratio”, IEEE International Symposium on Power Electronics, 2003, ISIE’03, vol. 1, 110.3 0.2998 0.2999 0.3 pp.411-416, June 2003. Time(s) [4] K. C. Tseng, T. J. Liang, “Novel highFig.5. Input current ripple for k>0.5 Efficiency Step-up Converter”, IEEE Proc. 1419 | P a g e
  5. 5. Radha Sree.K, Dr.R.Seyezhai / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.1416-1420 Electr. Power Appl., vol. 151, no. 2, pp. 182- Power Electronics, Washington, pp. 991- 190, March 2004. 997, 2009. [5] S. Kamtip, K. Bhumkittipich, “Design and [16] R. Seyezhai, “Design Considerations of Analysis of Interleaved Boost Converter for interleaved Boost Converter for Fuel-cell Renewable Energy Applications”, 9th Eco- Systems”, International Journal of Energy and Material Science Engineering Advanced Engineering Sciences and Symposium, May 2011. Technologies, vol. 7, no. 2, pp. 323-329, [6] A. Newton, T.C. Green and D. Andrew, 2011. “AC/DC Power Factor Correction using [17] P.Thounthong, P.Sethakul, S.Rael and Interleaving Boost and Cuk Converters”, B.Davat , “Design and implementation of 2- IEEE Power Electr. And Variable Speed phase interleaved boost converter for fuel Drives Conf, pp. 293-298, 2000. cell power source”, Int. Conf. Power [7] M. Veerachary, T. Senjyu and K. Uezato, Electronics, Machines, and Drives ,PEM , “Maximum Power Point Tracking of pp. 91–95, 2008. Coupled Inductor Interleaved Boost [18] M.Veerachary, T.Senjyu and K.Uezato, converter Supplied PV System”, IEEE Pro. “Modeling and analysis of interleaved dual Electr Power Appl., vol. 150, no.1, pp. 71- boost converter”, IEEE International 80, 2003. Symposium on Industrial Electronics, Vol. 2, [8] B. A. Miwa, D. M. Otten and M. F. pp 718 – 722, 2001. Schlecht, “High Efficiency Power Factor [19] Fang Lin Luo, Hong Ye, Muhammad Correction using Interleaving Techniques”, Rashid, “Digital Power Electronics and IEEE Proc. APEC’92, Boston, USA, vol. 1, Applications”, pp. 34-43. pp. 567-578, 1992. [9] M. T. Zhang, M. M. Jovanovic nad F. C. Lee, “Analysis and Evaluation of Interleaving Techniques in Forward Converters”, IEEE Transactions on Power Electronics, vol. 13, no. 4, pp. 690-698, July 1998. [10] Gyu-Yeong Choe, Hyun Soo Kang, Byoung- Kuk Lee, “Design Considerations of Interleaved Converters for Fuel-cell Applications”, Proc. of international Conference on Electrical Machines and Systems, pp.238-243, 2007. [11] Chris Bridge and Laszlo Balogh, “Understanding Interleaved Boundary Condition Mode PFC Converters”, Fairchild Semiconductor Power Seminar, pp. 1- 14, 2008-2009. [12] H.Xu, E.Qiao, X.Guo, X.Wen and L.Kong , “Analysis and Design of High Power Interleaved Boost Converters for Fuel Cell Distributed Generation System”, Int. Conf. IEEE Power Electronics Specialists Conference (PESC), pp. 140 – 145, 2005 [13] H.Kosai, S.McNeal, Austin Page, Brett Jordan, Jim Scofield and B.Ray, “Characterizing the effects of inductor coupling on the performance of an interleaved boost converter”, Proc. CARTS USA, pp. 237–251, 2009. [14] R.J.Wai and R.Y.Duan, “High step-up converter with coupled-inductor”, IEEE Transactions on Power Electronics, Vol. 20, No.5, pp. 1025-1035, 2005. [15] Laszlo Huber, T.Brian Irving and M.Milan Jovanović, “Closed-Loop Control Methods for Interleaved DCM/CCM Boundary Boost PFC Converters”, Int. Conf. IEEE Applied 1420 | P a g e