This document provides a summary of Kashif Sagheer's qualifications and work experience. It includes his personal details, education history with an MSc in Infotech from University of Stuttgart and BSc in Electronics from Mehran University of Engineering & Technology. His work experience includes positions at Frauhofer IBP, Advantest Europe, Institut für Machinenelmente, and Institut für Techniche Informatic where he worked on various embedded system and FPGA projects. He is interested in areas like embedded systems, FPGA programming, and digital system design.

1. KASHIF SAGHEER
Date of Birth: 14 Dec, 1985 Gender: Male
Address: 26D3.01 Allmandring 3, Stuttgart, 70569, Germany
Mobile: 017645810135
Email: st104782@stud.uni-stuttgart.de
Kashifsagheer@gmail.com
Available From: Immediately
Qualification:
M.Sc Infotech (major: embedded system) (June, 2016)
University of Stuttgart, Germany
B.E Electronics (Jan, 2004 –Dec,2007)
Mehran University of Engineering & Technology, Pakistan
Dissertation: Texture analysis of magnetic resonance calf images for automatic
classification of muscle aging:
The thesis aims at finding an optimal subset of features, for a given training data set, which
enables the automatic classification based on texture analysis TA and manifest their uses for
the problem of characterization and classification of calf muscle. For this purpose, we used a
set of 21 young and old people calf muscle T2-weighted magnetic resonance (MR) images.
These volunteers were of 19-75 years of age and underwent MR examinations.
Job Experiences:
Organization: Frauhofer IBP
Designation: Studenten Mitarbeiter (HIWI) (April, 2015 – June,2016)
• I am working on a software implementation of measuring of acoustic parameters. In order
to accomplish this task, I used LABWINDOWs tool from National Instrument
international.
Organization: Advantest Europe
Designation: Studenten Praktikum (Sep, 2014 – Feb, 2015)
• Design & Implementation of Microblaze processor based embedded system in Vivado
software. The embedded system is used to reconfigure & test the flash memory in case
of any fault occures in the memory as well as in Xilinx ultra-high performance FPGA’s
configuration scheme.
• Design & Implementation of Microblaze processor based embedded system with DMA
controller in Vivado software. The embedded system is used to transfer and control the
transaction between DDR2 to high speed lvds IO. The Artix 7 (AC701) evaluation board
is used for prototyping.

2. • To write Verilog code for LFSR and its instances to get appox 80% resource utilization for
Dynamic power estimation of Stratix V fpga board designed by Advantest layout design
group.
• To design and write VHDL code for a customize IP core in Vivado for bridging between
DMA ip and selectio ip.
Organization: Institut für Machinenelmente (Universität Stuttgart)
Designation: Studenten Mitarbeiter (HIWI) (Jun, 2014 – Aug, 2014)
Implementation of image processing algorithms in Matlab and C++ for detecting scratches on a
plane metal surface
Organization: Institut für Techniche Informatic (Universität Stuttgart)
Designation: Studenten Mitarbeiter (HIWI) (Oct, 2013 – Feb, 2014)
• Implementation of finite state machine for scan chain module
• Modification of degilent VHDL code for pc communication
• Software development in C++ for pc interface with FPGA kit
Organization: SUPARCO Pakistan
Designation: Design Engineer (Apr, 2008 - Aug, 2012)
• Design, development and programming of embedded system (general purpose On board
data handling)
• Embedded software development
• Digital system design on FPGA
• Signal integrity, crosstalk, electromagnetic interference and power analysis of electronic
boards
• Multilayer printed circuit board design in ORCAD and Altium
• Implementation of hardware and software (driver) for CAN communication bus, I2C, SPI,
RS422, RS232 for embedded hardware communication
Technical Knowledge
Softwares
Eclipse, Visual Studio, CANoe, Keil,
Mplab, SDK embedded development
tool, ASCET, CAN bus analyzer, Xillinx
ISE,
ModelSim, IAR, OrCAD,
Altium, Matlab, Labview, Labwindow,
Proteus, Pspice, Multisim and VIVADO.
Programming
Languages
Assembly, C/C++,
Java,
Python, CUDA,
OpenCL, Visual,
Basic, VHDL, Verilog
HDL, SystemC, ANSI
C.
Hardware
8051-Controller,PIC,AVR
Controller, ARM
Controller, 386 EX
embedded processor,
Spartan, Vertex and 7
Series FPGA’s, Zynq SOC.

3. Professional Trainings
• Advance HDL techniques for SOC (Advantest Europe)
• Zynq based SOC or embedded system hardware and software design (Advantest Europe)
• High performance RISC Processor design, synthesis and implementation (Universität
Stuttgart)
• High performance computing with graphic cards (Universität Stuttgart)
• Embedded system (Universität Stuttgart)
• Image Compression (Universität Stuttgart)
Area of Interests
• Embedded system hardware and software(C/C++)
• FPGA programming in VHDL or Verilog
• Digital system design and computer architecture
• Software development
Research and Publication
FRAM based TMR (triple modular redundancy) for fault tolerance implementation
(All Pakistan Technical Paper Competition COMSATS Institute of Information Technology, Lahore, Pakistan, April 19, 2011)
Language Skills
English: Professional proficiency
German: A2 Level
Urdu: Native language
Other Activities
Reading books, reading articles, cricket and football
References
Available upon request