The document discusses the benefits of using cloud computing for FPGA design, focusing on personal data centers to improve timing closure processes. It emphasizes the advantages of parallel processing to save time and enhance design iterations through secure, easy-to-use tools while detailing specific technical approaches and future developments. Additionally, it outlines next steps for expanding support for FPGA processes and invites feedback from users.

1. Cloud Computing for Chip Design
“What Can FPGA Designers Do With
Personal Data Centers?”
Harnhua Ng, Plunify Pte Ltd
October 14, 2011

2. Agenda
§ FPGA Design Data Center
§ Specific Areas of Note
§ FPGA Timing Closure
§ Current Approach
§ Demonstration
§ Cloud Approach
§ Going Forward
Page § 2

3. “Personal Data Center for FPGA Design”
Simulation
Routing/
Synthesis
Page § 3

4. Confidentiality, Ease of Use
Precedents: Foundry <-> foundry customer interaction
Audited Security
Standards
§ AES encryption
§ SSL transmission
§ Asymmetric keys
• Secure and Encrypted End-to-End Transfers
• Plugins to Existing Tools
• Distributed File Uploads / Downloads
Page § 4

5. FPGA Timing Closure
Current Limitations
Costly Delays
“Timing Experiments”
§ Case 1: Miss timing by a bit
§ Change a setting, repeat till
successful
§ Case 2 : Timing is way off
§ Back to drawing board – path
restructuring, pipelining etc.
N hrs per iteration
Drawbacks
M iterations - Takes time to re-iterate one at a time
- Usually at a later design stage
Total: N x M hours - Randomness: *Fingers crossed*
- Requires communication between “tools
people” and “design people”
≈ days, weeks…
Page § 5

6. Cloud Closure
Data Center Approach
§ Run iterations in parallel
§ Save time wasted from waiting for
each iteration
§ Save time on re-engineering the
design
§ Use generated results from iterations
to troubleshoot better
X servers
N hrs per iteration
Total: N hours
Page § 6

7. Design – OR1200 32-bit processor core
§ 32-bit RISC
§ Harvard architecture
§ 5-stage pipeline
§ Virtual memory
§ Basic DSP capabilities
§ Implemented in various
commercial ASICs &
FPGAs
Page § 7

8. Target Chip & Software
§ Altera Stratix III L50
§ 65-nm technology
§ Logic elements: 47.5K
§ Package: F780
§ Speed Grade: Commercial 2
§ Altera Quartus II
§ Version 10.0 SP1
Page § 8

9. Timing Problem
Timing Aspect Slack (ns)
Worst Setup Time -0.519
Page § 9

10. Cloud Approach
Run in Parallel
• Calculate various parameters
§ “Seeds”
§ Placement optimizations
§ Routing optimizations
§ Register-to-register timing
§ Effort levels
§ Schedule and run in parallel
Multiple parallel runs
Page § 10

11. Result: Timing Solutions Found
Set Timing Aspect Slack (ns)
19 Worst Setup Time 0.093
26 Worst Setup Time 0.011
Page § 11

12. EDAxtend Platform
Complete design tool flow
Cloud Test
Cloud Explore Cloud Closure
IP Libraries
Place Timing/ Design
Design
Simulate Synthesis and Power Rule
Entry
Route Analysis Checking
• Aldec Riviera Pro • Altera Quartus II • Magma
• Mentor Graphics • Simucad
Modelsim
• Sigasi HDT • Altera Quartus II • Altera Quartus II
• TransEDA
Cloud Compile - Cloud Collab
Page § 12

13. Next Steps
§ Support more FPGA processes
§ IP cores
§ Complementary tasks e.g. multi-vendor flows
§ Extend features to broader EDA tasks
§ E.g. Simulator,
DFM, Verification tools
Page § 13

14. Test Drive & Feedback
§ Web account: register at www.plunify.com
§ Desktop plugin: contact us at
tellus@plunify.com
§ What would you like to see in the cloud?
Page § 14

15. Cloud-Accelerated FPGA Design
§ Secure, easy to use
§ Demo: Timing closure
§ Shorten Time-To-Market
§ Reduce overheads and development
costs
Page § 15