The document discusses different types of programmable logic devices (PLDs), including SPLDs, CPLDs, and FPGAs. It describes SPLDs as the least complex PLDs containing around 200 logic gates. CPLDs can contain the equivalent of 2 to 64 SPLDs and are more complex than SPLDs. FPGAs have the greatest logic capacity, containing thousands to millions of logic gates. The document provides examples of SPLDs like PALs, PLDs, and PROMs and describes their AND and OR gate configurations. It also describes the architecture of CPLDs, which contain multiple programmable logic blocks and interconnects like SPLDs.

1. PLD’s
BY :
•Ahmed Ashraf
•Islam Ashraf
•Nour Gamal

2. Review
•Introduction
•Types of logic circuits
• Types of PLDs
•Types of SPLDs
•CPLD

3. Introduction
• Fixed function digital ICs are classified
according to their complexity.
• They are listed here from the least complex to the
most complex.
• For example :-
(SSI, MSI, LSI, VLSI and ULSI).

4. Fixed-Function Integrated Circuits

5. • In fixed function devices a specific logic function is
contained in the IC package when it is purchased
and it can never be changed.
• Another category of logic device is one in which
the logic function is programmed by user and,
in some cases, can be reprogrammed many
times.
• These devices are called programmable logic
devices or PLDs
Introduction

6. Logic Circuits
Standard Logic Circuits Programmable Logic Circuits
•Realize single
function or set of
functions,
once defined
and with no
possibility of
changing
•Contains great number of
standard logic circuits
•Possibility of realizing
many various functions
•Hardware can configure
any time user need to
only by programming

7. Type of PLDs
PLD
SPLD CPLD FPGA

8. PLD Logic Capacity
• SPLD
– about 200 gates
• CPLD
– Altera FLEX (250K logic gates)
– Xilinx XC9500
• FPGA
– Xilinx Vertex-E ( 3 million logic gates)
– Xilinx Spartan (10K logic gates)
– Altera

9. SPLD
• The least complex form of PLDs.
• Can typically replaced several fixed function SSI or MSI
devices and their connections.
• A typical package has 24 to 28 pins.
• A few categories of SPLD are listed below:-
- PAL (Programmable Array Logic)
- PLA (Programmable Logic Array)
- PROM (Programmable Read-Only Memory)

10. CPLD
• Much higher capacity than SPLDs, permitting more
complex logic circuits to be programmed into them.
• A typical CPLD is the equivalent of from 2 to 64 SPLDs
and come in 44 pins to 160 pin packages depending on
the complexity.
• There are several forms of CPLD, which vary in
complexity and programming capability.

11. FPGA
• Different from SPLD and CPLD.
• Have the greatest logic capacity.
• Consist of an array of anywhere from 64 to thousands of
logic gates groups that are sometimes called logic blocks.
• Two basics classes of FPGA are course grained and fine
grained.
• FPGAs come in packages ranging up to 1000 pins or more.

12. SPLD’sCompared
Type AND array connections OR array connections
• PROM
• PLA
• PAL
• Fixed at factory
• Programmable by customer
• Programmable by customer
• Programmable by customer
• Programmable by customer
• Fixed at factory

13. SPLDs
Fixed AND array
(decoder)
Programmable OR
array
Programmable
connections Outputs
Inputs
Programmable read-only memory (PROM)
Programmable
AND array
Fixed OR
array
connections
Programmable
Programmable array logic (PAL) device
Programmable logic array (PLA)
Programmable
AND array
Programmable
OR array
connections
Programmable
All use AND-OR structure- different in which is programmable
Inputs
Inputs
Outputs
Outputs
Programmable
connections

14. GeneralizedSPLD
Inverter buffer
Array of inputs And gates Or gates

15. ProgrammableSymbology

16. PROM
representation using gates simplified representation

17. PROM
Use a PROM to implement an:
•inverter F1 = A
•OR
•NAND
•XOR F4
F2 = A+B
F3 = A·B F4
= A B
A B F1 F2 F3 F4
0 0 1 0 1 0
0 1 1 1 1 1
1 0 0 1 1 1
1 1 0 1 0 0
Truth table is transferred directly
to the PROM grid.

18. PLA
representation using gates simplified representation

19. PLA
• AND array and OR array
are programmable
• XOR is available to
complement an output if
needed
• Example:
• 3 inputs/2 outputs
• F1 = A B’ + A C + A’ B C’
• F2 = (AC + BC)’

20. PAL

21. PAL
• Fixed OR array and
programmable AND array
• Opposite of ROM
• Feed back is used to support
more product terms
• AND output can not be shared
here!
Example:
4 inputs/4 outputs with fixed 3-
input OR gates
• W = A B C’ + A’ B’ C D’
• X = ?
• Y = ?
• Z = ?

22. CPLD
•PALs and GALs are available only in small sizes – equivalent to
a few hundred logic gates
•For bigger logic circuits, complex PLDs or CPLDs can be used.
•CPLDs contain the equivalent of several PALs/GALs – linked
by programmable interconnections – all in one integrated
circuit (IC)
•CPLDs can replace thousands, or even hundreds of thousands,
of individual logic gates – increased integration density

23. CPLD
•Some CPLDs are programmed using a PAL programmer,
but this method becomes inconvenient for devices with
hundreds of pins.
•A second method of programming is to solder the device
to its printed circuit board, then feed it with a serial data
stream from a personal computer.
• The CPLD contains a circuit that decodes the data
stream and configures the CPLD to perform its specified
logic function.

24. CPLD
•Each manufacturer has a proprietary name for its
CPLD programming system
•For example, Lattice calls it "in-system programming"
•However, these proprietary systems are beginning to
give way to a standard from the Joint Test Action
Group (JTAG)

25. CPLDArchitecture
• Simplified CPLD
architecture
• Small number of largish PLDs
(e.g., “36V18”) on a
single chip
• Programmable
interconnect between
PLDs
• Large number of I/O
blocks
• Large number of pins

26. CPLDArchitecture
• Generalized architecture for
a complex PLD
• Programmable Interconnect
Array – Capable of
connecting any LAB input or
output to any other LAB
• Logic Array Blocks
– Complex SPLD-like structure
• Input/Output Blocks

27. CPLDArchitecture
• Each of the SPLD-like blocks in a
CPLD can be programmed as
with a PAL or GAL
• Many SPLD-like blocks (e.g.,
LABs) are included in one CPLD
• LABs can be interconnected to
build larger logic systems

28. CPLD
• Composition of Complex PLDs
–typically composed of 2-64 SPLDs
–interconnected using sophisticated logic
–includes macrocells (more about these later)
–includes input/output blocks
• Economical for designing large systems
• Fast – switching speed

29. CPLD
• Complex PLD's have arrays of PLD's on one chip, with
an interconnection matrix connecting them.
• Timing performance can be more predictable than
FPGAs because of simpler interconnect structure.
• Density is normally less than most FPGAs (although
high end CPLDs will have about the same density as
low-end FPGAs).
• Performance of CPLDs is usually better than FPGAs,
but depends on vendor number of cells in CPLD, and
compared FPGA.

30. Thanks