The document provides a summary of various physical design problems Lee Johnson has solved using Tcl scripting in different EDA tool environments over several projects from the late 1990s to recent years. It lists solutions by project, including mesh clock routing flows in Cadence Innovus from 2015-2016, floorplanning and routing scripts for IBM chips from 1997-2015, and scripts addressing problems like pin placement, bus routing, and macro placement for other ASIC projects during the same period. It also provides examples of general utilities developed.

1. Lee Johnson Friday, November 25, 2016
PD Problems solved with Tcl
Prepared for: Lee Johnson
Prepared by: Lee Johnson
November 22, 2016
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LEE JOHNSON

2. Lee Johnson Friday, November 25, 2016
EXECUTIVE SUMMARY
Objective
To show my knowledge of Physical Design problem solving using Tcl language in various PD tool API environments
Goals
List solutions roughly by date, project, tool suite, etc.
Solution
I visited notes from projects as far back as the late 90s, recalling project-specific and general flows and utilities.
Project Outline
• List project-specific items from recent-to-past
• General solutions (utilities, etc) last
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LEE JOHNSON

3. Lee Johnson Friday, November 25, 2016
CADENCE - 2015-2016
Mesh Clock flow (the following list is not in the order of flow steps)
• Create mesh reserves, allocated resource for mesh stripes prior to other routing.
• Generate mesh stripes from a list of spine locations; while allowing for non-uniform power grid
• Given customer desired spacing between htree tap buffers, derive the x-y aspect, for the flexH tree command.
• Derive the power rails from the power plan, to allow for DRC-clean creation of stripes and shields.
• Script to build Htree given user parms (spacing, layers, etc)
• Script to create mesh net, connect to Htree and under-mesh buffering.
• Shield the mesh stripes with adjacent power voltage, or optionally opposite power voltage.
• Proc to traverse a buffer tree in breadth-first-search fashion, keeping track of levels, get pin arrivals , slews, etc.
Allows for existence of multi-driver net in the tree (mesh net). Uses dict data structure for gathering and
reporting.
• Layer preferences setup script; allows the flow to be use with any technology and layer stack, while managing
allocation of Htree and Mesh resources.
• Script to parse techLef directly for lower layer rules not accessible via dbGet.
• Cache the variables created during the flow, save with each db, so that restarting with that db can have the
associated flow variables.
• Call FlexH or CCOpt commands, set net or term properties appropriately during the flow.
• Create a routing ‘fence’ outside the core area, to prevent NanoRoute making crazy routes to the edge of the
design.
• dbGet wrappers (hide complexity of one or more dbGet commands, simplify calling script)
• Given pinList, get list of instances, or instance pointers
• Given a netName, get the source(s). (Can handle multi-driver net such as mesh drivers)
• Find all multi-driver nets in the design
• Given buffer or inverter output pin, find input (needed for tree traversal)
• Given buffer or inverter input pin, find output
• Given a net, find the root of the buffer/inverter tree driving the net.
• Given a sink pin, find the source pin driving the connected net
• Given an instance pin name, return the instance name
• Given an NDR (Non-Default-Rule) and layer, return the width defined in the NDR for that layer.
• Given a layer, run length , and width of an adjacent object, get the required run-length spacing
Favorite built-in Innovus commands
• dbShape, very reliable way to create DRC-clean shapes given existing shapes.
• dbSchema, best way to figure out what’s possible with dbGet.
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LEE JOHNSON

4. Lee Johnson Friday, November 25, 2016
Lacking:
I didn’t do any hierarchical work with Innovus while with Cadence.
IBM 1997-2015
(employed from 1984, logic design, timing, and other scripting languages)
P9 2013-2015 (both Skill and Tcl used. Skill in VirtuosoXL, Tcl in Finale Space Based Router)
• Pin placement utilities: Loads power plan specs, defines procs that allow legal pin placement even when power
grid hasn’t been drawn.
• Channelize pin region: Assign pins to legal channels based on top level design spec.
• Script to parse and load Virtuoso floorplan file into Finale.
• Proc to save net segments and vias in a tree data structure, allows for BFS traversal, can make ordered
modifications to net components.
• Utility to copy “mirrored” floorplan, allows one designer to create a reference floorplan, then is duplicated to
symmetric versions.
• Proc to interleave list elements, allows for sorting and placing bus pins. Works like a matrix transpose. Also re-
purposed to allow tools that place elements in row-first fashion to result in a column-first placement.
• Wiring demand estimation “calculators”: Based on engineered bus planning, allow for quick evaluation of
planning changes to bus layer and wire width allocation.
• Customize boundary pin dimensions based on bus plan (layer, density, etc.)
• Proc to check for nets’ Steiner routes crossing hard macros, helped debug wiring congestion caused by layer
constraints lower than the macro ceiling.
• Proc to parse a net NDR tagging file written from Virtuoso for use in Finale.
• Proc to find common nets connecting between a pair of instances (used for aligning partition interfacing pins).
• Proc to align interface pins based on one partition to another.
ASICS (VARIOUS CHIPS, INCLUDING XBOX-360, PPC4XX PROCESSOR CORES) 2003-2013
• Trim a clock net with non-uniform wire widths for performance.
• Parse nets from a checking log file, optionally ignoring certain nets.
• Proc to add a buffer chain between pins, evenly distribute between source and sink.
• Proc to create even spacing between a set of pre-placed instances.
• Various procs to support BonnPlace of PPC4XX datapath macros. The tool required a table of multi-row circuit
sizes such as to place as many as possible on the same row, aiding pin alignment and straight routing.
• Proc to automate placement of multi-bit (bit-stack) floorplan instances.
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5. Lee Johnson Friday, November 25, 2016
• Proc to directly create a routed DEF. (XBOX-306 chip, Warp Router couldn’t be used to route aligned pins.)
• Various scripts to align terminals between adjacent partitions.
• End-to-end flow for XBOX-360 PPC Unit.
• Assign nets to “buckets” based on length, to guide layer assignment.
• Utility to rename machine-generated nets by a human-readable heuristic, such as the source pin name.
• Utility to find all gater enables, for later optimization.
• Custom placement of PPC460 EU GPR array cells. (A new register file design didn’t have an abstract. So we
were provided with the flattened netlist. I create a script to place the cells in our floorplan, in the optimal fashion
according to the designer’s intent.)
CELL BROADBAND ENGINE PROCESSOR 2000-2003
• Create an end-to-end flow to ‘grow’ the L2 floorplan, proceed through buffering, routing and timing. Started
with new vhdl netlist, ended with routed design ready for timing. The flow took advantage of floorplan symmetry,
to transform rotation/mirroring of cells over main axes. (The L2 floorplan could been seen as 4 quadrants
containing local copies of the same macros, with symmetry in both X and Y directions.)
• Created a family of relative placement commands, allowed for a placement flow that was tolerant of changes in
custom macro dimensions. This included a “keep distance” proc, so that existing placement could be updated
to honor cell spacing constraints.
• Proc to visualize holes in rectangles of a large macro. Necessary to ensure buffer placement for routes that
straddle the large macro (L2 cache arrays. Maybe similar to dbShape … NOT… ).
• Various utilities to support flow scripts execution.
• Power planning/routing scripts.
•
ASICS (VARIOUS CHIPS, 1997-2000)
• Created a peripheral placement flow for a customer DDR interface. The flow was parameterized such that the
customer could rotate the floorplan based on the board and package design constraints.
• Custom shielding script for clock nets (needed in an early technology version for which shielded wire codes
were not provided).
• Script to check custom delay line balance.
GENERAL FLOOR PLANNING OR FLOW UTILITIES
• Create a list of integers from A to B
• Given a region, return true/false if a given point lies in the region
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6. Lee Johnson Friday, November 25, 2016
• Grid “snap” procs, given variables defining a floorplan, return value of input value snapped to the closest grid
value.
• Idle message proc, send a message to my (and/or others) email address when a long-running flow has
completed or has stopped.
• “Do not disturb” delay proc: for the idle message proc, compute a message transmitting delay interval, so that
the message isn’t sent during overnight hours.
• Prime factors: For creating an automated MxN array floorplan of an arbitrary number of elements, use prime
factorization of the total number of elements, to help choose how to fit the array in available floorplan space.
• Automation of tool control files from netlist data, or parsing existing files.
Favorite built-in commands
• dict data structure. Allows flexible storage, easier to change and maintain than simple lists
• tree_struct. Build and traverse trees
• regexp: Powerful for string and file parsing
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