ANALOG INTEGRATED CIRCUIT DESIGN Chapter 16 presented by Oveis Dehghantanha in University of Birjand

1. Nyquist-Rate
D/A Converters
1
Seyyed Mohammad Razavi, Associate Professor
Oveis Dehghantanha, PhD candidate
Faculty of Electrical and Computer Engineering, University
of Birjand, Birjand, South Khorasan, Iran
November 2019

2. 2
1. Decoder-Based Converters
1.1 Resistor String Converters
1.2 Folded Resistor-String Converters
1.3 Multiple Resistor-String Converters
1.4 Signed Outputs
2. Binary-Scaled Converters
2.1 Binary-Weighted Resistor Converters
2.2 Reduced-Resistance-Ratio Ladders
2.3 R-2R-Based Converters
2.4 Charge-Redistribution Switched-Capacitor Converters
2.5 Current-Mode Converters
2.6 Glitches
3. Thermometer-Code Converters
3.1 Thermometer-Code Current-Mode D/A Converters
3.2 Single-Supply Positive-Output Converters
3.3 Dynamically Matched Current Sources
4. Hybrid Converters
4.1 Resistor-Capacitor Hybrid Converters
4.2 Segmented Converters

3. 1. Decoder-Based Converters
3

4. 4
 Features:
 Only one path between resistor string and D/A output.
 Guaranteed monotonicity, provided that the voltage
follower does not have too large offset.
 Compact design when using only n-transistors.(no
contacts)
 Delay through switch network is the major speed
limitation of the circuit.
 2 𝑁
resistors are required.(when only one resistor string
is included)
Resistor String Converters

5. 5
 Resistor size:
 Choice of resistor size directly affects DAC maximum operating
speed.
 Power dissipation function of Vref 2
/ R × 2 𝑁
.
 Trade-off between speed and power dissipation.
 Resistor type:
 Choice of resistive material and technology is important.
 Diffusion type resistor results in:
1. high temperature and voltage coefficient
2. poor INL/DNL
 Better choice is PolySi resistor. (Lower temperature and voltage
coefficient about 1/3 to 2/3 and about half ,respectively compared
to diffusion resistors)
 Today thin film or metal resistors is used. (smaller parasitic
components, precise value and low temperature coefficient)
Resistor String Converters

6. 6 Resistor String Converters
 Features:
 High-speed implementation (compared to the previous
one) due to maximum of one switch in series.
 Less resistance through switches.
 The switches are controlled by digital logic.
 More area for the decoder compared to the previous
DAC.
 Larger capacitance on the buffer input, due to the 2 𝑁
transistors connected to it.
 Pipelining may be applied for “moderate speed” .
 2 𝑁
resistors are required.

7. 7 Folded Resistor-String Converters
 Features:
 Similar structure like what can be found in digital memories.
 Reducing size of digital circuitry and capacitive Loading.
(compared to the previous one)
 b1b2 : Most significant bits in the 4 bit case. (selects one single
word line.)
 Number of transistor junctions connected to the output line is
now 2 2 𝑁, instead of 2 𝑁
.(desired increase rate in speed)
 4 bit case: 8 instead of 16
 8 bit case: 32 instead of 256
 When a word line goes high, all the bit lines must be pulled to
new levels, it limits the desired speed. (no increase equal to the
ratio 2 2 𝑁 / 2 𝑁
).
 2 𝑁
resistors are required.

8. 8 Multiple Resistor-String Converters
 Features:
 A second tapped resistor string is connected between buffers
whose inputs are two adjacent nodes of the first resistor string, as
shown.
 In this 6-bit case the 3 MSBs determine the two adjacent nodes.
The 2nd “fine” string linearly interpolates between the two
adjacent voltages from the first “coarse” resistor string.
 Guaranteed monotonicity assuming matched OpAmps and voltage
insensitive offset voltages.
 OpAmps must be fast and low noise.
 Relaxed matching requirements for the 2nd resistor string.
 Only 2× 2 𝑁/2
resistors are required, so suitable for:
1. higher-resolution applications
2. low-power applications

9. 9 Signed Outputs
 Features:
 In applications where negative output voltages are
required, the bottom of the resistor string can be
connected to −𝑉𝑟𝑒𝑓, and it has some drawbacks like:
1. requiring a negative power supply
2. requiring the circuit to realize a dual power supply with
exactly matched voltages
 Switched-capacitor (SC) gain amplifier is viable solution.
 Negative output can be realized by changing the clock
phases of the input switches, so an inverting amplifier is
realized.

10. 2. Binary-Scaled Converters
10

11. 11 Binary-Scaled Converters
 Features:
 Binary-scaled D/A converters combine binary-weighted circuit
quantities. (currents, resistors, capacitors, etc.)
 Such techniques are generally :
1. hardware-efficient
2. potentially subject to significant nonlinearities
 Monotonicity is not guaranteed under such schemes.
 Largest DNL in the MSB changing is inevitable.

12. 12 Binary-Weighted Resistor Converters
 Features:
 Popular for a bipolar technology (bipolar differential pairs can
be used for current switches).
 We have:
Where
 Only N resistors are required.
 The resistor and current ratios are on the order of 2 𝑁
so:
 switches also are scaled because of current ratio.
 Monotonicity is not guaranteed.
 This approach is prone to glitches for high-speed operation.

13. 13 Reduced-Resistance-Ratio Ladders
 Features:
 The large resistor ratios in a binary-weighted array are reduced
by adding two series resistors.
 The current ratio has remained unchanged.
 By inserting 3R, VA is equal to one-fourth the reference voltage.
 Resistance seen to the right of the resistor 3R equals R, because
of adding 4R(to ground).
 It is binary-weighted too, but with one-fourth resistance ratio
compered to the previous binary-weighted case.
 This procedure is recursively repeatable to meet the R-2R ladder
structure.

14. 14 R-2R-Based Converters
 Features:
 Popular structure for achieving:
1. small number of components
2. resistance ratio of only 2 (independent of the number of bits)
 Analysis gives: and so on.
Thus for all is.
 This result gives the following current relationships:
, , and so on.
 Compared to binary-sized approach only 2:1 component ratios
are needed, and its outcomes are:
1. smaller size
2. better accuracy

15. 15 R-2R-Based Converters
 Features:
 For this 4-bit R-2R-Based D/A converter, we see that:
and
 The resistance ratio has been reduced, but the current ratio
through the switches is still large, so:
 the switch sizes are usually scaled in size to accommodate the
widely varying current levels.
 Down figure shows an approach to flow equal currents through
all the switches.
 This current ratio reduction occurs at the expense of some
voltage swings in the internal nodes of the R-2R ladder, which in
turns cause:
 slower configuration

16. 16 Charge-Redistribution Switched-Capacitor Converters
 Features:
 The basic idea is to simply replace the input capacitor of an SC gain amplifier
by a programmable capacitor array (PCA) of binary-weighted capacitors.
 Insensitive to input offset voltage, 1/f and finite OpAmp Gain.
 An additional sign bit can be realized by interchanging the clock phases
(shown in parentheses) for the input switches.
 Be careful in the clock generator design.
 C2: deglitching capacitor for reducing the clock feed-through.
 Φ1(precharge phase): C, 2C, 4C, 8C to Vref and 16C to Ground.
 𝑄𝑡 = 𝑉𝑟𝑒𝑓 𝑏18𝐶 + 𝑏24𝐶 + 𝑏32𝐶 + 𝑏4 𝐶
 Φ2(evaluation Phase): C, 2C, 4C, 8C to Ground and 16C to Out.
 𝑉𝑜𝑢𝑡 = −
𝑄𝑡
16𝐶
= −𝑉𝑟𝑒𝑓
𝑏18𝐶+𝑏24𝐶+𝑏32𝐶+𝑏4 𝐶
16𝐶
 𝑉𝑜𝑢𝑡 = −𝑉𝑟𝑒𝑓
𝑖=1
𝑛
𝑏𝑖
2 𝑛−𝑖 .𝐶
16𝐶
= −
𝑉 𝑟𝑒𝑓
16 𝑖=1
4
𝑏𝑖24−𝑖

17. 17 Current-Mode Converters
 Features:
 Current-mode D/A converters are very similar to resistor-
based converters.
 The upper portion of each current source always remains at
ground potential, so:
 this approach is intended for higher-speed applications.
 The basic idea is to switch currents to either the output or to
ground.
 The output current is converted to a voltage through the use
of RF.

18. 18 Glitches
 Features:
 Glitches are a major limitation during high-speed operation.
 Ideally, when a DAC output changes it should move from one
value to its new one monotonically. But in practice, the output is
likely to overshoot, undershoot, or both.
 The uncontrolled movement of DAC output from one value to a
new value during the transition is called as glitch.
 Glitch can arise from two mechanisms:
1. capacitive coupling of digital transitions to the analog
output.(frequently produces roughly equal positive and negative spikes
which cancel in the longer term.)
2. the effects of some switches in the DAC operating more quickly
than others and producing temporary spurious outputs.(generally
unipolar, much larger, and of greater concern.)

19. 19 Glitches
 Features:
 Glitches are mainly the result of different delays occurring when
switching different signals.
 Because of different current of branches, fully matching of these
two delays is highly unlikely.
 Possible solutions:
1. The glitch disturbance can be reduced by limiting the bandwidth
(by placing a capacitor across the resistor Rf, but this approach:
 slows down the circuit.
2. Another approach is to use a sample and hold on the output
signal.
3. Finally, the most popular way to reduce glitches is to modify
some or all of the digital word from a binary code to a
thermometer code.

20. 3. Thermometer-Code Converters
20

21. 21 Thermometer-Code D/A Converters
 Features:
 A thermometer-code D/A digitally recodes the input value to
a thermometer-code equivalent.
 A thermometer code differs from a binary one in that a
thermometer code has 2 𝑁
−1digital inputs to represent different
2 𝑁
digital values.
 Typically, in a thermometer-code representation, the number of
1s represents the decimal value.
 A thermometer-based converter does have advantages over its
binary counterpart, such as:
1. low DNL errors
2. reduced glitching noise (banks of resistors are never exchanged at
slightly different times when the output should change by only 1 LSB.)
3. guaranteed monotonicity (when the binary input changes to the next
higher number, one more digital value in the thermometer code goes high,
causing additional current to be drawn out of the virtual ground and
forces the OpAmp output to go some amount higher-never lower.)
𝑑1= 𝑏1 𝑏2 𝑏3 𝑑2= 𝑏1 𝑏2 𝑑3 =𝑏1(𝑏2 + 𝑏3)
𝑑4= 𝑏1 𝑑5 =𝑏1+𝑏2 𝑏3 𝑑6 = 𝑏1 + 𝑏2
𝑑7 = 𝑏1+𝑏2+𝑏3

22. 22 Thermometer-Code D/A Converters
 Features:
 Using a thermometer code does not increase the size of the analog
circuitry compared to a binary-weighted approach, since:
 the total resistors value of both is 7R, so each approach requires the
same area.
 By the same argument, the total area required by the transistor
switches in both is the same, because:
 all transistor switches in a thermometer-code approach are of equal
sizes since they all pass equal currents, ,but transistors are usually
size-scaled in binary-weighted designs to account for the various
current densities.
 It should be mentioned that a thermometer-code charge-
redistribution D/A can also be realized.

23. 23
Thermometer-Code Current-Mode D/A Converters
 Features:
 A current mode D/A Converter determines the output voltage by pulling
current from a number of cells.
 Thermometer-code decoders in both row and column decoding causes:
1. inherent monotonicity
2. low DNL errors
 The figure shows an 8x8 configuration (64 gradation) = 6bit resolution
 By simply increasing the gray sections, current pulled from R rises, and
Vout increase in negative.
 Thermometer code control prevents glitches from occurring at Vout.
 Off-chip 50Ω or 75Ω load is suitable for high speed.
 The delay to all switches (here M1,M2) must be equal to suppress
glitching.
 Cascade current sources are used here to reduce current-source
variation due to voltage changes in the output signal.

24. 24 Single-Supply Positive-Output Converters
 Features:
 To avoid the use of two logic driving levels, the gate of 𝑄2should
be connected to a DC bias voltage.
 A matched feedback loop is used to set up accurate known current-
source biasing.
 One side of each differential current-steering pair is connected to
𝑉𝐵𝑖𝑎𝑠 in order to:
 maintain accurate current matching that is independent of 𝑉𝑜𝑢𝑡.
 Cascade current sources are less affected by output voltage
achieving high accuracy.
 To maximize speed in this converter, the voltage swing at the
common connections of the current switches (for example 𝑄1,
𝑄2and 𝑄3) should be small.
 As a result, the output voltage range is reduced.

25. 4. Hybrid Converters
25

26. 26 Hybrid Converters
 Features:
 A hybrid converter combines different D/A architectures to
realize different portions of the converter design.
 Hybrid designs are an extremely popular approach for designing
converters because:
 they combine the advantages of different approaches.
 By using a thermometer-code approach for the top few MSBs
while using a binary-scaled technique for the lower LSBs:
1. glitching is significantly reduced .
2. accuracy is high for the MSB where it is needed most.
3. valuable circuit area is saved with a binary-scaled approach.

27. 27 Resistor-Capacitor Hybrid Converters
 Features:
 It is possible to combine tapped resistor strings with switched-capacitor
techniques in this way:
1. the top 7 bits determine which pair of voltages across a single resistor
is passed on to the 8-bit capacitor array.
2. the capacitor array then performs an 8-bit interpolation between the
pair of voltages.
 This approach gives guaranteed monotonicity, assuming the capacitor
array is accurate to only 8 bits.

28. 28 Segmented Converters
 Features:
 The segmented D/A converter is a popular example of a hybrid
converter.
 In 6-bit segmented D/A converter shown in Figure:
1. the two MSB currents are obtained in one segment from three
equal current sources using thermometer coding. (High bits are
switched to the output, whereas low bits are switched to ground.)
 The use of a thermometer code for the MSB currents greatly
minimizes glitches.
2. for the four LSBs, one additional current source from the MSB
segment is diverted where it is divided into binary-weighted
currents, which are also switched to either ground or the output.
 Accuracy requirements of four LSBs are very relaxed.

29. 29
Thank You
For Your Attention