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1. IEEE TRANSACTIONS ON POWER ELECTRONICS
Quasi-Single-Stage Current-Fed Resonant AC-DC Converter
Having Improved Heat Distribution
Waqar Uddin, Tsegaab Alemayehu Wagaye, Student Member, IEEE, and Minsung Kim, Senior Member, IEEE
Abstract— This paper presents a quasi-single-stage current-
fed resonant ac-dc converter having improved heat distribution.
Secondary-side switches are turned off with the voltage closed
to zero at high instantaneous power and with the voltage
closed to the half of the output voltage at low instantaneous
power. Switching losses at the primary-side bottom switches
are reduced; this change improves the heat distribution over
the switches. The primary-side duty-cycle fixed at 0.5 results in
negligible input current ripple; this trait can significantly reduce
the size of filter inductor at the grid side. Experimental results
show the effectiveness of the proposed ac-dc converter and its
improved heat distribution against a conventional solution.
Index terms - Zero voltage switching, high efficiency, heat
distribution, zero current ripple.
I. INTRODUCTION
Ac-dc power converters to connect the ac grid to var-
ious dc loads are essential equipment for modern indus-
trial applications. In compliance with IEC 61000-3-2, ac/dc
power converters are imposed to meet high power factor
(PF) and low total harmonic distortion (THD) to achieve
high power quality on the utility grid. The current trend
toward energy-saving and compact power electronics has also
emphasized the high efficiency, high power density, and cost-
effectiveness.
Commercialized single-phase ac-dc converters have been
widely adopted two-stage ac/dc architecture because of
its straightforward implementation. In this architecture, the
front-end ac/dc converter uses a diode bridge followed by a
boost cell, and shapes the input current close to a sinusoidal
waveform that is in phase with the grid voltage. Second-stage
dc/dc converters are developed in numerous topologies such
as LLC [1–4], CLLC [5], and phase-shift full-bridge [6–9];
it provides the galvanic isolation and good output voltage
regulation. However, the use of separately-designed stages
and bulky dc-link capacitor increase the cost and the size of
the two-stage ac/dc converter.
A cost-effective approach to reduce the number of the
power components is to use quasi-single-stage architecture.
Quasi-single-stage converters consist of a full-bridge diode
rectifier and a high-frequency dc–dc converter. These con-
verters eliminate a front-end boost stage and realize the boost
function by using the high-frequency dc-dc converter. To
operate the circuits at medium power capacity, full-bridge
Manuscript received Jul. 16, 2021; revised Oct. 18, 2021, Dec. 22, 2021,
and Mar. 28, 2022; accepted Jun. 9, 2022. This research was supported
by the National Research Foundation of Korea (NRF) grant funded by
the Korea government (MSIT) (No. 2021R1C1C1004276) (Corresponding
author: Minsung Kim.)
W. Uddin is with Department of Electrical Engineering, National Univer-
sity of Technology, Islamabad, 44000, Pakistan (waqar9895@gmail.com)
T. A. Wagaye and M. Kim are with the Division of Electronics and
Electrical Engineering, Dongguk University, Seoul, 04620, South Korea (e-
mail: tsegaab@dgu.ac.kr; mkim@dgu.ac.kr).
based topologies are widely adopted for quasi-single-stage
ac/dc converters. Quasi-single-stage ac/dc converters that use
dual-active-bridge topology have been proposed [10–13].
They provide bidirectional power flow, simple control, and
soft switching operation. However, it requires four secondary-
side switches, which increases the development cost of the
converter. To reduce the cost, a quasi-single-stage ac/dc con-
verter that uses dual-half-bridge topology has been developed
[14]. It uses small number of active power components.
However, the soft switching region is narrow, so this design
has limited power conversion efficiency under wide variation
of the grid voltage. As an alternative to the two-level full-
bridge based one, quasi-single-stage three-level ac/dc convert-
ers have been proposed [15–17]. Three-level topology keeps
the blocking voltage of each power components at half of
the grid voltage. A decrease in blocking voltage in a switch
usually decreases the drain-source resistance; and thereby
reduces the converter’s conduction loss. Also, half of the
grid voltage is applied to the switch at switching instants,
so the switching loss is reduced. Despite these efforts, the
aforementioned quasi-single-stage converters are the voltage-
fed type, so these converters require a large size passive
filter; this trait can reduce the power density of the converter.
To address this drawback, quasi-single-stage current-fed full-
bridge converters have been presented [18–21]; they deploy
the input inductor at the grid side, which provides low-
input current harmonics, and reduces the size and cost of
the passive filter inductor at the grid side. However, bottom
switches at the primary side suffer from hard switching loss
at turn-on and turn-off instants. To lessen the switching loss,
a quasi-single-stage current-fed resonant converter has been
proposed [22]. Resonant power transfer naturally enables
zero-current-switching, and so reduces the switching loss at
the turn-off instant. Nonetheless, current flowing through the
input inductor generates larger switching loss at the bottom
switches at the primary side than at top switches at the
primary side. The unbalanced heat distribution complicates
the task of designing the heat sink design. Furthermore, when
the grid voltage deviates from nominal voltage, this converter
enters to asymmetric above resonance mode and its grid
current becomes severely distorted.
In this paper, a quasi-single-stage current-fed resonant ac-
dc converter having improved heat distribution is proposed.
The current doubler with active clamp circuit is used at
the primary side and active voltage doubler circuit with
bidirectional switch on the secondary side. Utilization of
the bidirectional switch provides turn-off with the voltage
close to zero at high instantaneous power and turn-off with
the voltage close to the half of the output voltage at low
instantaneous power. Moreover, the switching loss at the main
switch is reduced, which improves the heat distribution, so the
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

2. IEEE TRANSACTIONS ON POWER ELECTRONICS
(a)
(b)
Fig. 1. Circuit diagram of current-fed ac/dc converters. S0j0 , Ds0j0 , Cs0j0
(j = 1, ..., 6): equivalent models of the switches; Dr: diode bridge rectifier;
T: transformer with turns ratio n=Ns/Np, where Np is the number of
primary side winding turns, and Ns is the number of secondary side winding
turns; Lm: magnetizing inductor; Lr: resonant inductor; L1 and L2: input-
side inductors; Cc: clamp capacitor; Cr1 and Cr2: resonant capacitors; Co:
output capacitor; vg: grid voltage; vin: input voltage; Vo: output voltage;
vcr1 and vcr2: voltage across Cr1, Cr2; VCc: voltage across Cc; iin:
input current; io: output current; iL1 and iL2: current through L1, L2;
vpri: primary-side voltage of T; vsec: secondary-side voltage of T; iLm:
magnetizing current; iLr: current through Lr; iS0j0 : current through Sj, Rl:
Load resistor. (a) Proposed ac-dc converter. (b) Conventional ac-dc current-
fed converter [22].
thermal management system can be minimized. Furthermore,
the primary-side switches operate with 50% duty-ratio, which
makes the input current ripple negligible regardless of the
variations in grid voltage and load; this aspect dramatically
reduces the size of the filter inductor at the grid side. The
proposed converter operation is experimentally verified by
designing and testing a 1-kW prototype.
The structure of the paper is organized as follows. Section
II explains the circuit topology and its operation principle.
Section III discusses steady state operation of proposed
converter and Section IV presents its control structure. Sec-
tion V details the switching loss of the proposed converter
and Section VI addresses its design guideline. Section VII
describes experimental validation. The paper is concluded in
Section VIII.
II. CIRCUIT OPERATIONS
The proposed current-fed converter (Fig. 1a) is composed
of a diode rectifier, a current doubler with an active clamp cir-
cuit and a resonant circuit plus a bidirectional switch isolated
with a transformer T. On the primary side of T, the converter
uses a current doubler circuit with an active clamp circuit
composed of input inductors (L1, L2), a clamping capacitor
Cc, four switches (S1, S2, S3, S4). On the secondary side
of T, the converter uses an active voltage doubler circuit
composed of a resonant inductor Lr, two resonant capacitors
(Cr1, Cr2), a bidirectional switch (S5, S6), and two diodes
Fig. 2. Waveforms of proposed ac/dc converter during a grid cycle. Tg is
a grid period.
(D1, D2).
The complementary pulse-width modulation (PWM) signal
with primary-side duty ratio of DpTs=0.5Ts and necessary
dead-time td is applied to the switches in pairs (S1, S4)
and (S2, S3). The PWM signal with secondary-side duty-
ratio of (Ds + 0.5)Ts and phase-shift of 180◦
is applied to
the bidirectional switches at the secondary side. The duty
of bidirectional switches is manipulated to control the input
current and output voltage of converter. Compared to the con-
ventional current-fed converter [22] (Fig. 1b), the proposed
current-fed converter features improved heat distribution over
the switches. Primary-side duty-cycle fixed at 0.5 makes the
input current ripple become negligible. Moreover, the circuit
experiences low switching loss because the secondary-side
switches are turned off with the voltage close to zero at high
instantaneous power and are turned off with the voltage close
to Vo/2 at low instantaneous power (Fig. 2).
The operation of proposed converter is analyzed under the
following assumptions for simplification.
1) Switch Sj (j = 1, ..., 6) is modeled as a junction capacitor
Cs0j0 and a body diode Ds0j0 .
2) The capacitance of clamp capacitor Cc is considered to be
large enough so that the voltage across the clamp capacitor
VCc has a constant value.
3) The capacitance of output capacitor Co is assumed to
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

3. IEEE TRANSACTIONS ON POWER ELECTRONICS
be large enough to neglect the voltage ripple at the output
voltage Vo.
4) Transformer T is modeled as a magnetizing inductance
Lm and its leakage inductance. The leakage inductance is
considered to be connected in series with resonant inductance
Lr.
5) The resonant capacitors Cr1 and Cr2 are identical; thus,
Cr1 = Cr2 = Cr.
6) The input inductors L1 and L2 have same characteristics;
thus, L1 = L2 = L.
The operation of proposed topology is divided into four
modes (Fig. 3). Due to symmetric operation, the modes are
analyzed during the first half switching period (Fig. 4).
A. Mode Analysis
Mode 1 [t0, t1]: At time t0, S1, S4, and S5 are turned on
with zero-voltage-switching (ZVS), and S6 is already turned
on before S1, S4, and S5 are turned on. vpri = −VCc is
transferred to secondary side of T. Then, vsec = −nVCc is
applied to Lr, and so iLr
increases linearly in the negative
direction. The mathematical expression can be written as
Lr
diLr
dt
= −nVCc, (1)
with iLr(t0)=0.
Solving (1) yields
iLr(t) =
−nVCc
Lr
(t − to). (2)
At this instant, the capacitor voltage is given as
vcr1(t) =
Vo
2
+ ∆Vcr, (3)
when ∆Vcr is the ripple of the resonant capacitor voltage.
The operation of converter follows the trajectory from A1
to B1 (Fig. 5).
Mode 2 [t1, t2]: At time t1, S6 is turned off at t1 with low
voltage. −nVCc is applied to the resonant tank. Then, iLr
starts to flow sinusodially. The mathematical expression is
given as
Lr
diLr(t)
dt
= −nVCc − vcr1(t) + Vo, (4)
iLr(t) = Cr1
dvcr1(t)
dt
− Cr2
dvcr2(t)
dt
. (5)
Vo = vcr1(t) + vcr2(t), so (5) can be written as
iLr(t) = Cr1
dvcr1(t)
dt
− Cr2
d(Vo − vcr1(t))
dt
= 2Cr1
dvcr1(t)
dt
. (6)
The differential equations (4) and (6) are solved for iLr
and vcr1 using initial conditions vcr1(t1)=−nVCc +
Vo + r1 cos α and iLr(t1)=− r1
Zr
sin α where
α=sin−1
−nVCcZr
Lrr1
(t1 − t0)
and r1=Vo
2 + ∆Vcr − nVCc
is the radius of the circular path centered at (−nVCc + Vo,
0) (Fig. 5); the result is
vcr1(t) = −nVCc + Vo + r1 cos[α + ωr(t − t1)], (7)
iLr(t) = −
r1
Zr
sin[α + ωr(t − t1)]. (8)
(a)
(b)
(c)
(d)
Fig. 3. Equivalent circuits of the proposed ac/dc converter during the first
half of the switching period. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode
4.
The angular resonant frequency ωr and characteristic
impedance Zr can be calculated as
ωr =
1
p
Lr(Cr1 + Cr2)
, Zr =
s
Lr
(Cr1 + Cr2)
. (9)
The operation of converter follows the trajectory from B1 to
A2 (Fig. 5).
Mode 3 [t2, t3]: At time t2, the resonance formed by Lr, Cr1
and Cr2 comes to its end at t2. iLr=0 and vcr1 is discharged
to its minimum value. Also, the current through D1 becomes
zero, and so D1 does not suffer from the reverse recovery
problem. In this mode, iL1 follows a positive slope while
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

4. IEEE TRANSACTIONS ON POWER ELECTRONICS
Fig. 4. Theoretical waveforms of the proposed ac/dc converter. vgs0j0 : the
gate-source voltage of the j-th switch (j=1,...,6).
iL2 follows a negative slope as
iL1(t) =
vin
L1
, (10)
iL2(t) =
vin − VCc
L2
, (11)
while vin = |vg|. The trajectory at this mode stays at A2
(Fig. 5).
Mode 4 [t3, t4]: At time t3, the switching state of S1 and
S4 has changed from on to off. The current flowing through
Ds2 and Ds3 discharges Cs2 and Cs3. Hence S2 and S3 are
Fig. 5. State-plane trajectory of the proposed ac/dc converter.
turned on with ZVS. The trajectory path is the same as in
Mode 3.
III. STEADY-STATE ANALYSIS
A. Voltage Conversion Ratio
Applying the voltage-second balance law to L1 = L2
during a switching period yields
vinDpTs + (vin − VCc)(1 − Dp)Ts = 0. (12)
Substituting Dp = 0.5 into (12) and rearranging it yield
VCc = 2vin. (13)
To obtain the gain of proposed converter. the ripple of the
resonant capacitor voltage ∆Vcr needs to be calculated first.
The voltage doubler on the secondary side of T operates in
symmetrical way during the steady state, so half of average
current that flows through resonant inductor iLr
during the
interval [t1 − t2] is delivered to the output load. Hence, the
average output current Io can be written as
Io =
2
Ts
Z t2
t1

8. −
r1
2Zr
sin[α + ωr(τ − t1)]

12. dτ
=
1
TsZrωr
[r1(1 + cos α)] =
2∆Vcr
TsZrωr
=
2Cr∆Vcr
Ts
. (14)
Solving (14) for ∆Vcr yields
∆Vcr =
PoTs sin2
(ωgt)
VoCr
. (15)
where Po is the rated output power.
Then by applying (t1 − t0)=DnTs (Fig. 4) with nominal
duty-ratio Dn to (2) and from (3), iLr(t) and vcr1(t) at t1
are calculated as
iLr(t1) =
−2nvin
Lr
DnTs, (16)
vcr1(t1) =
Vo
2
+ ∆Vcr. (17)
The circle equation centered at (−nvin + Vo, 0) and radius
r1 (Fig. 5) is described as
(vcr1(t) + 2nvin − Vo)2
+ (ZriLr(t))2
= r2
1. (18)
Substituting Eqs. (16) and (17) into (18) yields
Dn =
1
nVrms
s
LrPo
Ts
1 −
1
M
, (19)
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

13. IEEE TRANSACTIONS ON POWER ELECTRONICS
Fig. 6. Normalized input-current ripple of double current-fed converters
according to the primary-side duty-cycle variation. Red dotted line: current
ripple of each inductor; blue solid line: ripple of input current; red dot:
current ripple when Dp=0.5.
where Vrms is root-mean-square (RMS) value of vg and
M= Vo
4nvin
is the voltage gain of the proposed converter.
B. Input-Current Ripple
The current ripples of input inductors L1 and L2 in
switching frequency fs is described as
∆iL1 = ∆iL2 =
vinDp
Lfs
(1 − Dp), (20)
∆iin =







vinDp
Lfs
(1 − 2Dp), if Dp ≤ 0.5
vinDp
Lfs
(2Dp − 1), if Dp 0.5
. (21)
Dp affects normalized ∆iL1,2 and ∆iin (Fig. 6). The
current ripple of each inductor varies from 0 to 1 under
the variation of Dp. iL1 and iL2 are 180◦
phase shifted
and can generate the input current with reduced ripple.
When Dp = 0.5, iL1 and iL2 will cancel each other out
and will result in ripple free current; i.e., ∆ii ≈ 0. In
the proposed converter, the primary switches (S1, ..., S4) are
operated with 50% duty ratio and so the proposed converter
naturally obtains a ripple-free current. Meanwhile, the duty
of secondary-side bidirectional switches is manipulated to
achieve the desired input current and output voltage.
IV. CONTROLLER DESIGN
The control algorithm (Fig. 7) has a dual-loop structure.
The inner loop is used to control the grid current ig, while the
outer loop regulates the output voltage Vo of proposed ac/dc
converter. The outer loop computes the desired peak current
Iref
g,pk for given output power Po. Then Iref
g,pk is multiplied by
| sin ωgt| and generates iref
g . The inner loop calculates the
difference of iref
g and ig; the error ei is fed to proportional-
integral (PI) controller. The PI controller generates a desired
duty-ratio which will be applied to the switches. To reduce
the burden on the PI controller, the feed-forward nominal
(a)
(b)
Fig. 7. Controller configuration of the proposed ac/dc converter; PLL stands
for phase-locked-loop. (a) Controller. (b) Switching modulation.
duty term from (19) is used. The complete control duty D
for bidirectional switches is given as
Ds = Dn + Dc (22)
where Dc is the output of PI controller and Dn is the nominal
duty-ratio, which can be obtained from (19). As a result, the
proposed controller makes ig in phase with vg for achieving
almost unity power factor. Meanwhile, it maintains the output
voltage at the desired output voltage Vo,ref .
V. SWITCH LOSS ANALYSIS
A. Switching Loss
The switches in the proposed converter are turned on with
ZVS. The diodes are turned on/off with zero current. There-
fore, only switching losses at turn-off instant are calculated.
The total switching losses can be represented as
Psw−total =
n
X
j=1
Psw,S0j0 =
n
X
j=1
Poff,S0j0
= vds off,S0j0 · is off,S0j0 ·
toff,S0j0
2Ts
, (23)
where Psw,S0j0 is the switching loss of the j-th switch
(j=1, ..., 6). vds off,S0j0 is the voltage across the j-th switch
at the turn-off instant. is off,S0j0 is the current flowing
through the j-th switch at the turn-off instant, and toff,S0j0
is the turning-off time of the j-th switch.
In the proposed ac/dc converter, switching losses at S1 and
S2 are the same. Thus,
Psw,S1 = Psw,S2 = Poff,S1, (24)
with
Poff,S1 = 2vin ·
vin
L1
−
n2
VCc
Lm
·
toff,S1
Ts
. (25)
Similarly, the switching losses of S3 and S4 are
Psw,S3 = Psw,S4 = Poff,S3, (26)
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

14. IEEE TRANSACTIONS ON POWER ELECTRONICS
Fig. 8. Turn-off switching losses of the ac/dc converters. Prop. and conv.
stand for proposed and converter, respectively. (a) When vg=175 Vrms. (b)
When vg=220 Vrms. (c) When vg=265 Vrms.
with
Poff,S3 = 2vin ·
−vin
L1
+
n2
VCc
Lm
·
toff,S3
Ts
. (27)
The switching losses of S5 and S6 are
Psw,S5 = Psw,S6 = Poff,S5, (28)
with
Poff,S5 =
Vo
2
− ∆Vcr
·
r1
2Zr
sin(ωrDsTs) ·
toff,S5
Ts
.
(29)
Fig. 9. Conduction losses of the ac/dc converters. (a) When vg=175 Vrms.
(b) When vg=220 Vrms. (c) When vg=265 Vrms.
B. Conduction Loss
The total conduction loss Pcd−total can be obtained as
Pcd−total =
n
X
l=1
Pcd,S0l0 +
n
X
m=1
Pcd,D0m0 + Pcd,Dr
= I2
S0l0 Rds0l0 + VD0m0 ID0m0 + VDrIDr, (30)
where Pcd,S0l0 is the conduction loss of the l-th switch
(l=1,...,6), Pcd,D0m0 is the conduction loss of the m-th diode
(m=1,2), and Pcd,Dr is the conduction loss of the rectifier
diode; IS0m0 is the RMS current flowing through S0m0 and
Rds0m0 is the on-state resistance of S0m0 ; VD0m0 is the
forward voltage of D0m0 and ID0m0 is the average current
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

15. IEEE TRANSACTIONS ON POWER ELECTRONICS
TABLE I
PEAK CURRENT STRESS AND VOLTAGE STRESS ON THE SWITCHES OF
THE PROPOSED AC/DC CONVERTER
Switch
Current /
Values
Voltage
S1, S2
IS1,2 peak
n2
vin,peak
2fs
·
1
Lr
−
1
Lm
+
vin,peak
4fsL1
VS1,2 peak 2vin,peak
S3, S4
IS3,4 peak
nvin,peak
2fs
·
1
Lm
−
1
Lr
−
vin,peak
4fsL1
VS3,4 peak 2vin,peak
S5, S6
IS5,6 peak
2nvin,peakDs
fsLr
VS5,6 peak Vo/2 + ∆Vcr,peak
D1, D2
ID1,2 peak
n2
vin,peakTs
2Lr
VD1,2 peak Vo
Dr
IDr peak iin,peak
VDr peak vin,peak
flowing through D0m0 ; VDr is the forward voltage of Dr and
IDr is the average current flowing through Dr.
The switching and conduction losses (Fig. 8) of the con-
verters vary over half cycle of different grid voltages. Note
that the switching and conduction losses of the conventional
converter in [22] are obtained only when vg=220 Vrms
because the grid current of the converter in [22] was highly
distorted when vg=175 Vrms or vg=265 Vrms. This will
be discussed in Section VII in detail. When vg=220 Vrms,
the primary-side bottom switches in [22] experience high
switching loss as in Fig. 8b. In contrast, the main-switching
action occurs at the secondary-side switches in the proposed
converter, and so its primary-side bottom switches experience
reduced switching loss. Moreover, secondary-side switches of
the proposed converter experience low switching loss because
they are turned off with the voltage closed to zero at high
instantaneous power and with the voltage closed to the half
of the output voltage at low instantaneous power. As a result,
heat management is facilitated in the proposed converter. The
conduction loss mainly occurs at the diodes due to the high
forward voltage drop at the diodes (Fig. 9).
VI. DESIGN GUIDELINE
A. Input Inductance Design
The inductor current ripple ∆iin is highest at vin,peak.
Then, the peak of the inductor current ripple ∆iin,peak should
be more than average inductor current Iin to guarantee ZVS
turn-on for S1 and S2 under the grid voltage variation
∆iin,peak =
vin,peak
4Lfs
≥
2Po
ηvin,peak
= Iin,peak, (31)
where Po is the output power, Iin,peak is the peak of the
average input current, and η is the efficiency of the converter.
Solving (31) for L yields
L ≤ Lcrit =
ηv2
in,peak
8Pofs
, (32)
where Lcrit is the critical inductance. If (32) is satisfied in
a grid period, S1 and S2 can be turned on with ZVS. If not,
S1 and S2 cannot be turned on with ZVS.
B. Selection of Transformer Turns Ratio
The turns ratio n of T can be calculated from the voltage
gain M of the proposed converter as
n ≤
Vo
4Mminvin,peak
=
Vo
4vin,peak
, (33)
where Mmin is the minimum of M.
C. Resonant Inductance and Resonant Capacitance
The stable operation of converter is highly dependent on
the proper selection of resonant capacitor Cr. The peak of
capacitor voltage ripple ∆Vcr,peak must be less than half of
output voltage Vo such that vcr(t) ≥ 0
∆Vcr,peak ≤ Vo/2. (34)
Substituting the value of ∆Vcr,peak from (15) into (34) gives
Cr ≥
2Po
V 2
o fs
. (35)
The value of capacitor must be selected to satisfy (35).
Combining eqs. (9) and (35) to calculate Lr yields
Lr ≤
V 2
o fs
ω2
r Po
≤
Vofs
ω2
r Io
. (36)
(36) is used to guide selection of Lr; which has an inverse
relationship with output power Po and average output current
Io. Hence Lr should be set large enough to reduce the current
stress on devices while satisfying (36).
D. Switch Consideration
The switches undergo voltage stress and current stress
(Table I). The peak drain-source voltage stress determines
the voltage rating of the switches. The current stress also
determines the current rating of the switches. In Table I,
IS0l0 peak is peak current stress on the l-th switch. VS0l0 peak
is peak voltage stress on the l-th switch; ID0m0 peak is peak
current stress on the m-th diode; VD0m0 peak is peak voltage
stress on the m-th diode; IDr peak is peak current stress on
the rectifier diode; VDr peak is peak voltage stress on the
rectifier diode; vin,peak is peak voltage of vin; iin,peak is
peak voltage of iin.
VII. EXPERIMENTAL RESULTS
The proposed ac/dc converter was validated by construct-
ing (Fig. 10, Table II, Table III) and testing a 1-kW prototype.
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

16. IEEE TRANSACTIONS ON POWER ELECTRONICS
Fig. 10. Prototype of the proposed ac/dc converter.
TABLE II
PARAMETERS AND COMPONENTS OF THE PROTOTYPE
Parameters Symbols Value
Primary side voltage vg 175-265 Vrms
Secondary side voltage Vo 380 V
Rated output power Po 1 kW
Switching frequency fs 50 kHz
Resonant frequency fr 113 kHz
Input side inductor L1,2 0.45 mH
Resonant inductance Lr 10.8 µH
Magnetizing inductance Lm 87.5 µH
Clamp capacitance Cc 1 µF
Transformer turns ratio Np:Ns 32:8
Resonant capacitance Cr1, Cr2 178 nF
Output capacitance Co 1,000 µF
Components Symbol Part number
Primary side switches S1, ..., S4 UF3C120070K3S
Secondary side switches S5, S6 UF3C065040K3S
Secondary side diodes D1, D2 D2065C6
Transformer core T PQ5050
TABLE III
SPECIFICATION OF THE MAGNETIC COMPONENTS
Transformer property Value
Transformer size PQ5050
(Length/Width/Height) (30/48/48.5 mm)
Core material Ferrite R material, Magnetics
Turns ratio, n 0.25
Primary winding, Np 32 turns, 16 AWG x 2
Secondary winding, Ns 8 turns, 14 AWG x 3
Magnetic inductance 1.4 mH
Leakage inductance 0.38 µH
External inductor property Value
External inductor size PQ3535
(Length/Width/Height) (35.5/39.1/37.6 mm)
Core material Ferrite R material, Magnetics
Winding 31 turns, 16 AWG
Inductance 10.8 µH
Its operation is demonstrated for vg = 220 Vrms with
fg = 60 Hz and Vo = 380 V. A control algorithm was
developed using Code Composer Studio program, and was
executed on a TMS320F28377D digital signal processor.
The experimental waveforms (Fig. 11) of resonant ca-
pacitor voltages vcr1, vcr2 and resonant inductor current
iLr varied along with the grid voltage variation. The high-
Fig. 11. Experimental waveforms of vcr1, vcr2, and iLr.
Fig. 12. Experimental waveforms of vds1, iS1, vds4, and iS2. Due to
the symmetry in switching operation of (S1, S4) and (S2, S3), only the
waveform of the switch pair (S1, S4) is presented.
frequency waveforms are zoomed-in at a different instant
to show the behaviors of different voltages and currents
in the circuit. The ripple of the capacitor voltage is high
at high instantaneous power and low at low instantaneous
power. At high instantaneous power, the inductor current
increases linearly during a short period of time and decreases
sinusoidally during a long period of time. In contrast, at low
instantaneous power, the inductor current increases linearly
during a long period of time and decreases sinusoidally
during a short period of time.
The experimental waveforms (Fig. 12) of primary switches
(S1, S4) are half-sinusoidal. Before switches S1 and S4 are
turned on, negative current flows through them. Therefore,
they are turned on with ZVS. In the bidirectional switches
(S5, S6), vds of S5 is equal to Vo/2−∆Vcr at turn-off instant
(Fig. 13). At high instantaneous power, the ripple of the
resonant capacitor voltage ∆Vcr is closed to half of the output
voltage Vo. Hence, S5 is turned off with the voltage closed
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
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17. IEEE TRANSACTIONS ON POWER ELECTRONICS
Fig. 13. Experimental waveforms of vds5, iS5, vds6, and iS6.
Fig. 14. Experimental waveforms of iD1 and iD2.
Fig. 15. Experimental waveforms of iin, iL1, and iL2.
to Vo/2. In contrast, at low instantaneous power, the ripple of
the resonant capacitor voltage ∆Vcr becomes small, but vds
(a)
(b)
(c)
Fig. 16. Experimental waveforms of Vo, vg, and ig when vg = 220 Vrms
and the output power is varied. (a) At the steady state. (b) From 500 W (288
Ω) to 1 kW (144 Ω). (c) From 1 kW (144 Ω) to 500 W (288 Ω).
Fig. 17. Measured efficiency curves according to the output load and the
grid voltage variations.
of S5 is still lower than Vo/2, and so S5 is turned off with
low voltage.
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
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18. IEEE TRANSACTIONS ON POWER ELECTRONICS
Fig. 18. Measured power factor curves according to the output load and the
grid voltage variations.
iD1 and iD2 are also half-sinusoidal (Fig. 14). The current
through the diode starts to flow after the bidirectional switch
is turned off. The current is transferred to output through
diodes. Both the diodes are turned-off at zero current, so
they do not suffer from the reverse-recovery problem.
The waveforms (Fig. 15) of input inductor current
(iL1, iL2) and input current iin are half-sinusoidal. The
primary switches are operated with 50% fixed duty ratio, so
the ripple in input current iin is eliminated.
The waveforms of grid voltage, grid current and output
voltage are presented in Fig. 16a. The grid current is sinu-
soidal and the output voltage is almost constant. The grid
voltage vg and the grid current ig are completely in-phase;
this result shows the effectiveness of control algorithm. The
power factor achieved is 0.996 which is almost unity and the
current waveform is exactly sinusoidal, with total harmonic
distortion of 3.46%. Moreover, the output voltage Vo reaches
the desired output voltage. To validate the dynamic perfor-
mance of the proposed ac/dc converter, the output power is
varied from 500 W to 1 kW and vice versa. When the output
power is changed, the grid current well tracked the reference
grid current and output voltage well regulated the reference
output voltage under the power variation (Fig. 16b,c).
The efficiency (Fig. 17) and the input power factor
(Fig. 18) of the proposed converter were measured using a
Yokogawa WT1800 power analyzer. The proposed converter
achieved a peak efficiency of 95.1% and the input power
factor of 0.996 at vg=220 Vrms and full load. The loss
breakdown of the proposed converter is conducted at full-
load. The use of secondary-side switching alleviates the
losses occurred at the primary-side switches (Fig. 19). The
efficiency and the input power factor of the conventional
converter were obtained only when vg=220 Vrms. The grid
current of this converter was highly distorted when vg=175
Vrms or vg=265 Vrms, and so we did not measure its
efficiency and input power factor. The efficiency and the
input power factor of the conventional converter were slightly
higher than those of the proposed converter at vg=220 Vrms
and under the different output powers.
Thermal images (Fig. 20) verify improved heat distribution
at the primary-side switches and secondary-side switches
of the proposed converter. Maximum temperature at the
primary-side switches of the conventional converter [22] was
measured at 68.1◦
C. In contrast, maximum temperatures at
(a)
(b)
(c)
(d)
Fig. 19. Loss breakdown of the converters at full-load. (a) Proposed
converter when vg=175 Vrms. (b) Proposed converter when vg=220
Vrms. (c) Conventional converter in [22] when vg=220 Vrms. (d) Proposed
converter when vg=265 Vrms.
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
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19. IEEE TRANSACTIONS ON POWER ELECTRONICS
(a) (b) (c)
Fig. 20. Thermal images of the switches of the converters. (a) Primary-side switches of the conventional converter [22]. (b) Primary-side switches of the
proposed converter. (c) Secondary-side switches of the proposed converter.
the primary-side switches and the secondary-side switches
of the proposed converter were measured at 35.2◦
C and
39.1◦
C, respectively. The improved heat distribution is able
to simplify the design of heat sink attached to the switches.
The proposed converter and other ac/dc converters are
compared in terms of topology, shape of the inductor current,
the number of power components, power conversion effi-
ciency, etc. (Table IV). Two-stage ac/dc converter in [4] con-
sists of dual-output-rectifier and dual-input dc transformer.
The front-end rectifier controls the input current and regulates
the dc-bus voltage. The use of the dc transformer fixes the
voltage gain between dc-bus voltage and output voltage. The
rectifier stage experiences high switching loss and conduction
loss, which lowers the efficiency of the converter. Even
though the switching loss of the dc transformer is negligible,
the conduction loss of the dc transformer exists. When the
input voltage becomes lower, the current flowing through
the front-end circuit increases. Then, MOSFET switches at
the front-end circuit in [4] experience high conduction loss,
because the front-end circuit in [4] has a single current-fed
structure. In contrast, MOSFET switches in the proposed
converter experience relatively low conduction loss, because
the proposed converter is built based on double current-fed
structure. When the input voltage varies from 175 Vrms
to 265 Vrms, the dc bus voltage will be able to reach
2·265·
√
2=749 V in the proposed converter. In contrast, the
dc bus voltage in [4] maintains at 435 V. The smaller dc
bus voltage reduces the voltage stress on the active power
components. However, the required number of active power
components is larger than that of the proposed converter;
the cost of active power components takes a large portion
in the development cost. In Table V, we have estimated
and compared the cost for the active power components of
the converters when these converters operate in the same
input/output environment. We can see that the development
cost of the converter in [4] is higher than that of the proposed
converter. Moreover, the converter in [4] presents the single
current-fed structure and so the high-frequency input current
ripple occurs as the duty-ratio changes; the converter in [4] re-
quires the additional LC filter at the grid side. Meanwhile, the
proposed converter employs double current-fed structure and
operates with Dp=0.5; the input current ripple is theoretically
zero. This aspect does not require the additional LC filter,
which can further reduce the size and cost of the converter
in the ac/dc applications. The unfolded dual-active-bridge
ac/dc converter has been developed in [13]. The converter
has a buck-boost functionality, so it can cover the wide output
voltage range. However, it requires secondary-side switches,
which increases the development cost of the converter. The
unfolded double current-fed linear ac/dc converter has been
presented in [21]. This converter requires only two switches at
the primary side, but it will need additional snubber circuits
to suppress the voltage spike occurred at the primary-side
switches. The unfolded double current-fed resonant ac/dc
converter has been presented in [22]. This converter achieves
high efficiency because full resonance is ensured under the
grid voltage of 220 Vrms. However, the heat distribution
between primary-side top switches and bottom switches is
unbalanced; this trait increases the size of the heat sink.
Besides, when the grid voltage deviates from 220 Vrms, the
resonance is broken in first half switching cycle, but not in
the second half switching cycle. That is, the converter enters
to asymmetric above resonance mode. The converter in [22]
operating asymmetric above resonance mode cannot achieve
satisfactory power factor and total harmonic distortion in the
grid current. Compared to the converter in [22], the proposed
ac/dc converter adopts the active voltage doubler at the
secondary side; this aspect significantly reduces the switching
loss at the high instantaneous power and also reduces at the
low instantaneous power. Also, the secondary side switch-
ing balances the loss distribution between the primary-side
top switches and bottom switches, which reduces the size
of the heat sink. The secondary-side switching makes the
resonant currents in first half switching cycle and second
half switching cycle become symmetric. This will increase
the controllability of the proposed converter.
VIII. CONCLUSION
In this paper, a quasi-single-stage current-fed resonant ac-
dc converter having improved heat distribution is proposed.
By using bidirectional switch at the secondary side of the
transformer, it achieves the turn-off with the voltage closed
to zero at high instantaneous power and the turn-off with
the voltage closed to the half of the output voltage at low
instantaneous power. Switching loss at the main switch is
reduced, so heat is distributed evenly among the active
switches. The primary-side switches operate with 0.5 duty-
cycle, which makes the input current ripple almost negligible.
Theoretical analysis and experimental results for a 1-kW pro-
totype demonstrate the feasibility of the proposed converter.
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

20. IEEE TRANSACTIONS ON POWER ELECTRONICS
TABLE IV
COMPARISON OF THE CONVENTIONAL AC/DC CONVERTERS AND THE PROPOSED CONVERTER
Items [4] [13] [21] [22]
Proposed
converter
Topology
Two-stage Unfolded Unfolded Unfolded Unfolded
dual-output- dual-active- double double double
rectifier bridge current-fed current-fed current-fed
+ LLC + active-clamp active-clamp
rectifier + voltage-doubler + active
voltage-doubler
Operation mode Buck-boost Buck-boost Boost Boost Boost
Inductor current
Mode 1 Resonant Linear Linear Resonant Linear
Mode 2 - Linear - - Resonant
Switches 6 8 2 4 6
Number of Diodes 10 4 8 6 6
components Capacitors 4 3 1 5 4
Inductors 2 1 2 3 3
Transformers 1 1 1 1 1
Peak efficiency 96.2% 95% 92% 96.3% 95.1%
Grid voltage 200-240 Vrms 220 Vrms 110 Vrms 220 Vrms 175-265 Vrms
Output voltage 240-360 V 400 V 48 V 360 V 380 V
Rated power 1.5 kW 1.0 kW 0.1 kW 1 kW 1 kW
Heat distribution Balanced Balanced Unbalanced Unbalanced Balanced
Input-current ripple Medium High Medium Medium Zero
Controllability under
Good Good Good Poor Good
grid voltage variation
Implementation cost High High Low Low Medium
TABLE V
PRICE COMPARISON OF THE CONVENTIONAL AC/DC CONVERTERS AND THE PROPOSED CONVERTER
Part Part number Voltage rating Unit price ($) [4] [13] [21] [22] Proposed
MOSFET
UF3C065040K3S 650 V 12.55 6 - - - 2
UJ3C120070K3S 1200 V 15.38 - 8 2 4 4
Diode D2065C6 650 V 8.51 6 - 4 2 2
Diode rectifier KBPC5010 700 V 3.61 1 1 1 1 1
Total cost ($) 129.97 126.65 68.41 82.15 107.25
Courtesy: The price of the components is referred to www.mouser.com.
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© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.

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Waqar Uddin was born in Upper Dir, Khyber
Pukhtunkhwa, Pakistan. He received his B.S. and
M.S degree in Electrical Power Engineering and
Electrical Engineering from COMSATS University
Islamabad, Abbottabad Campus, Pakistan, respec-
tively in 2013 and 2016. He worked as a Lec-
turer at University of Management Technology,
Lahore, Sialkot Campus, Pakistan from 2016 to
2018. He completed his Ph.D. degree in 2020 from
Pusan National University, Busan, South Korea. In
2020/2021, he worked as a Postdoctoral Researcher
in the CPC laboratory at Dongguk University, Seoul, South Korea. Since
2021, he is working as an Assistant Professor at the National University of
Technology, Islamabad, Pakistan.
His research interests include power converter and control, grid-connected
converters, electric drives and integration of renewable energies to grid.
Tsegaab Alemayehu Wagaye (Student Member,
IEEE) received the B.S. degree in electrical and
computer engineering from Addis Ababa Univer-
sity, Addis Ababa, Ethiopia, in 2019. He is cur-
rently working toward the Ph.D. degree at Dongguk
University, Seoul, Korea.
His research interests include highly efficient
power conversion systems and control, highly effi-
cient power circuit design and inverter circuits.
Minsung Kim (M’14-SM’20) was born in Ulsan,
Korea, in 1986. He received the B.S. degree in
electrical engineering from Pohang University of
Science and Technology (POSTECH), Pohang, Ko-
rea, in 2008, and the Ph.D. degree in electrical
engineering from POSTECH, Pohang, Korea, in
2013.
Since 2013, he has been with Department of
Creative IT Engineering and Future IT Research
Laboratory, POSTECH, Pohang, Korea, where he
is currently Research Assistant Professor. In 2016,
he has also worked as Research Scholar in Future Energy Electronics Center
at Virginia Tech, Blacksburg, VA. In 2017, he has also served as Academic
Visitor in Control and Power System Group at Imperial College London,
London, UK. Since 2018, he has been with the Division of Electronics
and Electrical Engineering, Dongguk University, Seoul, Korea, where he is
currently an Assistant Professor.
His current research interests include highly efficient power conversion
circuit design, intelligent controller design for industrial electronics, and
renewable energy energy storage systems.
This article has been accepted for publication in IEEE Transactions on Power Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2022.3185830
© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.