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Shift Registers
 A shift register is a sequential logic block
made up of flip-flops that allows parallel or
serial loading and serial or parallel outputs
as well as shifting bit by bit.
 Common tasks of shift registers:
– Serial/parallel data conversion
– UART (an example)
– Time delay
– Ring counter
– Twisted-ring counter or Johnson counter
– Memory device
Shift Registers
3684
Shift Registers
368
36
3
An example of a shift
register at work would
be a calculator.
1 0 1 0 1 1 0 1
Serial In Serial out
…0 1… …1 0…
Serial In
1 0 1 0 1 1 0 1
1 0 1 0 1 1 0 1
…0 1…
Parallel out
MSB LSB
1 0 1 0 1 1 0 1
1 0 1 0 1 1 0 1
Parallel out
Parallel in
MSB LSB
1 0 1 0 1 1 0 1
1 0 1 0 1 1 0 1
Parallel In
MSB LSB
Serial Out
…1 0…
Shift Register Types
SERIAL LOAD SHIFT REGISTER
Note the use of D FFs.
Clock (CLK) inputs wired in parallel.
Clear (CLR) inputs can be activated with LOW
or disabled with HIGH.
Preset (PS) inputs deactivated.
Parallel outputs here.
Order= A B C D
Inputs here:
(1) Data
(2) Clock
(3) Clear
Clear input:
Active = 0
Deactivated = 1
Clock input:
Positive-edge
triggering
Clock Pulse 1
Clear = 0
Data = 1
0 0 0 0
1 0 0 0
Clock Pulse 2
Clear = 1
Data = 1
1 1 0 0
0 1 1 0
Clock Pulse 3
Clear = 1
Data = 1
Clock Pulse 4
Clear = 1
Data = 0
0 0 1 1
Clock Pulse 5
Clear = 1
Data = 0
0 0 0 1
Clock Pulse 6
Clear = 1
Data = 0
Clock Pulse 7
Clear = 1
Data = 1
1 0 0 0
0 1 0 0
Clock Pulse 8
Clear = 1
Data = 0 4-bit
serial-in
parallel out
shift right
shift register
74164 IC Shift Register
74LS164
Dsa
Dsb
CP
MR
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Serial In Parallel out
Clock
Master reset

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Lecture on types of Shift Registers.pptx

  • 2.  A shift register is a sequential logic block made up of flip-flops that allows parallel or serial loading and serial or parallel outputs as well as shifting bit by bit.  Common tasks of shift registers: – Serial/parallel data conversion – UART (an example) – Time delay – Ring counter – Twisted-ring counter or Johnson counter – Memory device Shift Registers
  • 3. 3684 Shift Registers 368 36 3 An example of a shift register at work would be a calculator.
  • 4. 1 0 1 0 1 1 0 1 Serial In Serial out …0 1… …1 0… Serial In 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 …0 1… Parallel out MSB LSB 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 Parallel out Parallel in MSB LSB 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 Parallel In MSB LSB Serial Out …1 0… Shift Register Types
  • 5.
  • 6.
  • 7. SERIAL LOAD SHIFT REGISTER Note the use of D FFs. Clock (CLK) inputs wired in parallel. Clear (CLR) inputs can be activated with LOW or disabled with HIGH. Preset (PS) inputs deactivated. Parallel outputs here. Order= A B C D Inputs here: (1) Data (2) Clock (3) Clear Clear input: Active = 0 Deactivated = 1 Clock input: Positive-edge triggering Clock Pulse 1 Clear = 0 Data = 1 0 0 0 0 1 0 0 0 Clock Pulse 2 Clear = 1 Data = 1 1 1 0 0 0 1 1 0 Clock Pulse 3 Clear = 1 Data = 1 Clock Pulse 4 Clear = 1 Data = 0 0 0 1 1 Clock Pulse 5 Clear = 1 Data = 0 0 0 0 1 Clock Pulse 6 Clear = 1 Data = 0 Clock Pulse 7 Clear = 1 Data = 1 1 0 0 0 0 1 0 0 Clock Pulse 8 Clear = 1 Data = 0 4-bit serial-in parallel out shift right shift register
  • 8.
  • 9.
  • 10.
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 18. 74164 IC Shift Register 74LS164 Dsa Dsb CP MR Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Serial In Parallel out Clock Master reset