Arasan Chip Systems develops and marketing interface IP that meets MIPI standards. Digital IP can typically be emulated in FPGA, but mixed signal IP for physical interface cannot. Arasan provides MIPI D-PHY and MIPI M-PHY is module form for application processor / system on a chip developers to use with their emulation boards.

1. MIPI® PHY Modules for SoC Development,
Validation and Compliance Testing
Surender Sharma
Sam W. Beal
Arasan Chip Systems

2. Surender Sharma
Arasan Chip Systems
(408) 282-1600
surender@arasan.com
Sam W. Beal
Arasan Chip Systems
(408) 282-1600
sam.beal@arasan.com

3. MIPI PHY Modules for SoC Development,
Validation and Compliance Testing
MIPI Interfaces are used in a wide range of mobile devices, from
smartphones to tablets with new applications emerging beyond
mobile. SoC designers typically use FPGA-based prototyping boards for
design, debug, validation and compliance.
Low-power high-speed SLVS I/Os for camera, display and storage (CSI,
DSI, UFS) are typically not supported by FPGA vendors. Arasan has
developed PHY modules to support this need.
Slide 3

4. Outline
D-PHY and M-PHY Overview
Hardware Prototyping
Use Cases
Arasan UFS HVP System
Arasan PHY Modules
D-PHY Module, System Example
M-PHY Module, System Example
Summary
Slide 4

5. What is D-PHY?
D-PHY Overview
MIPI defined I/O for display (DSI) and camera (CSI)
High-speed (HS) Low Power (LP) Modes
HS SLVS 200mV differential up to 1.5Gbps
LP LVCMOS 1.2V single-ended low speed
Separate clock and data lanes (up to 4 data lanes)
Not supported in standard FPGAs
Slide 5

6. D-PHY Functional Diagram
Slide 6

7. What is M-PHY?
M-PHY Overview
• MIPI defined I/O for high speed and very low power
• Adopted by JEDEC for next generation mobile storage (UFS)
• Adopted by PCI-SIG for mobile PCIe
• Adopted by USB for USB 3 chip to chip (SSIC)
High-speed / Low Power / Low pin count
• 1 or 2 lanes SerDes
• HS 1.2Gbps – 5.9Gbps (Gear 1, 2, 3)
• LS 10Kbps – 576Mbps (Gear 0-7)
Not supported in standard FPGAs
Slide 7

8. M-PHY Module Interface
Reference MPHY Module Interface
(RMMI)
Physical Media Interface
Slide 8

9. Hardware Prototyping – Use Cases
Host
Board
PHY
Target
PHY
Early Software Development
SoC Validation
SoC Demonstration
Compliance Testing
Slide 9

10. Arasan UFS HVP Example
Memory CPU FPGA
Host Platform
ConnectivityIP BoardMotherboard
UFS
Device or Host
Software Stack and
Drivers for Linux
UFS &
UniPro
Host
RTL IP
M-PHY
Digital &
Analog IP
Device Platform
FPGA
Connectivity IP Board
MemoryCPU
Motherboard
UFS
Device or Host
Software Stack and
Drivers for Linux
UFS &
UniPro
Device
RTL IP
M-PHY
Digital &
Analog IP
Hardware Platform Enables Early Software Development & Device Testing
Slide 10

11. D-PHY Module
D-PHY
Test
Chip
FMC Connector SMA Connectors
PHY Protocol Interface PPI Physical Media Interface
Slide 11

12. D-PHY Module Example
DSI Configuration
Slide 12

13. D-PHY Development – loopback test
Slide 13

14. M-PHY Module
Slide 14

15. M-PHY Module
The board consists of
ACS MIPI M-PHY test chip
Power supply regulator
Multiple test points and mode switches
High speed SMA for differential signaling
Samtec FMC for board to board connection
Slide 15