Design Automation Conference - IP Talks June 2011


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Overview of SD storage IP from Arasan Chip Systems, given at the Design Automation Conference (DAC 2011) San Diego, CA by Dennis McCarty

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Design Automation Conference - IP Talks June 2011

  1. 1. Total Storage Solutions Dennis McCarty Arasan Chip Systems
  2. 2. <ul><li>Keeping up with Standards </li></ul><ul><li>Arasan Supported Standards </li></ul><ul><li>SD Flash Now and in the Future </li></ul><ul><li>SD 4.0 Improvements </li></ul><ul><li>ONFI Flash Overview </li></ul><ul><li>Universal Flash Storage </li></ul><ul><li>Deliverables </li></ul><ul><li>Arasan Total Solution </li></ul><ul><li>Total Solution Advantage </li></ul>Overview
  3. 3. IP Customers Need <ul><li>IP products that adhere to evolving standards </li></ul><ul><li>Customers want custom versions that adapt to new standards </li></ul><ul><li>Users want timely support from design engineers who know the product </li></ul>
  4. 4. Arasan Standards Products <ul><li>Membership and participation in standards bodies allows us ground floor view of changes and additions to new versions </li></ul><ul><li>Products roll out as soon as standard approved </li></ul><ul><li>Development engineers also support products </li></ul>
  5. 5. Arasan IP Memory Standards Coverage <ul><li>SD / SDIO / MMC / CF / XD / Pro </li></ul><ul><li>ONFI NAND Flash </li></ul><ul><li>Universal Flash Storage </li></ul>
  6. 6. SD is Pervasive <ul><li>SD is the most pervasive format for Flash </li></ul><ul><li>SD found in </li></ul><ul><ul><li>Cameras </li></ul></ul><ul><ul><li>Video </li></ul></ul><ul><ul><li>Games </li></ul></ul><ul><ul><li>Mobile </li></ul></ul><ul><ul><li>Tablets </li></ul></ul>
  7. 7. SD is Improving <ul><li>SD growing at 15% annually </li></ul><ul><li>Capacities increasing as shown by the SDXC offering 32G to 2T </li></ul><ul><li>Speeds going to 104 MB/s </li></ul>
  8. 8. Growth of SD Standard
  9. 9. SD 4.0 Background <ul><li>SD 4.0 most recent revision to the SD standard </li></ul><ul><li>Introduces the powerful UHS-II PHY for faster throughput </li></ul><ul><ul><li>1.56 GB/s/lane at 52MHz </li></ul></ul><ul><ul><li>300 MB/s overall </li></ul></ul><ul><li>Adds second row of pins for differential signaling </li></ul><ul><ul><li>D0+/- and D1+/- </li></ul></ul><ul><li>Bus clock 208 MHz </li></ul><ul><li>Capacity from 32GBy to 2TBy </li></ul>
  10. 10. SD 4.0 Controller Architecture
  11. 11. Arasan SD Compliance <ul><li>Current to SD 4.0 (rev. April 2011) </li></ul><ul><li>Arasan 4.0 Device controller core available April 2011 </li></ul><ul><li>Only announced product in the market </li></ul>
  12. 12. ONFI Background <ul><li>ONFI Open NAND Flash Interface </li></ul><ul><ul><li>NAND Flash Industry Consortium </li></ul></ul><ul><li>Version 3.0 </li></ul><ul><ul><li>Latest specification for NAND Flash control </li></ul></ul><ul><ul><li>Faster data transfers and new features </li></ul></ul><ul><ul><li>Backwards compatible with previous versions </li></ul></ul>
  13. 13. <ul><li>Operates memory devices at any frequency up to 200 MHz </li></ul><ul><ul><li>400 MT/S </li></ul></ul><ul><li>Differential signaling on clock and data lines </li></ul><ul><li>DDR-2 Transfers </li></ul><ul><ul><li>True and Complement Data Strobes </li></ul></ul><ul><ul><li>SDR, NV-DDR and NV-DDR2 </li></ul></ul>ONFI 3.0 Features
  14. 14. ONFI 3.0 Features <ul><li>Single and Dual data bus discovery </li></ul><ul><li>Eight chip enables </li></ul><ul><li>Page sizes up to 8K </li></ul><ul><li>ECC up to 64 bits </li></ul><ul><ul><li>Dynamically configurable ECC width </li></ul></ul><ul><li>Warm-up cycles for high-speed operation </li></ul><ul><li>Supports all new commands </li></ul>
  15. 15. Patented BCH Coding <ul><li>BCH Coded ECC supports dynamically scalable correction bits </li></ul><ul><li>Parallel bit processing on the BCH encoder </li></ul><ul><li>Parallel syndrome generation </li></ul><ul><li>Inversion-less Berlekamp-Massey algorithm for key equation solver </li></ul><ul><li>Parallel computation for the key equation solver </li></ul><ul><li>Parallel Chien search algorithm </li></ul>
  16. 16. ONFI Compliance <ul><li>Compliant to the 3.0 ONFI (rev. 2011) </li></ul><ul><li>Arasan 3.0 core available July 2011 </li></ul><ul><li>Only announced product in the market </li></ul>
  17. 17. ONFI NAND Flash Architecture CE_N(7:0) CLK- Data(15:0)+ Data(15:0)- CLK+
  18. 18. <ul><li>Originally part of Mobile Industry Processor Interface (MIPI) Alliance </li></ul><ul><li>Universal Flash Storage </li></ul><ul><ul><li>Similar to SCSI, but with own command set </li></ul></ul><ul><ul><li>Large storage capacity </li></ul></ul><ul><ul><li>Simple, high-performance serial interface </li></ul></ul><ul><li>2.9Gbps max per lane, version 1.0 </li></ul><ul><li>Multiple partitions on memory Logical Units (LU) </li></ul>UFS Features
  19. 19. UFS Architecture
  20. 20. Arasan IP Core Deliverables <ul><li>RMM (Reuse Methodology Manual) compliant Verilog </li></ul><ul><li>Configurable Behavioral models </li></ul><ul><li>Verification Suite & Test Cases </li></ul><ul><li>Documentation and Design Support </li></ul><ul><ul><li>User Guide </li></ul></ul><ul><ul><li>24/7 phone and email support </li></ul></ul><ul><ul><li>Optional on-site support </li></ul></ul>
  21. 21. Arasan Total Solution <ul><li>A ‘Total IP Solution’ bundles everything you need to implement standards </li></ul><ul><ul><li>RTL </li></ul></ul><ul><ul><li>Analog Mixed Signal </li></ul></ul><ul><ul><li>Verification IP </li></ul></ul><ul><ul><li>Software Drivers/Stacks </li></ul></ul><ul><ul><li>Protocol Analyzers </li></ul></ul><ul><ul><li>Hardware Development Kits </li></ul></ul><ul><ul><li>Technology Consulting </li></ul></ul>
  22. 22. <ul><li>Total Solution Benefits </li></ul><ul><ul><li>Cores, with no gaskets or wrappers for low-gate design </li></ul></ul><ul><ul><li>Compliance across the standard </li></ul></ul><ul><ul><li>Single supplier – Single support </li></ul></ul><ul><ul><li>Guaranteed compatibility </li></ul></ul><ul><ul><li>Lowest overall cost and risk </li></ul></ul><ul><ul><li>Seamless integration from PHY to SW layers </li></ul></ul><ul><ul><li>Fastest cycle: MRD to SoC </li></ul></ul>Total Solution Benefits
  23. 23. Thank you <ul><li>Explore Arasan Chip Systems IP at </li></ul><ul><li>Use Arasan Chip Systems IP to plan your next product </li></ul><ul><li>Please stay and talk with Dennis McCarty </li></ul>