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  1. 1. MICROPROCESSORAn integrated circuit contained on a single silicon chip, amicroprocessor contains the arithmetic logic unit, control unit,internal memory registers, and other vital circuitry of a computerscentral processing unit (CPU). Microprocessor commonly is usedinterchangeably with CPU and processor.Three basic characteristics differentiate microprocessors: Instruction set: The set of instructions that the microprocessorcan execute. bandwidth : The number of bits processed in singleinstruction. Clock speed : Given in megahertz (MHz), the clock speeddetermines how many instructions per second the processor canexecute.In both cases, the higher the value, the more powerfulthe microprocessor that runs at 50MHz is more powerful than a16-bitmicroprocessor that runs at 25MHZ.
  2. 2. The few microprocessors images:
  3. 3. PIN OUT DIAGRAM OF 8085Manufacturers: AMD, Intel, NEC, Siemens, Toshiba X1 1 40 VCC X2 2 39 Hold Reset Out 3 38 HLDA SOD 4 37 CLK (OUT) SID 5 36 RESET IN Trap 6 35 Ready RST 7.5 7 34 IO/M RST 6.5 8 33 S1 RST 5.5 9 32 RD INTR 10 31 WR INTA 11 30 ALE AD0 12 29 S0 AD1 13 28 A15 AD2 14 27 A14 AD3 15 26 A13 AD4 16 25 A12 AD5 17 24 A11 AD6 18 23 A10 AD7 19 22 A9 VSS 20 21 A8 Properties 1) Single + 5V Supply 2) 4 Vectored Interrupts (One is Non Maskable)
  4. 4. 3) Serial In/Serial Out Port4) Decimal, Binary, and Double Precision Arithmetic5) Direct Addressing Capability to 64K bytes of memoryThe Intel 8085A is a new generation, complete 8 bit parallelcentral processing unit (CPU). The 8085A uses amultiplexed data bus. The address is split between the 8bitaddress bus and the 8bit data bus.Pin DescriptionThe following describes the function of each pin:A6 - A1s (Output 3 State)Address Bus: The most significant 8 bits of the memoryaddress or the 8 bits of the I/0 address, 3 stated during Holdand Halt modes.AD0 - 7 (Input/output 3state)Multiplexed Address/Data Bus; Lower 8 bits of the memoryaddress (or I/0 addresses) appear on the bus during the firstclock cycle of a machine state. It then becomes the data busduring the second and third clock cycles. 3 stated duringHold and Halt modes.
  5. 5. ALE (Output)Address Latch Enable: It occurs during the first clock cycle ofa machine state and enables the address to get latched intothe chiplatch of peripherals. The falling edge of ALE is set toguarantee setup and hold times for the address information.ALE can also be used to strobe the status information. ALEis never 3statesSO, S1 (Output)Data Bus Status. Encoded status of the bus cycle: S1 can beused as an advanced R/W status.RD (Output 3state)READ; indicates the selected memory or 1/0 device is to beread and that the Data Bus is available for the data transfer.WR (Output 3state)WRITE; indicates the data on the Data Bus is to be writteninto the selected memory or 1/0 location. Data is set up atthe trailing edge of WR. 3stated during Hold and Halt modes.READY (Input)If Ready is high during a read or write cycle, it indicates thatthe memory or peripheral is ready to send or receive data. IfReady is low, the CPU will wait for Ready to go high beforecompleting the read or write cycle.
  6. 6. HOLD (Input)HOLD; indicates that another Master is requesting the use ofthe Address and Data Buses. The CPU, upon receiving theHold request, will relinquish the use of buses as soon as thecompletion of the current machine cycle. Internal processingcan continue. The processor can regain the buses only afterthe Hold is removed. When the Hold is acknowledged, theAddress, Data, RD, WR, and IO/M lines are 3stated.HLDA (Output)HOLD ACKNOWLEDGE; indicates that the CPU hasreceived the Hold request and that it will relinquish the busesin the next clock cycle. HLDA goes low after the Holdrequest is removed. The CPU takes the buses one half clockcycle after HLDA goes low.INTR (Input)INTERRUPT REQUEST; is used as a general purposeinterrupt. It is sampled only during the next to the last clockcycle of the instruction. If it is active, the Program Counter(PC) will be inhibited from incrementing and an INTA will beissued. During this cycle a RESTART or CALL instructioncan be inserted to jump to the interrupt service routine. TheINTR is enabled and disabled by software. It is disabled byReset and immediately after an interrupt is accepted.INTA (Output)INTERRUPT ACKNOWLEDGE; is used instead of (and hasthe same timing as) RD during the Instruction cycle after anINTR is accepted. It can be used to activate the 8259Interrupt chip or some other interrupt port.
  7. 7. RST 5.5RST 6.5 - (Inputs)RST 7.5RESTART INTERRUPTS; These three inputs have thesame timing as INTR except they cause an internalRESTART to be automatically inserted.RST 7.5 Highest PriorityRST 6.5RST 5.5 Lowest PriorityThe priority of these interrupts is ordered as shown above.These interrupts have a higher priority than the INTR.TRAP (Input)Trap interrupt is a non maskable restart interrupt. It isrecognized at the same time as INTR. It is unaffected by anymask or Interrupt Enable. It has the highest priority of anyinterrupt.RESET IN (Input)Reset sets the Program Counter to zero and resets theInterrupt Enable and HLDA flip flops. None of the other flagsor registers (except the instruction register) are affected TheCPU is held in the reset condition as long as Reset isapplied.
  8. 8. RESET OUT (Output)Indicates CPU is being reset. It can be used as a systemRESET. The signal is synchronized to the processor clock.X1, X2 (Input)Crystal or R/C network connections to set the internal clockgenerator X1 can also be an external clock input instead of acrystal. The input frequency is divided by 2 to give theinternal operating frequency.CLK (Output)Clock Output for use as a system clock when a crystal or R/C network is used as an input to the CPU. The period of CLKis twice the X1, X2 input period.IO/M (Output)IO/M indicates whether the Read/Write is to memory or l/OTristated during Hold and Halt modes.SID (Input)Serial input data line: The data on this line is loaded intoaccumulator bit 7 whenever a RIM instruction is executed.SOD (output)Serial output data line. The output SOD is set or reset asspecified by the SIM instruction.
  9. 9. Vcc +5 volt supply.A8 - A15 (Output 3 State)Address Bus; The most significant 8 bits of the memory addressor the 8 bits of the I/0 address,3 stated during Hold and Haltmodes.AD0 - 7 (Input/Output 3state)Multiplexed Address/Data Bus; Lower 8 bits of the memoryaddress (or I/0 address) appear on the bus during the first clockcycle of a machine state. It then becomes the data bus during thesecond and third clock cycles. 3 stated during Hold and Haltmodes.ALE (Output)Address Latch Enable: It occurs during the first clock cycle of amachine state and enables the address to get latched into the onchip latch of peripherals. The falling edge of ALE is set toguarantee setup and hold times for the address information. ALEcan also be used to strobe the status information. ALE is never3stated.S0, S1 (Output)IO/M- (Output)IO/M- indicates whether the Read/Write is to memory or l/O(Tristated during Hold and Halt modes)
  10. 10. S0, S1, and IO/M- represent Data Bus Status. Encoded status ofthe bus cycle:S0 S1 IO/M-0 0 * Halt State (IO/M- Tristated)0 1 0 Memory Read0 1 1 I/O Read1 0 0 Memory Write1 0 1 I/O Write1 1 0 Opcode Fetch1 1 1 Interrupt AcknowledgeS1 can be used as an advanced R/W status. If used this way, itshould not be sampled until the trailiing edge of ALE.RD- (Output 3state)READ; indicates the selected memory or I/O device is to be readand that the Data Bus is available for the data transfer. Tristatedduring Hold and Halt modes. The processor samples the data busabout one half clock cycle before the trailing edge of RD-.WR- (Output 3state)WRITE; indicates the data on the Data Bus is to be written intothe selected memory or I/O location. Data is set up at the trailingedge of WR. Tristated during Hold and Halt modes. The data busis held valid for about one half clock cycle beyond the trailingedge of WR-, or until the leading edge of ALE. It is important torealize that any external bus drivers must not be dropped at thetrailing edge of WR- because that creates a race condition - UseALE to drop the drivers if needed.
  11. 11. READY (Input)If Ready is high during a read or write cycle, it indicates that thememory or peripheral is ready to send or receive data. If Ready islow, the CPU will wait for Ready to go high before completing theread or write cycle. It is sampled about one half clock cycle afterALE goes false, on the rising edge of CLK. Note that Ready issampled about one half clock cycle after the trailing edge of ALE,and this is not a lot of time - make sure your address/readydecoders are fast enough to respond.HOLD (Input)HOLD; indicates that another Master is requesting the use of theAddress and Data Buses. The CPU, upon receiving the Holdrequest. will relinquish the use of buses as soon as thecompletion of the current machine cycle. Internal processing cancontinue.The processor can regain the buses only after the Hold isremoved. When the Hold is acknowledged, the Address, Data,RD-, WR-, and IO/M- lines are 3stated.HLDA (Output)HOLD ACKNOWLEDGE; indicates that the CPU has receivedthe Hold request and that it will relinquish the buses in the nextclock cycle. HLDA goes low after the Hold request is removed.The CPU takes the buses one half clock cycle after HLDA goeslow.INTR (Input)INTERRUPT REQUEST; is used as a general purpose interrupt.It is sampled only during the next to the last clock cycle of the
  12. 12. instruction. If it is active, the Program Counter (PC) will beinhibited from incrementing and an INTA will be issued. Duringthis cycle a RESTART or CALL instruction can be inserted tojump to the interrupt service routine. The INTR is enabled anddisabled by software. It is disabled by Reset and immediatelyafter an interrupt is accepted.INTA (Output)INTERRUPT ACKNOWLEDGE; is used instead of (and has thesame timing as) RD during the Instruction cycle after an INTR isaccepted. It can be used to activate the 8259 Interrupt chip orsome other interrupt port.RESTART INTERRUPTS; These three inputs have the sametiming as INTR except they cause an internal RESTART to beautomatically inserted.RST 7.5 ~~ Highest Priority (Edge triggered)RST 6.5 ~~ Medium Priority (Level triggered)RST 5.5 ~~ Lowest Priority (Level triggered)The priority of these interrupts is ordered as shown above. Theseinterrupts have a higher priority than the INTR. They can bemasked with the SIM instruction.TRAP (Input) (Edge and Level triggered)Trap interrupt is a nonmaskable restart interrupt. It is recognizedat the same time as INTR. It is unaffected by any mask orInterrupt Enable. It has the highest priority of any interrupt.
  13. 13. RESET IN- (Input)Reset sets the Program Counter to zero and resets the InterruptEnable and HLDA flipflops. None of the other flags or registers(except the instruction register) are affected The CPU is held inthe reset condition as long as Reset is applied.RESET OUT (Output)Indicates CPlj is being reset. Can be used as a system RESET.The signal is synchronized to the processor clock.X1, X2 (Input)Crystal or R/C network connections to set the internal clockgenerator X1 can also be an external clock input instead of acrystal. The input frequency is divided by 2 to give the internaloperating frequency.CLK (Output)Clock Output for use as a system clock when a crystal or R/ Cnetwork is used as an input to the CPU. The period of CLK istwice the X1, X2 input period.SID (Input)Serial input data line The data on this line is loaded intoaccumulator bit 7 whenever a RIM instruction is executed.SOD (output)Serial output data line. The output SOD is set or reset asspecified by the SIM instruction.Vcc+5 volt supply.
  14. 14. FUNCTIONAL DIAGRAM OF 8085
  15. 15. 8085 Functional DescriptionThe 8085A is a complete 8 bit parallel central processor. Itrequires a single +5 volt supply. Its basic clock speed is 3 MHzthus improving on the present 8080s performance with highersystem speed. Also it is designed to fit into a minimum system ofthree ICs: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.The 8085A uses a multiplexed Data Bus. The address is splitbetween the higher 8bit Address Bus and the lower 8bitAddress/Data Bus. During the first cycle the address is sent out.The lower 8bits are latched into the peripherals by the AddressLatch Enable (ALE). During the rest of the machine cycle the DataBus is used for memory or l/O data.The 8085A provides RD, WR, and lO/Memory signals for buscontrol. An Interrupt Acknowledge signal (INTA) is also provided.Hold, Ready, and all Interrupts are synchronized. The 8085A also
  16. 16. provides serial input data (SID) and serial output data (SOD) linesfor simple serial interface. In addition to these features, the 8085Ahas three maskable, restart interrupts and one non-maskable trapinterrupt. The 8085A provides RD, WR and IO/M signals for Buscontrol.Status InformationStatus information is directly available from the 8085A. ALEserves as a status strobe. The status is partially encoded, andprovides the user with advanced timing of the type of bus transferbeing done. IO/M cycle status signal is provided directly also.Decoded So, S1 Carries the following status information:HALT, WRITE, READ, FETCH S1 can be interpreted as R/W inall bus transfers. In the 8085A the 8 LSB of address aremultiplexed with the data instead of status. The ALE line is usedas a strobe to enter the lower half of the address into the memoryor peripheral address latch. This also frees extra pins forexpanded interrupt capability.Interrupt and Serial l/OThe8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5,and TRAP. INTR is identical in function to the 8080 INT. Each ofthe three RESTART inputs, 5.5, 6.5. 7.5, has a programmablemask. TRAP is also a RESTART interrupt except it isnonmaskable. The three RESTART interrupts cause the internalexecution of RST (saving the program counter in the stack andbranching to the RESTART address) if the interrupts are enabledand if the interrupt mask is not set. The non-maskable TRAPcauses the internal execution of a RST independent of the stateof the interrupt enable or masks. The interrupts are arranged in afixed priority that determines which interrupt is to be recognized ifmore than one is pending as follows: TRAP highest priority, RST7.5, RST 6.5, RST 5.5, INTR lowest priority This priority scheme
  17. 17. does not take into account the priority of a routine that was startedby a higher priority interrupt. RST 5.5 can interrupt a RST 7.5routine if the interrupts were re-enabled before the end of the RST7.5 routine. The TRAP interrupt is useful for catastrophic errorssuch as power failure or bus error. The TRAP input is recognizedjust as any other interrupt but has the highest priority. It is notaffected by any flag or mask. The TRAP input is both edge andlevel sensitive.Basic System TimingThe 8085A has a multiplexed Data Bus. ALE is used as a strobeto sample the lower 8bits of address on the Data Bus. Figure 2shows an instruction fetch, memory read and l/ O write cycle(OUT). Note that during the l/O write and read cycle that the l/Oport address is copied on both the upper and lower half of theaddress. As in the 8080, the READY line is used to extend theread and write pulse lengths so that the 8085A can be used withslow memory. Hold causes the CPU to relingkuish the bus when itis through with it by floating the Address and Data Buses.System Interface8085A family includes memory components, which are directlycompatible to the 8085A CPU. For example, a system consistingof the three chips, 8085A, 8156, and 8355 will have the followingfeatures:· 2K Bytes ROM· 256 Bytes RAM· 1 Timer/Counter· 4 8bit l/O Ports· 1 6bit l/O Port
  18. 18. · 4 Interrupt Levels· Serial In/Serial Out PortsIn addition to standard l/O, the memory mapped I/O offers anefficient l/O addressing technique. With this technique, an area ofmemory address space is assigned for l/O address, thereby,using the memory address for I/O manipulation. The 8085A CPUcan also interface with the standard memory that does not havethe multiplexed address/data bus.

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