Microprocessor laboratory 03 Arithmetic Operation (Additional and Subtraction)

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This document is a laboratory report from Arkhom Jodtang of the Avionics Division of CATC Thailand. It describes Laboratory 3 on arithmetic operations using a Microprocessor (MCS-51) system that was conducted on March 22, 2016. The laboratory focused on performing and understanding basic arithmetic operations like addition, subtraction, multiplication and division using the microprocessor.

Laboratory 3
Arithmetic Operation
Arkhom Jodtang
Avionics Division, CATC, Thailand.

Tuesday, March 22, 2016 2
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

Tuesday, March 22, 2016 3
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

Tuesday, March 22, 2016 4
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

Tuesday, March 22, 2016 5
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

Tuesday, March 22, 2016 6
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

Tuesday, March 22, 2016 7
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

Tuesday, March 22, 2016 8
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

Tuesday, March 22, 2016 9
Microprocessor (MCS-51) Laboratory 3:
Arithmetic Operation

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This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.

PPT on GRP pipes manufacturing and testing

PPT on GRP pipes manufacturing and testing

PPT on GRP pipes manufacturing and testing

anoopmanoharan2

CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT

CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT

CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECT

The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been referred to as the "New Great Game." This research centres on the power struggle, considering geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil politics, and conventional and nontraditional security are all explored and explained by the researcher. Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role in Central Asia. This study adheres to the empirical epistemological method and has taken care of objectivity. This study analyze primary and secondary research documents critically to elaborate role of china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade, pipeline politics, and winning states, according to this study, thanks to important instruments like the Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study, China is seeing significant success in commerce, pipeline politics, and gaining influence on other governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai Cooperation Organisation and the Belt and Road Economic Initiative.

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01-GPON Fundamental fttx ftth basic .pptx

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Low power architecture of logic gates using adiabatic techniques

Low power architecture of logic gates using adiabatic techniques

Low power architecture of logic gates using adiabatic techniques

nooriasukmaningtyas

The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

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Hierarchical Digital Twin of a Naval Power System

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Hierarchical Digital Twin of a Naval Power System

A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.

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ACEP Magazine edition 4th launched on 05.06.2024

ACEP Magazine edition 4th launched on 05.06.2024

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PPT on GRP pipes manufacturing and testing

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