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This document discusses low power dual edge triggered static flip-flops. It begins by explaining how increasing clock frequency increases power consumption. It then introduces dual edge triggered flip-flops (DETFFs) which can capture data on both the rising and falling clock edges, allowing the clock frequency to be doubled without increasing power. The document presents the structure of conventional DETFFs and a proposed new static DETFF design using parallel positive and negative latches with a multiplexer to select the appropriate sampled data value. Analysis shows the proposed DETFF operates by latching input data on both clock edges for reduced power consumption compared to single edge triggering.
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Low power vlsi design ppt
it is class notes given by Prof. Dr R.Nakkeeran,At Dept. of Electronics engineering, Pondicherry university,India on Low Power Vlsi Design.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...
In high speed data path network flop is one of the major functional elements to store intermediate
results and data at different stages. But the most important problem is huge power utilization due to switching
activity and increase in clock period that is Timing Latency; causes the performance of data path in digital
design is decreased. The existing works implement various Flipflop topology in data path structure design such
as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop
(WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is
minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a
definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide
Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area
of the circuit is also reduced while comparing with previous methods.
A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...
Abstract: In high speed data path network flop is one of the major functional elements to store intermediate results and data at different stages. But the most important problem is huge power utilization due to switching activity and increase in clock period that is Timing Latency; causes the performance of data path in digital design is decreased. The existing works implement various Flipflop topology in data path structure design such as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop (WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area of the circuit is also reduced while comparing with previous methods. Index Terms: Circuit enhancement, flip-flops (FFs), high-speed, logical effort, master–slave, transmission-gate.
Recommended
Low power vlsi design ppt
it is class notes given by Prof. Dr R.Nakkeeran,At Dept. of Electronics engineering, Pondicherry university,India on Low Power Vlsi Design.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...
In high speed data path network flop is one of the major functional elements to store intermediate
results and data at different stages. But the most important problem is huge power utilization due to switching
activity and increase in clock period that is Timing Latency; causes the performance of data path in digital
design is decreased. The existing works implement various Flipflop topology in data path structure design such
as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop
(WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is
minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a
definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide
Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area
of the circuit is also reduced while comparing with previous methods.
A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure D...
Abstract: In high speed data path network flop is one of the major functional elements to store intermediate results and data at different stages. But the most important problem is huge power utilization due to switching activity and increase in clock period that is Timing Latency; causes the performance of data path in digital design is decreased. The existing works implement various Flipflop topology in data path structure design such as conventional Transmission Gate Based Master Slave Filpflop (TGMS FF), Write Port Master Slave Flip-flop (WPMS) and Clocked Complementary Metal Oxide Semiconductor (C2MOS). In WPMS method, area is minimized but delay is increased. In C2MOS technique Power consumption and delay is reduced, but there is a definite scope to reduce Power, area and delay. In this paper a Modified Clocked Complementary Metal Oxide Semiconductor Latch (mC2MOS Latch) is proposed and delay, power is again reduced up to 60% and the area of the circuit is also reduced while comparing with previous methods. Index Terms: Circuit enhancement, flip-flops (FFs), high-speed, logical effort, master–slave, transmission-gate.
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Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
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With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
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This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
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switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total
circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are
replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With
Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.
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LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
Design and Implementation of Low Power D flip flop for Embedded Application
https://www.irjet.net/archives/V9/i9/IRJET-V9I927.pdf
FAULT DETECTION AND CLASSIFICATION ON SINGLE CIRCUIT TRANSMISSION LINE USING ...
FAULT DETECTION AND CLASSIFICATION ON SINGLE CIRCUIT TRANSMISSION LINE USING ...Politeknik Negeri Ujung Pandang
- This paper proposes a new technique of using discrete wavelet transform (DWT) and back-propagation neural network (BPNN) based on Clarke’s transformation for fault classification and detection on a single circuit transmission line. Simulation and training process for the neural network are done by using PSCAD / EMTDC and MATLAB. Daubechies4 mother wavelet (DB4) is used to decompose the high frequency components of these signals. The wavelet transform coefficients (WTC) and wavelet energy coefficients (WEC) for classification fault and detect patterns used as input for neural network training back-propagation (BPNN). This information is then fed into a neural network to classify the fault condition. A DWT with quasi optimal performance for preprocessing stage are presented. This study also includes a comparison of the results of training BPPN and DWT with and without Clarke’s transformation, where the results show that using Clarke transformation in training will give in a smaller mean square error (MSE) and mean absolute error (MAE). The simulation also shows that the new algorithm is more reliable and accurate.Low power and high performance detff using common feedback inverter logic
Abstract The power consumption of a system is crucial parameter in modern VLSI circuits especially for low power applications. In this project, a low power Double Edge Triggered D-Flip Flop (DETFF) design is proposed in 65nm CMOS technology. The proposed DETFF is having less number of transistors than earlier designs. Simulations are carried out using HSPICE tool with different clock frequencies ranging from 400MHz to 2GHz and with different supply voltages ranging from 0.8V to 1.2V. In general, a power delay product (PDP)-based comparison is appropriate for low power portable systems. At nominal condition, the PDP of the proposed DETFF is improved by 65.48% and 44.85% over earlier designs DETFF1 and DETFF2 respectively. Simulation results show lowest power dissipation and least delay than existing designs, which claims that the proposed DETFF is suitable for low power and high speed applications. Keywords: CMOS, flip-flops, Double-edge triggered, power dissipation, delay and PDP.
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In this paper, a novel low-power pulse-triggered flip-flop (P-FF) design is presented. Pulse- triggered FF (P-FF) has been considered as a popular alternative to the conventional master –slave based FF in the applications of high speed. In particular, digital designs now-a-days often adopt intensive pipelining techniques and employ many FF-rich Modules. It is also estimated that the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20%–45% of the total system power. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. The simulations are done using Microwind & DSCH analysis software tools. Our proposed system simulations are done under 50nm technology and the results are compared with other conventional flip-flops. Hence, our proposed system is showing better output than the other flip-flops.
Low power and high performance detff using common
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
PERFORMANCE ANALYSIS OF D-FLIP FLOP USING CMOS, GDI, DSTC TECHNIQUES
https://www.irjet.net/archives/V9/i5/IRJET-V9I5191.pdf
SCAN CHAINS TESTING FOR LATCHES TO REDUCE AREA AND THE POWER CONSUMPTION
During the test mode of flip flop in a chip, a set of input vectors are sent through the flip-flop, it
consumes more power consumption than in the normal functional mode. In this paper, we
propose a latch with bi -stable element which reduces area as well as the power consumed. The
latch proposed consists of simple basic gates involving two inverters back to back which acts as
a bi-stable element and a transmission gate with the clock signal used to enable and disable the
rest of the circuit with impact on running the latch on Static Timing Analysis. The input test
vectors are either given by Automatic Test Pattern Generation (ATPG) or many other methods.
We model this using T-Simulation Program with Integrated Circuit Emphasis (T-SPICE) and see the power consumed.
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP
The power consumption of IC during test mode is higher than its normal mode. This brings the power as one of the major design constraints for today’s low power design technologies. In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too. The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode. The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%.
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http://sandymillin.wordpress.com/iateflwebinar2024
Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
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IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
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During the test mode of flip flop in a chip, a set of input vectors are sent through the flip-flop, it
consumes more power consumption than in the normal functional mode. In this paper, we
propose a latch with bi -stable element which reduces area as well as the power consumed. The
latch proposed consists of simple basic gates involving two inverters back to back which acts as
a bi-stable element and a transmission gate with the clock signal used to enable and disable the
rest of the circuit with impact on running the latch on Static Timing Analysis. The input test
vectors are either given by Automatic Test Pattern Generation (ATPG) or many other methods.
We model this using T-Simulation Program with Integrated Circuit Emphasis (T-SPICE) and see the power consumed.
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The power consumption of IC during test mode is higher than its normal mode. This brings the power as one of the major design constraints for today’s low power design technologies. In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too. The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode. The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%.
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FAULT DETECTION AND CLASSIFICATION ON SINGLE CIRCUIT TRANSMISSION LINE USING ...
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2024.06.01 Introducing a competency framework for languag learning materials ...
http://sandymillin.wordpress.com/iateflwebinar2024
Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
This webinar will introduce you to my framework, highlighting the key competencies I identified from my research. It will also show how anybody involved in language teaching (any language, not just English!), teacher training, managing schools or developing language learning materials can benefit from using the framework.
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Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
• The Committee on Oversight and Accountability is investigating the sources of funding and other support flowing to groups espousing pro-Hamas propaganda and engaged in antisemitic harassment and intimidation of students. The Committee on Oversight and Accountability is the principal oversight committee of the US House of Representatives and has broad authority to investigate “any matter” at “any time” under House Rule X.
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Best Digital Marketing Institute In NOIDA
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How libraries can support authors with open access requirements for UKRI funded books
Wednesday 22 May 2024, 14:00-15:00.
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Artificial Intelligence (AI) technologies such as Generative AI, Image Generators and Large Language Models have had a dramatic impact on teaching, learning and assessment over the past 18 months. The most immediate threat AI posed was to Academic Integrity with Higher Education Institutes (HEIs) focusing their efforts on combating the use of GenAI in assessment. Guidelines were developed for staff and students, policies put in place too. Innovative educators have forged paths in the use of Generative AI for teaching, learning and assessments leading to pockets of transformation springing up across HEIs, often with little or no top-down guidance, support or direction.
This Gasta posits a strategic approach to integrating AI into HEIs to prepare staff, students and the curriculum for an evolving world and workplace. We will highlight the advantages of working with these technologies beyond the realm of teaching, learning and assessment by considering prompt engineering skills, industry impact, curriculum changes, and the need for staff upskilling. In contrast, not engaging strategically with Generative AI poses risks, including falling behind peers, missed opportunities and failing to ensure our graduates remain employable. The rapid evolution of AI technologies necessitates a proactive and strategic approach if we are to remain relevant.
The approach at University of Liverpool.pptx
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Wednesday 22 May 2024, 14:00-15:00.
Azure Interview Questions and Answers PDF By ScholarHat
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special B.ed 2nd year old paper_20240531.pdf
Instagram:-
https://instagram.com/special_education_needs_01?igshid=YmMyMTA2M2Y=
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https://chat.whatsapp.com/JVakNIYlSV94x7bwunO3Dc
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https://youtube.com/@special_education_needs
Teligram :- https://t.me/special_education_needs
Slide Shere :-
https://www.slideshare.net/shabnambano20?utm_campaign=profiletracking&utm_medium=sssite&utm_source=ssslideview
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Mule 4.6 & Java 17 Upgrade | MuleSoft Mysore Meetup #46
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Event Link:-
https://meetups.mulesoft.com/events/details/mulesoft-mysore-presents-exploring-gemini-ai-and-integration-with-mulesoft/
Agenda
● Java 17 Upgrade Overview
● Why and by when do customers need to upgrade to Java 17?
● Is there any immediate impact to upgrading to Mule Runtime 4.6 and beyond?
● Which MuleSoft products are in scope?
For Upcoming Meetups Join Mysore Meetup Group - https://meetups.mulesoft.com/mysore/
YouTube:- youtube.com/@mulesoftmysore
Mysore WhatsApp group:- https://chat.whatsapp.com/EhqtHtCC75vCAX7gaO842N
Speaker:-
Shubham Chaurasia - https://www.linkedin.com/in/shubhamchaurasia1/
Priya Shaw - https://www.linkedin.com/in/priya-shaw
Organizers:-
Shubham Chaurasia - https://www.linkedin.com/in/shubhamchaurasia1/
Giridhar Meka - https://www.linkedin.com/in/giridharmeka
Priya Shaw - https://www.linkedin.com/in/priya-shaw
Shyam Raj Prasad-
https://www.linkedin.com/in/shyam-raj-prasad/
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How libraries can support authors with open access requirements for UKRI fund...
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Wednesday 22 May 2024, 14:00-15:00.
A Strategic Approach: GenAI in Education
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Synthetic Fiber Construction in lab .pptx
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Lpvlsi ppt
- 1. LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP By B.Nagajyothi
- 2. Flip-Flop have a great impact on circuit power consumption and speed. improving the performance one innovating approach is to increase the clock frequency. using high clock frequency Power consumption of the clock system increases.
- 3. An alternative clocking approach is based on the use of storage elements which are capable of capturing data on both rising and falling edges of the clock. Such storage elements are termed as Dual-Edge Triggered Flip-Flops (DETFFs). Double edge clocking can be used to save half of the power in the clock distribution network. The average power in a digital CMOS circuits is given by the following equation: Pavg = pt(CLV*Vdd* fclk) + Isc*Vdd + I leakage*Vdd
- 5. DETFF approach is preferred to reduce power dissipation Unlike SETFF, data is captured by both edges of the clock. Both positive and negative edges are used to sample the D input at alternate clock edges, and the appropriate sample is selected for the Q output by a clocked multiplexer (MUX).
- 6. CONVENTIONAL DUAL-EDGE TRIGGERED FLIP-FLOPS
- 7. STATIC EXPLICIT-PULSED DUAL EDGE TRIGGERED FLIP-FLOP
- 8. PROPOSED DUAL-EDGE TRIGGERED FLIP-FLOP
- 9. In the proposed DETFF, positive latch and negative latch are connected in parallel. These latches are designed using one transmission gate and two inverters connected back to back and the output of both the latches are connected to 2:1Mux as input. Mux is designed using one PMOS and one NMOS connected in series and gates are connected together and derived by the inverted CLK. Output of Mux is connected to the inverter for strengthening the output.
- 10. Back to back connected inverters hold the data when transmission gate is OFF and at the same time Mux sends the latched data to the inverter to get the correct D at the output. The proposed DETFF works as follows. When the CLK is low M3, M4 and M18 are ON and M5,M6 and M17 are OFF. Hence data hold by negative latch is transparent to Q. When CLK is high. The proposed DETFF works as follows. When the CLK is low M3, M4 and M18 are ON and M5,M6 and M17 are OFF. Hence data hold by negative latch is transparent to Q.
- 11. When CLK is high M5, M6 and M17 are ON and M3, M4 and M18 are OFF. If input D remains the same, Q also remains unchanged. On the other hand, if D is changed before the CLK then D will be hold by positive latch and the same value will be send to the output when CLK changes from Low to high and similarly for the transition of CLK from high to low.
- 12. RESULT