IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
An FPGA Based Floating Point Arithmetic Unit Using VerilogIJMTST Journal
Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation.
Multiplication is one of the common arithmetic operations in these computations. A high speed floating point
double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the proposed design is compliant
with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The
design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
FPGA Based Decimal Matrix Code for Passive RFID TagIJERA Editor
In this paper, Decimal Matrix Code is developed for RFID passive tag. The proposed DMC uses the decimal algorithm to obtain the maximum error detection and correction capability. The Encoder-Reuse Technique is used to minimize the area overhead of extra circuits without disturbing the complete encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The Simulation results reveals that the Decimal Matrix Code is effective than existing Matrix and Hamming odes in terms of Error Correction Capability. Xilinx ISE 14.7 Software is used for the simulation outputs. The complete design is verified and tested on Spartan-6 FPGA board. The performance of system is measured in terms of power, area and delay. The Synthesis result shows that, the power required for complete design of Decimal Matrix Code is 0.1mW with a delay of 3.109ns.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Congestion Control in Wireless Sensor Networks: A surveyIJERA Editor
Congestion is a major problem in almost all kinds of wireless networks such as mobile ad-hoc networks; wireless
sensor networks (WSNs). There are variety of applications of WSN such as defense, temperature monitoring,
health monitoring. Congestion occurs in the sensor network because of limited resources such as low processing
power of the sensor node. As all the sensor nodes are battery powered. Hence, congestion in the sensor network
results in waste of energy of sensor nodes. All the layers of protocol suite of the network can be involved in the
congestion control process. This paper gives a brief idea about various congestion control methods. In some of
the schemes, cross-layer design is applied for better results.
Validation of the Newly Developed Fabric Feel Tester for Its Accuracy and Rep...IJERA Editor
The present paper deals with a comprehensive study of reproducibility of the newly developed instrument to
study fabric handle characteristics using extraction principle. As reported earlier that a new nozzle extraction
method for objective measurement of fabric handle characteristics has been developed. The force exerted by the
fabric being drawn out of the nozzle is known as extraction force and the force exerted by the fabric at the side
wall of the nozzle is known as radial force. A few fabric samples have been tested on this newly developed
instrument and the effect of numbers of tests has been studied. It has been observed that minimum five samples
of a fabric test in this instrument gives lower standard deviation of the test results. Also the overall deviations of
results justified the reproducibility of the instrument and hence the said instrument if validated for its testing
parameters.
Graphical Password by Watermarking for securityIJERA Editor
The most common authentication method is to use alphanumerical usernames and passwords. This method has
been shown to have considerable disadvantage. For example, users tend to pick passwords that can be easily
guessed. On the other hand, if a password is very difficult to guess, then it is often difficult to remember. To
address this problem, some researchers have developed authentication methods that use pictures as passwords.
Graphical Password based on the fact that humans tend to remember images better. In this paper, we will
propose a new algorithm that using watermarking technique as the solution to solving image gallery attacks and
using the random character set generation for each image for resistance to shoulder surfing attack to provide
better system security. All the information images in registration phase will be process by copy right protection
of watermarking where the login page will check this information for security purposes.
An FPGA Based Floating Point Arithmetic Unit Using VerilogIJMTST Journal
Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation.
Multiplication is one of the common arithmetic operations in these computations. A high speed floating point
double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the proposed design is compliant
with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The
design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
FPGA Based Decimal Matrix Code for Passive RFID TagIJERA Editor
In this paper, Decimal Matrix Code is developed for RFID passive tag. The proposed DMC uses the decimal algorithm to obtain the maximum error detection and correction capability. The Encoder-Reuse Technique is used to minimize the area overhead of extra circuits without disturbing the complete encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The Simulation results reveals that the Decimal Matrix Code is effective than existing Matrix and Hamming odes in terms of Error Correction Capability. Xilinx ISE 14.7 Software is used for the simulation outputs. The complete design is verified and tested on Spartan-6 FPGA board. The performance of system is measured in terms of power, area and delay. The Synthesis result shows that, the power required for complete design of Decimal Matrix Code is 0.1mW with a delay of 3.109ns.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Congestion Control in Wireless Sensor Networks: A surveyIJERA Editor
Congestion is a major problem in almost all kinds of wireless networks such as mobile ad-hoc networks; wireless
sensor networks (WSNs). There are variety of applications of WSN such as defense, temperature monitoring,
health monitoring. Congestion occurs in the sensor network because of limited resources such as low processing
power of the sensor node. As all the sensor nodes are battery powered. Hence, congestion in the sensor network
results in waste of energy of sensor nodes. All the layers of protocol suite of the network can be involved in the
congestion control process. This paper gives a brief idea about various congestion control methods. In some of
the schemes, cross-layer design is applied for better results.
Validation of the Newly Developed Fabric Feel Tester for Its Accuracy and Rep...IJERA Editor
The present paper deals with a comprehensive study of reproducibility of the newly developed instrument to
study fabric handle characteristics using extraction principle. As reported earlier that a new nozzle extraction
method for objective measurement of fabric handle characteristics has been developed. The force exerted by the
fabric being drawn out of the nozzle is known as extraction force and the force exerted by the fabric at the side
wall of the nozzle is known as radial force. A few fabric samples have been tested on this newly developed
instrument and the effect of numbers of tests has been studied. It has been observed that minimum five samples
of a fabric test in this instrument gives lower standard deviation of the test results. Also the overall deviations of
results justified the reproducibility of the instrument and hence the said instrument if validated for its testing
parameters.
Graphical Password by Watermarking for securityIJERA Editor
The most common authentication method is to use alphanumerical usernames and passwords. This method has
been shown to have considerable disadvantage. For example, users tend to pick passwords that can be easily
guessed. On the other hand, if a password is very difficult to guess, then it is often difficult to remember. To
address this problem, some researchers have developed authentication methods that use pictures as passwords.
Graphical Password based on the fact that humans tend to remember images better. In this paper, we will
propose a new algorithm that using watermarking technique as the solution to solving image gallery attacks and
using the random character set generation for each image for resistance to shoulder surfing attack to provide
better system security. All the information images in registration phase will be process by copy right protection
of watermarking where the login page will check this information for security purposes.
Analysis of a Compessor Rotor using Finite Element AnalysisIJERA Editor
The compressor compresses its working fluid by first accelerating the fluid and then diffusing it to obtain a
pressure increase. In an axial flow compressor, air passes from one stage to the next, each stage raising the
pressure slightly. The energy level of air or gas flowing through it is increased by the action of the rotor blades
which exert a torque on the fluid which is supplied by an electric motor or a steam or a gas turbine.
In this present work we are taken the existing model of transonic compressor test rotors which contains 18
blades. The model was modeled in Pro-E Creo 5.0 with existing dimensions and analyzed using Ansys14.5. For
the analysis we are taken two different materials and compared the values.
For the further extension we changed the existing mode by decreasing the number of blades and analyzed with
different materials. The developed stress values of the existing model are compares with the modified models.
Our objective is to increase the performance of the rotor blade by changing the materials and the model. From
the observation we will suggest which model is suitable for the compressor rotor.
SRGM Analyzers Tool of SDLC for Software Improving QualityIJERA Editor
Software Reliability Growth Models (SRGM) have been developed to estimate software reliability measures such as
software failure rate, number of remaining faults and software reliability. In this paper, the software analyzers tool proposed
for deriving several software reliability growth models based on Enhanced Non-homogeneous Poisson Process (ENHPP) in
the presence of imperfect debugging and error generation. The proposed models are initially formulated for the case when
there is no differentiation between failure observation and fault removal testing processes and then this extended for the case
when there is a clear differentiation between failure observation and fault removal testing processes. Many Software
Reliability Growth Models (SRGM) have been developed to describe software failures as a random process and can be used
to measure the development status during testing. With SRGM software consultants can easily measure (or evaluate) the
software reliability (or quality) and plot software reliability growth charts.
A Review: Significant Research on Time And Frequency Synchronization In MIMO ...IJERA Editor
This paper proposes a fast and dependable procedure for timing and frequency synchronization of multiple-input
multiple- output (MIMO) orthogonal frequency division multiplexing (OFDM) systems. Orthogonal frequency
division multiplexing (OFDM) could be a outstanding technique for high info rate remote transmission. The
execution of OFDM framework is exceptionally touchy to transporter repeat Offset (CFO) that presents between
bearer electric resistances (ICI). Multi data multi yield frame work used for increasing various qualities increase
and limit of the framework. During this space repeat synchronization in associate OFDM framework is
contemplated and gave past work OFDM framework.
Natural Disaster (Tsunami) and Its Socio Economic and Environmental Impact – ...IJERA Editor
Natural Disaster (Tsunami) and Its Socio Economic And Environmental Impact – A Case Study Of
Kanyakumari Coast”. Kanyakumari is the southernmost district of Tamil Nadu. The software Arc Gis are used
to demarcate the Natural Disaster ( Tsunami) and its socio Economic and Environment Impact. The district lies
between longitudes is 77˚15‟ E 77˚36‟ Eastern longitudes. The Latitudes is 8˚03‟ N to 8˚35‟ Northern
latitudes.The District is bound by Tirunelveli District on the North and the East. The South Eastern boundary is
the Gulf of Manner. On the South and the South West, the boundaries are the Indian Ocean and the Arabian Sea.
On the West and Northwest it is bounded by Kerala. The Kanyakumari District total areas area is 1430.3Km.
The Coastal Villages elevations are 5 meter to 50 meter above mean sea level.Tirunelveli linked with the
Kanyakumari city by both road and railways. It is located south of Trichy at distance of 335km .Kanyakumari
was formed 1835 AD. It has an area of 1671.3 Km2 with 16.76 Lakh populations as per 2011 Census. The study
made by the researcher confirmed the various relief measures carried out in the affected areas in general and in
Agashteeshwaram Taluk in Kanyakumari measures be programmed in such a way that they facilities of their
livelihood besides regaining their aspirations of life.
A Microcontroller Based Intrusion Detection SystemIJERA Editor
A Microcontroller based Intrusion Detection System is designed and implemented. Rampant, Okintrusion to
restricted zones have highlighted the need for embedded systems that can effectively monitor, instantly alert
personnel of any breach in security and retrieve graphic evidence of any such activity in the secured area. At the
heart of the intrusion detection system is the PIC 168F77A Microcontroller that transmits pulses at 38 KHz. It is
suitably interfaced to a GSM modem that can send SMS on sight of infringement and a webcam that can take
snapshots. The report also presents the system software which has been developed in two parts: one in C++
Language using MPLAB KIT and the other written in AT COMMAND resident in the GSM modem. The
system is very cost-effective, uses easily available components and is adaptable to control systems.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...jmicro
This paper presents floating point multiplier capable of supporting wide range of application domains like scientific computing and multimedia applications and also describes an
implementation of a floating point multiplier that supports the IEEE 754-2008 binary interchange format with methodology for estimating the power and speed has been developed. This Pipelined vectorized floating point multiplier supporting FP16, FP32, FP64 input data and reduces the area, power, latency and increases throughput. Precision can be implemented by taking the 128 bit input operands.The floating point units consumeless power and small part of total area. Graphic Processor Units (GPUS) are specially tuned for
performing a set of operations on large sets of data. This paper also presents the design of a Double precision floating point multiplication algorithm with vector support. The single precision floating point multiplier is having a path delay of 72ns and also having the operating frequency of 13.58MHz.Finally this implementation is done in Verilog HDL using Xilinx ISE-14.2.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
computationally intense microprocessors capable of handling both fixed and floating- point mathematical
operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking
significant area. Over the years, the VLSI community has developed many floating-point adder algorithms
mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating
point adder with minimum time. Floating point numbers are used in various applications such as medical
imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the
performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL.
This paper discusses in detail the best possible FPGA implementation will act as an important design resource.
The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area,
and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A High Speed Transposed Form FIR Filter Using Floating Point Dadda MultiplierIJRES Journal
There is a huge demand in high speed area efficient parallel FIR filter using floating point dadda algorithm, due to increase performance of processing units. Area and spped are usually confictiong constraints so that improving speed results mostly in large areas. In our research we will try to determine the best solution to this problem by comparing the results of different multipliers. Different sized of two algorithm for high speed hardware multipliers were studied and implemented ie.dadda and booth multipliers. The working of these two multipliers were studied and implementing each of them separately in VHDL. The results of this research will help us to choose the better option between multipliers for floating point multiplier for fabricating different system.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Design and implementation of complex floating point processor using fpgaVLSICS Design
This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can
perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as
addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third
unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers.
The specific advancement in this processor is the new architecture introduced for complex arithmetic unit.
In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating
conversions. But using such hardware will lead to compromise between accuracy and number of bits used
to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that
compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The
complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for
real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single
precision numbers. The instruction set is specially designed to support integer, floating point and complex
floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the
processor is designed to implement on FPGA, the embedded block RAMs are utilized as RAM.
An Area Efficient Vedic-Wallace based Variable Precision Hardware Multiplier ...IDES Editor
The complete architecture with the necessary blocks
and their internal structures are proposed in this paper. In
this algorithm the complete variable precision format is
utilized for the multiplication of the two numbers with a size
of nxn bits. The internal multiplier is choosen for m bit size
and is implemented using vedic-wallace structure for high
speed implementation. The architecture includes the
calculation of all the fields in the format for complete output.
The exponent of the final result is obtained by using carry
save adder for fast computations with less area utilization.
This multiplier uses the concept of MAC unit, giving rise to
more accurate results having a bits size of the final result will
be 2n2.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Knowledge engineering: from people to machines and back
Lp2520162020
1. Pardeep Sharma, Gurpreet Singh / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.2016-2020
Analysing Single Precision Floating Point Multiplier on Virtex 2P
Hardware Module
Pardeep Sharma, Gurpreet Singh
Assistant Professor, Department of Electronics & Communication,
Shaheed Bhagat Singh State Technical Campus, Ferozepur.
Abstract
FPGAs are increasingly being used in the The first part of the floating point multiplier is sign
high performance and scientific computing which is determined by an exclusive OR function of
community to implement floating-point based the two input signs. The second part is the exponent
hardware accelerators. We present FPGA which is calculated by adding the two input
floating-point multiplication. Such circuits can be exponents. The third part is significand or mantissa
extremely useful in the FPGA implementation of which is determined by multiplying the two input
complex systems that benefit from the significands each with a “1” concatenated to it. That
reprogramability and parallelism of the FPGA “1” is the hidden bit. The main applications of
device but also require a general purpose floating points today are in the field of medical
multiplier unit. While previous work has imaging, biometrics, motion capture and audio
considered circuits for low precision floating- applications, including broadcast, conferencing,
point formats, we consider the implementation of musical instruments and professional audio.
32-bit Single precision circuits that also provide
rounding and exception handling. We introduce II. FPGA (FIELD PROGRAMMABLE GATE
an algorithm for multiplication and analyze its ARRAY)
performance on Virtex2P hardware module at FPGA stands for Field Programmable Gate
speed grade -7. Array. It is a semiconductor device containing
programmable logic components and programmable
Keywords - Floating point Multiplier, FPGAs, interconnects. The programmable logic components
Xilinx and Virtex. can be programmed to duplicate the functionality of
basic logic gates such as AND, OR, XOR, NOT or
I. INTRODUCTION more complex combinational functions such as
Many people consider floating-point decoders or simple mathematical functions [3] [8].
arithmetic an esoteric subject. This is rather In most FPGAs, these programmable logic
surprising because floating-point is ubiquitous in components (or logic blocks, in FPGA parlance) also
computer systems. Almost every language has a include memory elements, which may be simple flip
floating-point data type. Floating Point numbers flops or more complete blocks of memories. A
represented in IEEE 754 format are used in most of hierarchy of programmable interconnects allows the
the DSP Processors. Floating point arithmetic is logic blocks of an FPGA to be interconnected as
useful in applications where a large dynamic range is needed by the system designer, somewhat like a one-
required or in rapid prototyping applications where chip programmable breadboard shows in figure 1.
the required number range has not been thoroughly These logic blocks and interconnects can be
investigated. The floating Point Multiplier IP helps programmed after the manufacturing process by the
designers to perform floating point Multiplication on customer/designer (hence the term "field
FPGA represented in IEEE 754 single precision programmable", i.e. programmable in the field) so
floating point format. The single precision multiplier that the FPGA can perform whatever logical function
is divided into three main parts corresponding to the is needed [4].
three parts of the single precision format [1]. The
normalized floating point numbers have the form of
Z = (- )* * (1.M) (1)
Where M = m22 2-1 + m21 2-2 + m20 2-3+…+ m1
2-22+ m0 2-23;
Bias = 127.
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Vol. 2, Issue 5, September- October 2012, pp.2016-2020
Example:
Step 1: Suppose a decimal number 129.85 is taken.
Step 2: Convert it into binary number of 24 bits
i.e.10000001.1101110000000000.
Step 3: Shift the radix point to the left such that there
will be only one bit which is left of the radix point
and this bit must be 1. This bit is known as hidden
bit.
Step 4: Count the number of times radix points is
shifted to the left say „x‟. The number which is
formed after shifting of radix point is
1.00000011101110000000000. Here x=7.
Step 5: The number which is after the radix point is
called mantissa which is of 23 bits and the whole
number including hidden bit is called significand
which is of 24 bits.
Step 6: The value „x‟ must be added to 127 to get the
original exponent value which is 127 + „x‟. In this
Figure 1: FPGA board case exponent is 127 + 7 = 134 which is 10000110.
FPGAs are generally slower than their Step 7: Number is +ve hence MSB of number is 0.
application specific integrated circuit (ASIC) Step 8: Now assemble result into 32 bit format in the
counterparts, as they can't handle as complex a form of sign, exponent and mantissa
design, and draw more power. However, they have 01000011000000011101110000000000.
several advantages such as a shorter time to market, IV. MULTIPLICATION ALGORITHM FOR FLOATING
ability to re-program in the field to fix bugs, and POINT NUMBERS
lower non recurring engineering cost costs. Vendors As stated in the introduction, normalized floating
can sell cheaper, less flexible versions of their point numbers have the form of
FPGAs which cannot be modified after the design is
committed. The development of these designs is Z = (- ) * * (1.M) (1)
made on regular FPGAs and then migrated into a Where M = m22 2-1 + m21 2-2 + m20 2-3+…+ m1
fixed version that more resembles an ASIC. 2-22+ m0 2-23;
Complex programmable logic devices, or CPLDs, Bias = 127.
are another alternative. To multiply two floating point numbers the
following steps are taken [1] [6]:
III. FLOATING POINT FORMAT Step 1: Multiplying the significand; i.e.
The advantage of floating point format over (1.M1*1.M2)
fixed point format is the range of numbers that can Step 2: Placing the decimal point in the result
be presented with the fixed number of bits. Floating Step 3: Adding the exponents; i.e. (E1 + E2 – Bias)
point number is composed of three fields and can be Step 4: Obtaining the sign; i.e. s1 xor s2 and put the
of 16, 18, 32 and 64 bit. Figure shows the IEEE result together
standard for floating point numbers [2]. Step 5: Normalizing the result; i.e. obtaining 1 at the
MSB of the results‟ significand shown in figure 3.
31 30 22 0
Sign Exponent Mantissa
Figure 2: Standard for floating point numbers
1 bit sign of signifies whether the number is
positive or negative. „1‟ indicates negative number
and „0‟ indicate positive number. 8 bit exponent
provides the exponent range from E (min) =-126 to
E (max) =127. 23 bit mantissa signifies the fractional
part of a number the mantissa must not be confused
with the significand. The leading „1‟ in the Figure 3: Normalization of sign, exponent and
significant is made implicit [3]. mantissa
We present a floating point multiplier in
A. Conversion of Decimal to Floating numbers which rounding technique is implemented. Rounding
Conversion of Decimal to Floating point 32 bit support can be added as a separate unit that can be
formats is explained in 1 & 2 example.
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accessed by the multiplier or by a floating point EB = EB-true + bias And EA + EB = EA-true + EB-
adder, thus accommodating for more precision. The true + 2 bias
multiplier structure; Exponents addition, Significand So we should subtract the bias from the resultant
multiplication, and Result‟s sign calculation are exponent otherwise the bias will be added twice.
independent shown in figure 5.4. The significand Exponent Result = 10000111 (E1) +10000110 (E2)
multiplication is done on two 24 bit numbers and – 01111111 (Bias 127) = 10001110
results in a 48 bit product, which we will call the Eresult = 10001110
intermediate product (IP). The IP is represented as Step 4: Obtaining the sign; i.e. s1 xor s2 and put the
(47 downto 0). The following sections detail each result together
block of the floating point multiplier. 0 Xor 0 = 0, so the sign of the number is +ve
0 10001110
10.011111001111110010011101000110100111100
1010000
Step 5: Normalizing the result
Normalize the result so that there is a 1 just before
the radix point (decimal point). Moving the radix
point one place to the left increments the exponent
by 1; moving one place to the right decrements the
exponent by 1
Before Normalizing
0 10001110
10.011111001111110010011101000110100111100
1010000
After normalization
0 10001111
1.0011111001111110010011101000110100111100
1010000 (including hidden bit)
Step 6: Rounding the result to the nearest number [3]
[5]
The mantissa bits are more than 23 bits (mantissa
available bits); rounding is needed. If we applied the
round to nearest rounding mode then the stored value
is:
01000111100111110011111100100111(After
Figure 4: Algorithm for floating point multiplication rounding)
Step 7: Checking for underflow/overflow occurrence
A. An example of floating point multiplier with There are four main cases that the exponent is
proposed algorithm affected by normalization. It depends upon the
A: 0 10000111 10010101001110000101000 (32 Eresult that is calculated above [7] i.e.
bit) Table 1 Normalization effect on result‟s Exponent
B: 0 10000110 10010010011010111000010 (32 and Overflow/Underflow detection
bit)
To multiply A and B Eresult Category Comments
Step 1: Multiplying the significand (including hidden -125 ≤ Underflow Can‟t be
bit) Eresult < 0 compensated
110010101001110000101000 (24 bit)* during
110010010011010111000010 (24 bit) normalization
=10011111001111110010011101000110100111100
May turn to
1010000 (48 bit)
normalized
Step 2: Placing the decimal point in the result
Eresult = 0 Zero number during
10.011111001111110010011101000110100111100
normalization (by
1010000
adding 1 to it)
Step 3: Adding the exponents; i.e. (E1 + E2 – Bias)
May result in
Adding of exponents =10000111 (E1) +10000110
1 < Eresult Normalized overflow during
(E2)
< 254 number Normalization
The exponent representing the two numbers is
255 ≤ Overflow Can‟t be
already shifted/biased by the bias value (127) and is
Eresult compensated
not the true exponent; i.e. EA = EA-true + bias and
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Vol. 2, Issue 5, September- October 2012, pp.2016-2020
There are some special conditions while VI. SIMULATION WAVEFORM (USING
implementing floating point multiplier which needs MODEL SIM SIMULATOR)
to be handle these are explained in table. Case 1: When both the numbers are of same sign
The flow graph of overall algorithm for floating 1st input no. 405.22 =
point multiplier including rounding is shown in 01000011110010101001110000101000
figure 5. 2nd input no. 201.21 =
01000011010010010011010111000010
Desired output no. 81534.31 =
01000111100111110011111100100111
Figure 6: Signals in Model Sim
Simulation result 81534.31 =
01000111100111110011111100100111
Figure 5: Floating point multiplier flow graph
V. FINAL RESULTS/SYNTHESIS REPORT
Results of Virtex2P FPGA (XC2VP2-FG256) Speed
grade: -7 Figure 7: Simulation result for Floating point
multiplier
Table 2 Results/ Synthesis report
Seria Logic Utilization Used Avail Utilizati Case 2: When both the numbers are of different
l no. able on in sign
%age 1st input No. 721.51 =
1. Number of Slices 663 1408 47 01000100001101000110000010100011
2. Number of Slice 31 2816 1 2nd input No -902.12 =
Flip Flops 11000100011000011000011110101110
3. Number of 4 input 1232 2816 43 Desired output no -650888.6 =
LUTs 11001001000111101110100010001000
4. Number of 96 140 68
bonded IOBs
5. Number of 1 16 6
GCLKs
6. Memory Usage 189172
kilobytes
7. Combinational
Delay
With offset 61.459
Without offset ns
59.085 Figure 8: Signals in Model Sim
ns Simulation result -650888.6 =
11001001000111101110100010001000
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5. Pardeep Sharma, Gurpreet Singh / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.2016-2020
Figure 9: Simulation result for Floating point
multiplier
VII. CONCLUSIONS
The floating point multiplier has been
designed, optimized and implemented on Virtex
module. From the final results it is concluded that
implementation of floating point multiplier on
Virtex2P (XC2VP2-FG256) Speed Grade: -7 causes
small combinational delay i.e. 61.459 ns and less
number of slices (utilization of area) i.e. 663.
ACKNOWLEDGMENT
I would like to thanks the anonymous
reviewers for their insightful comments.
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