This document summarizes a presentation about building an open control stack for quantum computers using the RISC-V ecosystem. It discusses using a RISC-V based Quantum Instruction Set Architecture (QUASAR) to control quantum processors. It describes implementing QUASAR as a co-processor that interfaces with a RISC-V processor via a RoCC interface. The presentation outlines developing the software and hardware stack, from a high-level circuit description to generating control pulses on an FPGA-based prototype system. Scalability and integrating multiple quantum processors and FPGAs is discussed as future work.

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CONTRIBUTE.
COLLABORATE.
COMMERCIALIZE.
December 8-10 | Virtual Event

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December 8-10 | Virtual Event
Building an Open Control Stack for Quantum Computers
using RISC-V Ecosystem
Anastasiia Butko
Research Scientist
Lawrence Berkeley National Laboratory
#RISCVSUMMIT

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Quantum Computers
Introduction

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QUANTUM COMPUTER VS. ACCELERATOR

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INACCURACY OF TERMINOLOGY
Quantum computer ≠ Quantum Processing Unit (QPU)

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QUANTUM SYSTEM
Quantum computer ≠ Quantum Processing Unit
Quantum computer = Quantum Processing Unit + Control Hardware
User
Quantum Processing Unit
Cryogenic Control Architecture for Large-Scale Quantum Computing, J. M. Hornibrook et al., Phys. Rev. Applied 3, 024010,
(2015)

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Abstraction Levels
Main concepts in quantum computing

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• have been an active area of study long before any physical implementation of
quantum computers became available
• recent research and development bring the awareness of hardware to the high levels
(NISQ applications), but abstraction and modularity is crucial for scalability
ABSTRACTION LEVELS
Awareness across the Stack

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• have been an active area of study long before any physical implementation of
quantum computers became available
• recent research and development bring the awareness of hardware to the high levels
(NISQ applications), but abstraction and modularity is crucial for scalability
ABSTRACTION LEVELS
Awareness across the Stack
• operate at the level of physical pulses with very limited or no notion about software

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ABSTRACTION LEVELS
Awareness across the Stack
• Bridging the gap in between the theory and practice

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System Architecture
How is it done today and why it is NOT going to work in the future

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CONTROL UNIT
Software vs. Hardware Implementation
Software Control
• Everything in one place
• Easier to implement and modify
• NISQ experiments
• Long latency
• Limited bandwidth
• Limited flexibility (bit granularity)
• Poor scalability
S e q u e n c e
B a n d w i d t h
L a t e n c y 1 L a t e n c y 2
M E M
✅
✅
✅
❌
❌
❌
❌
L O A D

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Q A S M
L a t e n c y 1 L a t e n c y 2
M E M
Hardware Control
• Reduced latency
• Fast feedback
• Extended functionality in-place
• Potential scalability
• Separation of concepts
• Beyond-NISQ
• Requires specialized solution
• Harder to implement and modify
• Requires commercial support
❌
❌
✅
✅
✅
✅
✅
✅
CONTROL UNIT
Software vs. Hardware Implementation
❌

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• Quantum Instruction Set Architecture (QUASAR)
• extension to RISC-V ISA (open-source, modular, active community, eco-system)
• supports quantum operations, timing control, etc.
• transparent, adaptable, open
• New tools in hardware design and evaluation
• high-level HDL (Chisel)
• modular and parametrizable modules
Requires specialized solution
Harder to implement and modify
HARDWARE APPROACH
Building an efficient software-hardware interface
✅
✅

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RISC-V for Quantum
How we build and evaluate quantum control stack using RISC-V eco-system

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QUASAR Extensions
Different approaches
• Greenfield extension approach
• Tightly integrated with the processor micro-architecture
• High-level of customization
• May cause conflicts with other extensions
• Requires compiler extension
• RoCC co-processor adaptation
• Existing software support
• Modular approach easily interactable into a big system
• Lower-level of customization and flexibility
P r o c e s s o r
C o r e
L 1 I L 1 D
R I S C - V R o c k e t R o C C
m r q
m r s
c m d
r e s p
b u s y
Q U A S A R
D E C
W B
M E M
Q I
T S R
M S R
Q
P
U

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QUASAR Extensions
Different approaches
• Greenfield extension approach
• Tightly integrated with the processor micro-architecture
• High-level of customization
• May cause conflicts with other extensions
• Requires compiler extension
• RoCC co-processor adaptation
• Existing software support
• Modular approach easily interactable into a big system
• Lower-level of customization and flexibility
P r o c e s s o r
C o r e
L 1 I L 1 D
R I S C - V R o c k e t R o C C
m r q
m r s
c m d
r e s p
b u s y
Q U A S A R
D E C
W B
M E M
Q I
T S R
M S R
Q
P
U
• Quantum ISA Spec evaluation
• Metrics and methodology
• Comparison against existing solutions
• Scalability and performance projections
Understanding Quantum Control Processor Capabilities and Limitations through Circuit
Characterization, A. BUTKO et al., IEEE International Conference on Rebooting Computing
(ICRC), December 2020
https://arxiv.org/abs/1909.11719

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System Architecture Implementation
From core to system architecture
• Using Freedom Platform (SiFive) for system integration on VC707 FPGA

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• Using Freedom Platform (SiFive) for system integration on VC707 FPGA
• Run Linux
• Remote communication
• Periphery support
• Security
System Architecture Implementation
From core to system architecture

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• Using Freedom Platform (SiFive) for system integration on VC707 FPGA
• RoCC Interface
• Pulse Library Table (PLT)
• Additional functionalities
(loading Waveform Memory
for calibration, readout post-
processing )
System Architecture Implementation
From core to system architecture

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• Using Freedom Platform (SiFive) for system integration on VC707 FPGA
• Analog backend
• Phase manipulation
• Fast readout
• Timing control
System Architecture Implementation
From core to system architecture

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High-level circuit
QUASAR library
Linux OS
int main() {
qReset(); //reset hardware resources to ZERO
x90i(1); //apply the X90 immediate gate on qubit 1
tsi(5); //advances the time stamp on 5 cycles
y90i(0); //apply the Y90 immediate gate on qubit 0
return 0;
}
#define XCUSTOM_ACC 0
#define q_DO_X90 1
#define x90i(qid)
ROCC_INSTRUCTION_0_R_R(XCUSTOM_ACC, qid, 0, q_DO_X90);
Software Stack
From high-level circuit description to Linux executable
Control Pulses generated by
the Analog Backend

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FUTURE WORK
• How scalable are our approaches?
• QUASAR supports up to 512 qubits
• Quantum vector extension (qV) to express single-instruction multiple-qubits multiple-gates parallelism
• Multiple QUASAR co-processors, multiple FPGAs
• Bit manipulation for error-correction code
• Cool technologies
• Cryo-CMOS: energy dissipation, noise
• Superconducting: how the micro-architecture will change?
… and much more

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Advanced Quantum Testbed @ LBNL
Superconducting Quantum Processors at the Entanglement Frontier
1 mW Dilution fridge Cold stage
Commercial
Control
LBNL/ATAP
Control
3D Integrated Quantum Processor
Units (QPU)
Team: LBNL, UC Berkeley,
Bleximo, MIT-LL

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