LECTURE NOTES-DSD1.doc

GEETHANJALI INSTITUTE OF SCIENCE & TECHNOLOGY
(Approved by AICTE, New Delhi & Affiliated to JNTUA, Anantapuramu)
3rd Mile, Bombay Highway, Gangavaram (V), Kovur(M), SPSR Nellore (Dt),
Andhra Pradesh, India- 524137
DEPARTMENT OF ECE
LECTURE NOTES
ON
DIGITAL SYSTEM DESIGN (15A04504)
III B.TECH I SEMESTER
PREPARED BY
(SK.M.SHAHINA)

IIIB.TECH-I SEM(R15), ECE: DIGITAL SYSTEM DESIGN
Geethanjali instituteof science andtechnology,Nellore
Syllabus:
UNIT-I
CMOS LOGIC: Introduction to logic families, CMOS logic, CMOS logic families; BIPOLAR LOGIC
AND INTERFACING: Bipolar logic, Transistor logic, TTL families, CMOS/TTL interfacing, low voltage
CMOS logic and interfacing, Emitter coupled logic, Comparison of logic families, Familiarity with
standard 74-series and CMOS 40- series-ICs – Specifications.
UNIT-II
HARDWARE DESCRIPTION LANGUAGES: HDL Based Digital Design, The VHDL Hardware
Description Language–Program Structure, Types, Constants and Arrays, Functions and procedures,
Libraries and Packages, Structural design elements, Dataflow design elements, Behavioral design
elements, The Time Dimension, Simulation, Test Benches, VHDL Features for Sequential Logic Design,
Synthesis
UNIT-III
COMBINATIONAL LOGIC DESIGN PRACTICES: Description of basic structures like Decoders,
Encoders, Comparators, Multiplexers ( 74 –series MSI); Design of complex Combinational circuits using
the basic structures; Designing Using combinational PLDs like PLAs, PALs ,PROMs CMOS PLDs;
Adders & sub tractors, ALUs, Combinational multipliers; VHDL models for the above standard building
block ICs.
UNIT-IV
SEQUENTIAL MACHINE DESIGN PRACTICES: Review of design of State machines; Standard
building block ICs for Shift registers, parallel / serial conversion , shift register counters, Ring counters;
Johnson counters, LFSR counter ; VHDL models for the above standard building block ICs. Synchronous
Design example using standard ICs
UNIT –V
Design Examples (using VHDL): Barrel shifter, comparators, floating-point encoder, and dual parity
encoder.
Sequential logic Design: Latches & flip flops, PLDs, counters, shift register and their VHDL models.

UNIT-I
Introduction to Logic Family:
Logic Family: - A logic family is a collection of different integrated-circuit chips that have similar
input, output, and internal circuit characteristics, but that perform different logic functions. Chips
from the same family can be interconnected to perform any desired logic function.
Classification of Logic Families:- Logic families are mainly classified as
1. Bipolar Logic families and
2. Uni polar Logic families
1. Bipolar Logic families: A bipolar IC mainly uses bipolar devices like diodes and transistors as
their principle component, in addition to passive elements like resistors and capacitors. Bipolar
ICs are sub classified as Saturated Bipolar Logic family and Un-Saturated Bipolar Logic family.
The distinction between saturated logic and unsaturated logic is that, where as in saturated logic,
the transistors used in the IC are driven into saturation, in Un saturated logic, the transistors are
not driven into saturation.
i) Saturated bipolar logic family: In this family, the transistors used in the ICs are driven into
saturation.
Examples: a) Transistor Transistor Logic (TTL)
b) Resistor Transistor Logic (RTL)
c) Direct-Coupled transistor Logic (DCTL)
d) Diode Transistor Logic (DTL)
e) High Threshold Logic (HTL)
f) Integrated Injection Logic (IIL orI2L)
ii) Un Saturated logic family: In this family, the transistors used in the ICs are not driven into
saturation.
Examples: a) Schottky TTL
b) Emitter Coupled Logic (ECL)
2. Unipolar Logic families: It mainly uses unipolar devices like MOSFETs as their principle
component, in addition to passive elements like resistors and capacitors. These logic families have

the advantages of high speed and lower power consumption than bipolar families. These are
classified as
i) PMOS or P-Channel MOS Logic Family
ii) NMOS or N-Channel MOS Logic Family
iii) CMOS Logic Family
CMOS Logic and MOS Transistors:
CMOS LOGIC:- The basic building blocks in CMOS logic circuits are MOS transistors. CMOS
means Complementary Metal Oxide Semiconductor. Before introducing MOS transistors and
CMOS logic circuits, we must know about CMOS logic levels.
1) CMOS Logic Levels: A typical CMOS logic circuit operates from a 5-volt power supply.
Such a circuit may interpret any voltage in the range 0–1.5 V as a logic 0, and in the range 3.5–
5.0 V as a logic 1.Thus, the definitions of LOW and HIGH for 5-volt CMOS logic are as shown
in Figure. Voltages in the intermediate range are not expected to occur except during signal
transitions, and yield undefined logic values (i.e., a circuit may interpret them as either 0 or 1).

Fig.1 (a): Logic Levels for typical CMOS logic circuits.
2) MOS Transistors:-
A MOS transistor can be modeled as a 3-terminal device that acts like a voltage controlled
resistance. As suggested by Figure, an input voltage applied to one terminal controls the
resistance between the remaining two terminals. In digital logic applications, a MOS transistor is
operated so its resistance is always either very high (and the transistor is “off”) or very low (and
the transistor is “on”).
Fig.1 (b): MOS transistor as a voltage controlled resistance
There are two types of MOS transistors, n-channel and p-channel; the names refer to the type of
semiconductor material used for the resistance-controlled terminals.
i) n-channel MOS (NMOS) transistor:
The circuit symbol for an n-channel MOS (NMOS) transistor is shown in Fig1(c). The terminals
are called gate, source, and drain. (Note that the “gate” of a MOS transistor has nothing to do
with a “logic gate.”) As you might guess from the orientation of the circuit symbol, the drain is
normally at a higher voltage than the source. The voltage from gate to source (Vgs) in an NMOS
transistor is normally zero or positive. If Vgs = 0, then the resistance from drain to source (Rds) is
very high, on the order of a mega ohms (106 ohms) or more. As we increase Vgs (i.e., increase the
voltage on the gate), Rds decreases to a very low value, 10 ohms or less in some devices.

Fig.1 (c): NMOS Transistor
ii) p-channel MOS (PMOS) transistor:
The circuit symbol for a p-channel MOS (PMOS) transistor is shown in Fig1(d). Operation is
analogous to that of an NMOS transistor, except that the source is normally at a higher voltage
than the drain, and Vgs is normally zero or negative. If Vgs is zero, then the resistance from
source to drain (Rds) is very high. As we algebraically decrease Vgs (i.e., decrease the voltage on
the gate), Rds decreases to a very low value.
The gate of a MOS transistor has very high impedance. That is, the gate is separated from the
source and the drain by an insulating material with a very high resistance. However, the gate
voltage creates an electric field that enhances or retards the flow of current between source and
drain. This is the “field effect” in the “MOSFET” name.
Fig.1 (d): PMOS Transistor
The MOS transistor can be viewed as simple ON/OFF switch

CMOS Structure:
A generalized CMOS logic circuit consists of two transistor nets nMOS and pMOS. The pMOS
transistor net is connected between the power supply and the logic gate output called as pull-up
network Whereas the nMOS transistor net is connected between the output and ground called as
pull-down network. Depending on the applied input logic, the PUN connects the output node to
VDD and PDN connects the output node to the ground as shown in fig.1(e).
√ Pull-up network contains PMOS transistor and pull-down network consists of NMOS
Transistor.
√ When input applied as logic ‘0’(L) the PMOS transistor is in ON condition and that
translates output to logic ‘1’(H), i.e., applied voltage is pulled up to 5V(H) from 0V(L) by
PMOS transistor. Hence it is called as Pull-Up transistor.
√ When input applied as logic ‘1’(H) the NMOS transistor is in ON condition and that
translates output to logic ‘0’(L), i.e., applied voltage is pulled down to 0V(L) from 5V(H)
by NMOS transistor. Hence it is called as Pull-Down transistor.
Fig.1 (d): Structure of CMOS Logic Circuit
Pull-up network (PUN) and Pull-down network (PDN) are dual logic networks consisting of MOS
transistors in series/parallel connection.
i) Building CMOS gates (n-side):
For making the n-side (pull-down network) use the un-inverted expression.
For e.g.: Implement F = For n-side use F = (A • B) + (C • D)
1. AND expressions are implemented using series connection of n transistors
2. OR expressions are implemented using parallel connection of n transistors

(A • B) (C • D) (A • B) + (C • D)
AND: Series AND: Series OR: Parallel
ii) Building CMOS gates (p-side):
For making the p-side (pull-up network) invert the expression used for n-side.
For e.g.: Implement F = ((A • B) + (C • D))
1. For p-side invert above expression:
2. AND expressions are implemented using series connection of p transistors
3. OR expressions are implemented using parallel connection of p transistors
(A +B) (C + D) (A +B) • (C + D)
OR: Parallel OR: Parallel AND: Series
● Why we use PMOS for PUN and NMOS for PDN?
Fig. 1(e): CMOS Circuits with Threshold Drop

CMOS Inverter circuit:-
CMOS Inverter
NMOS and PMOS transistors are used together in a complementary way to form CMOS logic. The
simplest CMOS circuit, a logic inverter, requires only one of each type of transistor, connected as shown in
Fig. 2(a). The power supply voltage, VDD, typically may be in the range 3.5-5 V, and is most often set at
5.0 V for compatibility with TTL circuits. Ideally, the functional behavior of the CMOS inverter circuit
can be characterized by just two cases tabulated in Fig. 2(a).
Operation:
Case (i): VIN is 0.0 V. In this case, the bottom, n-channel transistor Q1 is off, since its Vgs is 0, but the top
p-channel transistor Q2 is on, since its Vgs is a large negative value (-5.0 V). Therefore, Q2 presents only a
small resistance between the power supply terminal (VDD, 5.0V) and the output terminal (VOUT), and the
output voltage is 5.0 V.
Case (ii): VIN is 5.0 V. Here, Q1 is on, since its Vgs is a large positive value (+5.0 V), but Q2 is off, since
its Vgs is 0. Thus, Q1 presents a small resistance between the output terminal and ground, and the output
voltage is 0 V.
Note: From case (i) & (ii) we can conclude that the operation of a basic CMOS circuit gives
INVERTING operation.
Fig. 2(a): CMOS Inverter Circuit
With the foregoing functional behavior, the circuit clearly behaves as a logical inverter, since a 0-volt input
produces a 5-volt output, and vice versa. Another way to visualize CMOS operation uses switches. As
shown in Fig.2 (c), the n-channel (bottom) transistor is modeled by a normally-open switch, and the p-

channel (top) transistor by a normally-closed switch. Applying a HIGH voltage changes each switch to the
opposite of its normal state, as shown in fig.2(d).
.
Fig. 2(b): Truth table and Logic symbol of Inverter
The switch model gives rise to a way of drawing CMOS circuits that makes their logical behaviour more
readily apparent. As shown in Fig.2(a), different symbols are used for the p and n-channel transistors to
reflect their logical behaviour. The n-channel transistor (Q1) is switched “on,” and current flows between
source and drain, when a HIGH voltage is applied to its gate; this seems natural enough. The p-channel
transistor (Q2) has the opposite behaviour. It is “on” when a LOW voltage is applied; the inversion bubble
on its gate indicates this inverting behaviour.
Fig. 2(c): Switch model for CMOS inverter Fig. 2(d): Switch model for CMOS
(LOW input) inverter (HIGH input)
Transfer Characteristics of CMOS inverter with Noise Margin:
Fig. 2(e) shows the transfer characteristics of a CMOS inverter with Noise margin. The parameter VIH and
VIL determine the noise margins and are defined as the point at which dv0/dt =-1.

For VI ≤ VIL and VI ≥ VIH , the gain is less than unity and the output changes slowly with input voltage. On
the other hand, when the input voltage is in the range of VIL < VI < VIH , the inverter gain is greater than
unity, and the output signal changes rapidly with a change in input voltage.
(OR)
Fig. 2(e): CMOS inverter voltage transfer characteristics
CMOS 2 Input NAND gate:
√ NAND gate is one of the basic logic gates to perform the digital operation on the input signals.
√ It is the combination of AND Gate followed by NOT gate i.e. it is the opposite operation of AND
gate where the Logic NAND gate is complementary of AND gate.
√ The logic output of NAND gate is low (FALSE) only when the inputs are high (TRUE).
√ To implement 2-Input NAND gate using CMOS logic we require 2 pull-up PMOS and 2 pull-
down NMOS transistors.
√ Fig.(3) shows the function table, logic symbol and circuit diagram for CMOS 2-input NAND gate.
It consists of two P-channel MOSFETs Q2 and Q4, connected in parallel and two N-channel
MOSFETs, Q1 and Q3 connected in series.
√ Fig.3(d) shows the switch model for 2-input NAND gate.

Fig.3(a): 2-input CMOS NAND gate Fig.3(b),(c): Function table and Logic
symbol of NAND Gate
Operation:
Case (i): When A=B=0 V, then both NMOS transistors are in OFF state since its VGSA = VGSB = 0 V.
Both PMOS transistors (Q2, Q4) are in ON state, since its VGSA and VGSB voltage is large negative (-
5V). So a PMOS transistor presents only a small resistance between VDD and output. Hence output is 5 V.
Case (ii): When A=0 V and B=5 V, then NMOS transistor (Q1) is in OFF state, since its input voltage
VGSA= 0 V and NMOS transistor (Q3) is in ON state since its VGSB=5V. PMOS transistor (Q2) is in ON
state, since its VGSA= -5V and PMOS transistor (Q4) is in OFF state, since its VGSB=0V. So PMOS
transistor Q2 presents only a small resistance between VDD and output. Hence output is 5 V.
Case (iii): When A=5 V and B=0 V, then NMOS transistor (Q1) is in ON state, since its input voltage
VGSA= +5V and NMOS transistor (Q3) is in OFF state since its VGSB=0V. PMOS transistor (Q2) is in
OFF state, since its VGSA= 0V and PMOS transistor (Q4) is in ON state since its VGSB=-5V. So PMOS
transistor Q4 presents only a small resistance between VDD and output. Hence output is 5 V.
Case (iv): When A=B=5 V, then both PMOS transistors are in OFF state, since its input voltages VGSA =
VGSB = 0 V. Both NMOS transistors (Q1, Q3) are in ON state since its VGSA and VGSB is large positive
(+5V). So an NMOS transistor presents only a small resistance between Output and ground. Hence output
is 0 V.

Fig.3(a): Switch model for 2-input CMOS NAND gate
CMOS 3 Input NAND gate:
Fig.3(e) shows the function table and circuit diagram for 3-i/p CMOS NAND gate.
Fig.3(e): 3-Input CMOS NAND gate.
CMOS 2-Input NOR gate :
√ NOR gate is one of the basic logic gates to perform the digital operation on the input signals.
√ It is the combination of OR Gate followed by NOT gate i.e. it is the opposite operation of OR gate
where the Logic NOR gate is complementary of OR gate.
√ The logic output of NOR gate is HIGH (True) only when the inputs are LOW (False).
√ To implementation 2 Input NOR gate using CMOS logic we require 2 pull-up PMOS and 2 pull-

√ Fig.(4) shows the function table, logic symbol and circuit diagram for CMOS 2-input NOR gate. It
consists of two P-channel MOSFETs Q2 and Q4, connected in series and two N-channel MOSFETs,
Q1 and Q3 connected in parallel.
Working operation:
Case (i): When A=B=0 V, then both NMOS transistors are in OFF state, since its VGSA = VGSB = 0 V.
Both PMOS transistors (PA, PB) are in ON state, since its VGSA and VGSB voltage is large negative (-
Case (ii): When A=0 V and B=5 V, then NMOS transistor (NA) is in OFF state, since its input voltage
VGSA= 0 V and NMOS transistor (NB) is in ON state since its VGSB=5V. PMOS transistor (PA) is in
ON state, since its VGSA= -5V and PMOS transistor (PB) is in OFF state since its VGSB=0V. So no
supply has the connection with output. Hence output is 0 V.
Case (iii): When A=5 V and B=0 V, then NMOS transistor (NA) is in ON state, since its input voltage
VGSA= +5V and NMOS transistor (NB) is in OFF state since its VGSB=0V. PMOS transistor (PA) is in
OFF state, since its VGSA= 0V and PMOS transistor (PB) is in ON state since its VGSB=-5V. So no
VGSB = 0 V. Both NMOS transistors (NA, NB) are in ON state Since its VGSA and VGSB is large
positive (+5V). So an NMOS transistor presents only a small resistance between Output and ground.
Hence output is 0 Volts.
Fig.4(a): 2-input CMOS NOR gate Fig.4(b),(c): Function table and Logic symbol
of NOR Gate

● Non-inverting Gates:
In CMOS, and in most other logic families, the simplest gates are inverters, and the next simplest
are NAND gates and NOR gates. A logical inversion comes “for free,” and typically it is not possible to
design a non inverting gate with a smaller number of transistors than an inverting one. CMOS non
inverting buffers and AND and OR gates are obtained by connecting an inverter to the output of the
corresponding inverting gate.
CMOS 2-input AND gate:
√ Fig.4(d) shows the function table, logic symbol and circuit diagram for 2-input AND gate.
AND gate is obtained by connecting an inverter to the output of NAND gate.
√ The logic output of AND gate is high (TRUE) only when the inputs are high (TRUE).
Operation:
Case (i): When A=B=0V(LOW), then both NMOS transistors (Q1, Q3) are in OFF state, since its VGSA
= VGSB = 0 V. Both PMOS transistors (Q2, Q4) are in ON state. Since its VGSA and VGSB voltage is
large negative (-5V). So a PMOS transistor presents only a small resistance between VDD and output.
Hence intermediate output VOUT1 is 5V(HIGH). Then it is applied as input to CMOS inverter circuit, so
NMOS transistors(Q5) is in ON state and PMOS transistors (Q6) is in OFF state, Hence the output VOUT
is obtained as 0V(LOW).
Fig.4(d): CMOS 2-input AND gate
Case (ii): When A=B=5V(HIGH), then both PMOS transistors (Q2, Q4) are in OFF state, since its input
voltages VGSA = VGSB = 0 V. Both NMOS transistors (Q1, Q3) are in ON state Since its VGSA and
VGSB is large positive (+5V). So an NMOS transistor presents only a small resistance between Output
and ground. Hence intermediate output VOUT1 is 0V(LOW). Then it is applied as input to CMOS inverter
circuit, so NMOS transistors (Q5) is in OFF state and PMOS transistors (Q6) is in ON state, Hence the
output VOUT is obtained as 5V(HIGH).

Case (iii): When A= 0V(LOW) and B=5V(HIGH), then NMOS transistor (Q1) is in OFF state, since its
input voltage VGSA= 0 V and NMOS transistor (Q3) is in ON state since its VGSB=5V. PMOS transistor
(Q2) is in ON state, since its VGSA= -5V and PMOS transistor (Q4) is in OFF state since its VGSB=0V.
So PMOS transistor Q2 presents only a small resistance between VDD and output. Hence intermediate
output VOUT1 is 5V(HIGH). Then it is applied as input to CMOS inverter circuit, so NMOS
transistors(Q5) is in ON state and PMOS transistors (Q6) is in OFF state, Hence the output VOUT is
obtained as 0V(LOW).
Case (iv): When A=5V(HIGH) and B=0V(LOW), then NMOS transistor (Q1) is in ON state, since its
input voltage VGSA= +5V and NMOS transistor (Q3) is in OFF state since its VGSB=0V. PMOS
transistor (Q2) is in OFF state, since its VGSA= 0V and PMOS transistor (Q4) is in ON state since its
VGSB=-5V. So PMOS transistor Q4 presents only a small resistance between VDD and output. Hence
output is 5V(HIGH). Then it is applied as input to CMOS inverter circuit, so NMOS transistors(Q5) is in
ON state and PMOS transistors (Q6) is in OFF state, Hence the output VOUT is obtained as 0V(LOW).
CMOS 2-input OR gate:
Fig.4(e) shows the logic symbol and circuit diagram for 2-input OR gate. OR gate is obtained by
connecting an inverter to the output of NOR gate. Fig.4(f) shows the function table of OR gate.
The logic output of OR gate is LOW (False) only when the inputs are LOW (False).
Fig.4(e): Circuit Diagram of CMOS 2-input OR gate

Fig.4(f): Function table of CMOS 2-input OR gate
Operation:
Case (i): When A=B=0V(LOW), then both NMOS transistors (Q1, Q3) are in OFF state, since its VGSA
= VGSB = 0 V. Both PMOS transistors (Q2, Q4) are in ON state. Since its VGSA and VGSB voltage is
large negative (-5V). So a PMOS transistor presents only a small resistance between VDD and output.
Hence intermediate output VOUT1 is 5V(HIGH). Then it is applied as input to CMOS inverter circuit, so
NMOS transistors(Q5) is in ON state and PMOS transistors (Q6) is in OFF state, Hence the output VOUT
is obtained as 0V(LOW).
Case (ii): When A=B=5V(HIGH), then both PMOS transistors (Q2, Q4) are in OFF state, since its input
voltages VGSA = VGSB = 0 V. Both NMOS transistors (Q1, Q3) are in ON state Since its VGSA and
VGSB is large positive (+5V). So an NMOS transistor presents only a small resistance between Output
and ground. Hence intermediate output VOUT1 is 0V(LOW). Then it is applied as input to CMOS inverter
circuit, so NMOS transistors (Q5) is in OFF state and PMOS transistors (Q6) is in ON state, Hence the
output VOUT is obtained as 5V(HIGH).
Case (iii): When A= 0V(LOW) and B=5V(HIGH), then NMOS transistor (Q1) is in OFF state, since its
input voltage VGSA= 0 V and NMOS transistor (Q3) is in ON state since its VGSB=5V. PMOS transistor
(Q2) is in ON state, since its VGSA= -5V and PMOS transistor (Q4) is in OFF state since its VGSB=0V.
So PMOS transistor Q2 presents only a small resistance between VDD and output. Hence intermediate
output VOUT1 is 0V(LOW). Then it is applied as input to CMOS inverter circuit, so NMOS transistors
(Q5) is in OFF state and PMOS transistors (Q6) is in ON state, Hence the output VOUT is obtained as
5V(HIGH).
Case (iv): When A=5V(HIGH) and B=0V(LOW), then NMOS transistor (Q1) is in ON state, since its
input voltage VGSA= +5V and NMOS transistor (Q3) is in OFF state since its VGSB=0V. PMOS
transistor (Q2) is in OFF state, since its VGSA= 0V and PMOS transistor (Q4) is in ON state since its
VGSB=-5V. So PMOS transistor Q4 presents only a small resistance between VDD and output. Hence
output is 0V(LOW). Then it is applied as input to CMOS inverter circuit, so NMOS transistors (Q5) is in
OFF state and PMOS transistors (Q6) is in ON state, Hence the output VOUT is obtained as 5V(HIGH).
Inputs Transistors Output
A B Q1 Q2 Q3 Q4 Q5 Q6 VOUT
L L off on off on on off L (0V)
L H off on on off off on H (5V)
H L on off off on off on H (5V)
H H on off on off off on H (5V)

CMOS AND-OR-INVERT Logic (AOI):
Fig.5(a) shows the logic diagram of two-wide, two input AND-OR-INVERT (AOI) gate
i.e. four input AND-OR-INVERT gate using 2-input AND and NOR gates. CMOS circuits can
implement two levels of logic gates with just a single level of transistor. The implementation of two
wide two input AND-OR-INVERT gate and its function table is shown in fig.5(b) and 5(c).
Fig.5(a): AOI Logic gate implementation (or) Logic diagram for AOI gate
√ CMOS circuits can perform two levels of logic with just a single “level” of transistors.
√ CMOS AND-OR-INVERT (AOI) gate is implemented by taking a logic function
√ In the above function AB forms a 2 input AND gate and CD also forms another 2 input AND gate.
Both are combined with OR logic and entire function contains Invert or complement operation.
√ Finally they form AND-OR-INVERT Logic.
√ Any given Boolean expression should be expressed in terms of Universal gate (NAND/NOR) format
by using De-Morgan’s principle.
√ All NMOS transistors in NAND gate implementation should be connected in SERIES and PMOS
transistors are in PARALLEL connection.
√ All NMOS transistors in NOR gate implementation should be connected in PARALLEL and PMOS
transistors are in SERIES connection.
√ When all the inputs A=B=C=D=0V (LOW) then all the NMOS transistors (Q1,Q3,Q5,Q7) are in
OFF state, since its VGS=0V and all the PMOS transistors (Q2,Q4,Q6,Q8) are in ON state, since its
VGS=-5V. So all the PMOS transistors presents only a small resistance between VDD and output.
Hence output is 5V(HIGH).
√ When all the inputs A=B=C=D=5V (HIGH) then all the PMOS transistors (Q2,Q4,Q6,Q8) are in
OFF state, since its VGS=0V and all the NMOS transistors (Q1,Q3,Q5,Q7) are in ON state, since its
VGS=+5V . So all the NMOS transistors presents only a small resistance between output and
Ground. Hence output is 0V(LOW).

(or)
Fig.5(b): CMOS AND-OR-INVERT gate
Fig.5(c): Function table of AOI gate

CMOS OR-AND-INVERT Logic (OAI):-
Fig.6(a) shows the logic diagram of two-wide, two input OR-AND-INVERT (AOI) gate
i.e. four input OR- AND-INVERT gate using 2-input AND and NOR gates. CMOS circuits can
implement two levels of logic gates with just a single level of transistor. The implementation of two
wide two input OR-AND-INVERT gate and its function table is shown in fig.6(b) and 6(c).
Fig.6(a): OAI Logic gate implementation (or) Logic diagram for OAI gate
(or)
Fig.6(b): CMOS OR- AND-INVERT gate

√ CMOS OR-AND-INVERT(OAI) gate is implemented by taking a logic function
√ In the above function A+B forms a 2 input OR gate and C+D also forms another 2 input OR gate.
Both are combined with AND logic and entire function contains Invert or complement operation.
√ Finally they form OR- AND-INVERT Logic.
Fig.6(c): Function table of OAI gate
√ All NMOS transistors in NOR gate implementation should be connected in PARALLEL and
PMOS transistors are in SERIES connection.
OFF state, since its VGS=0V and all the PMOS transistors (Q2,Q4,Q6,Q8) are in ON state, since
its VGS=-5V. So all the PMOS transistors presents only a small resistance between VDD and
output. Hence output is 5V(HIGH).
OFF state, since its VGS=0V and all the NMOS transistors (Q1,Q3,Q5,Q7) are in ON state, since

its VGS=+5V . So all the NMOS transistors presents only a small resistance between output and
Designa CMOS digital circuit that realizes the Booleanexpression?
Designa CMOS digital circuit that realizes the booleanexpression?
Sol:- Step-1: Design the PDN by first rewriting the expression as
In other words, write the complemented output in terms of un complemented input. We must first
complement this equation and then apply demorgan’s theorem.
Step-2: Design the PUN by writing the expression as

In other words, write the un complemented output in terms of complemented inputs. Again using
Demorgan’s theorem.
Thus, we can realize the CMOS logic circuit as,
Designthe CMOS logic circuit that has a functional behavior?
Sol:- Step-1: Design the PDN by first rewriting the expression as
In other words, write the complemented output in terms of un complemented input. We must first
complement this equation and then apply demorgan’s theorem.
Step-2: Design the PUN by writing the expression as

In other words, write the un-complemented output in terms of complemented inputs. Again using
Demorgan’s theorem.
Schottkytransistorand its need in TTL family:-
√ When the input of a saturated transistor is changed, the output does not change immediately; it takes
extra time, called storage time, to come out of saturation.
√ The storage time presents because the excess charge carriers in the base region provides Forward
biasing which may provide deep saturation to the transistor.
√ In fact, storage time accounts for a significant portion of the propagation delay in the original TTL
logic family.
√ The storage time can be reduced by removing excess charge carriers in the base region to prevent deep
saturation to the transistor before transistor is switched from ON to OFF state.
√ This is achieved by placing a Schottky diode between the base and collector of each transistor.
√ Schottky diodes have little capacitance, fast recovery time, hence it switched without storage delay
time.
√ Transistors, which do not saturate, are called Schottky clamped transistor or Schottky transistor.

Figure 4(b)Schottky Transistor
2 input NAND gate using TTL logic:-
TTL Logic:
LOW 0–0.8 volts
HIGH 2.0–5.0 volts
√ The NAND function is obtained by connecting AND gate with an inverting circuit.
√ The circuit’s operation is understood by dividing it into the three parts as
1) Diode AND gate and input protection.
2) Phase splitter.
3) Output stage.
Diode AND gate and input protection: Diodes D1, D2 and resistor R1 form a diode AND gate, Clamp
diodes D5 and D6 do nothing in normal operation, but limit undesirable large negative voltages may occur
on HIGH-to-LOW input transitions as a result of transmission-line effects. They are called as protective
diodes.
Phase splitter: Transistor Q2 and the surrounding R2, R3 and R4 resistors form a phase splitter that
controls the output stage. Depending on whether the diode AND gate produces a “low” or a “high” voltage
at VA, Q2 is either cut off or turned on. Diode AND gate and input protection and Phase splitter form
NAND gate.
Output stage: The output stage has two transistors, Q4 and Q5, only one of which is ON at any time. The
TTL output stage is sometimes called a totem-pole or push-pull output which is similar to the p-channel
and n-channel transistors in CMOS. Q4 and Q5 transistors provide active pull-up and pull-down to the
HIGH and LOW states, respectively. Except Q4 remaining all transistors are Schottky clamped transistors
because it can’t saturate. Q3 and Q4 connected in Darlington pair which may provide shorter output rise

time when switching from OFF to ON. Q6 regulates current flow into base of Q5 and helps to it in turning
to OFF.
Figure 4(c): TTL-2 input NAND gate
Table 3: Functional table of TTL-2 input NAND gate.
2 input NOR gate using TTL logic:-
√ The NOR function is obtained by connecting OR gate with an inverting circuit.
Inputs
VA
Transistors
VZ
Output
A B Q2 Q3 Q4 Q5 Q6 VOUT
L L ≤ 1.05 off on on off off 2.7 HIGH (5V)
L H ≤ 1.05 off on on off off 2.7 HIGH (5V)
H L ≤ 1.05 off on on off off 2.7 HIGH (5V)
H H 1.2 on off off on on ≤ 0.35 LOW (0V)

1) Diode inputs and input protection.
2) OR function and Phase splitter.
3) Output stage.
√ If either input X or Y is HIGH, the corresponding phase-splitter transistor Q2X or Q2Y is turned on,
which turns off Q3 and Q4 while turning on Q5 and Q6, and the output is LOW.
√ If both inputs are LOW, then both phase-splitter transistors are off, and the output is forced HIGH.
√ The speed, input, and output characteristics of a TTL NOR gate are comparable to those of a TTL
NAND.
√ The TTL NOR gate’s input circuits, phase splitter, and output stage are almost identical to those of an
TTL NAND gate. The difference is that TTL NAND gate uses diodes to perform the AND function,
while TTL NOR gate uses parallel transistors in the phase splitter to perform the OR function.
√ An n-input NOR gate uses more transistors and resistors and is thus more expensive in silicon area than
an n-input NAND. Internal leakage current limits the number of Q2 transistors that can be placed in
parallel, so NOR gates have poor fan-in. As a result, NOR gates are less commonly used than NAND
gates in TTL designs.
√ The most “natural” TTL gates are inverting gates like NAND and NOR. Non-inverting TTL gates
include an extra inverting stage, typically between the input stage and the phase splitter. As a result,
non-inverting TTL gates are typically larger and slower than the inverting gates.
Table 4: Functional table of TTL-2 input NOR gate.
A B VAX Q2X VAY Q2Y Q3 Q4 Q5 Q6 Vz VOUT
L L ≤ 1.05 off ≤ 1.05 off on on off off ≥ 2.7 HIGH (5V)
L H ≤ 1.05 off 1.2 on off off on on ≤ 0.35 LOW (0V)
H L 1.2 on ≤ 1.05 off off off on on ≤ 0.35 LOW (0V)
H H 1.2 on 1.2 on off off on on ≤ 0.35 LOW (0V)

Figure 6: TTL-2 Input NOR gate
sinking and sourcing currents in TTL family:-
When output of TTL NAND gate circuit is connected to input of another TTL NAND gate circuit then
Case (i): Sinking Current
√ When TTL input is driven LOW by the output of another TTL circuit, then the transistor Q5 is in
ON state and it provides the path to ground, for the current flowing out of the Diode B.
√ When current flows into a TTL output in LOW State, then the output is said to be SINKING
CURRENT.

Figure 7(a): TTL output Driving a TTL input LOW (Sinking Current)
Case (ii): Sourcing Current
√ When TTL input is driven HIGH by the output of another TTL circuit then the transistor Q4 is in
ON state then a small amount of leakage current flows through the reverse biased diodes A.
√ When current flows out of a TTL output in HIGH State, then the output is called SOURCING
CURRENT.
Figure 7(b): TTL output Driving a TTL input HIGH (Sourcing Current)

CMOS/TTLInterfacing:-
Interfacing means connecting outputs of one circuit to inputs of another circuit that may have
different electrical characteristics. If two circuits that are going to interface have different Electrical
characteristics,then direct connection can’t be made. In such cases Driver and Load circuits are connected
through interface circuit. Its function is to take the driver output signal and condition it so it is compatible
with the requirements of load.
One must consider the following important points while interfacing two circuits or systems.
√ Driver output must satisfy the voltage and current requirements of the load circuit.
√ If both driver and load require different power supplies, then outputs of both circuits must swing
between its specified voltage ranges.
The interfacing may done in between two different logic families or within the same logic families.
Interfacing in between CMOS and TTL logic families is achieved in ways as
(a) TTL Driving CMOS circuits.
(b) CMOS driving TTL circuits.
(a) TTL Driving CMOS circuit:
In this, TTL circuit acts as a driver circuit and CMOS circuit acts as Load circuit. The two circuits
are from different families with different electrical characteristics. Therefore, we must check that the
driving device can meet the current and voltage requirements of the load device.
TTL (74LS) CMOS (74HC/HCT)
VOHmin = 2.7V
VOLmax = 0.5V
IOHmax = 0.4mA
IOLmax = 8mA
VIHmin = 3.5V
VILmax = 1.5V
IIHmax = 1µA
IILmax = 1µA
Table 7(a) Voltage and Current comparison of CMOS and TTL families
● From the above table IIH(max), IIL(max) values for CMOS are extremely low as compared with
IOH(max), IOL(max) values of TTL, So here have the Compatibility means TTL has no problem meeting
the CMOS current requirements .

● But VOH(min) for TTL less than to VIH(min) for CMOS, here voltage requirements are not satisfied. In
such cases compatibility can be done by connecting pull-up resistor RPU at the output of TTL as
shown in fig.10(a).
● RPU raises TTL Output to Approximately 5V in ‘HIGH’ state.
Figure 10(a): Interfacing of TTL NAND gate with CMOS NAND gate
TTL Driving HIGH Voltage CMOS:
● Sometimes we face a difficult situation that CMOS circuit operated with VDD > 5v. Outputs of
many TTL devices can’t operate at more than 5V. In such cases some alternative arrangements are
made. They are:
(1) Use of Open collector buffer as Interface:
(2) Level Translator: It shifts the low voltage output from TTL into High voltage input for CMOS
(1) Use of Open collector buffer as Interface: When the TTL output cannot be pulled up to VDD, one
can use open collector buffer as an interface between TTL output and CMOS operating at VDD > 5V.
Figure 11: (a) Use of Open collector buffer as Interface
(2) Level Translator: The second alternative is to use level translator circuit such as the 40104. This is
a CMOS chip that is designed to take a low-voltage input from TTL and translate it to high voltage
output for CMOS as shown in fig.11(b)

Figure 11: (a) Use of Level translator as Interface
(b) CMOS Driving TTL circuit:
In this, CMOS circuit acts as a driver circuit and TTL circuit acts as Load circuit. The two circuits
are from different families with different electrical characteristics. Therefore, we must check that the
driving device can meet the current and voltage requirements of the load device.
TTL (74) CMOS (4000B)
VOHmin = 4.95V
VOLmax = 0.1V (0.05V)
IOHmax = 0.4mA
IOLmax = 0.4mA
VIHmin = 2V
VILmax = 0.8V
IIHmax = 40µA
IILmax = 1.6µA
Table 7(a) Voltage and Current comparison of CMOS and TTL families
CMOS driving TTL in the HIGH state: Above table indicates that CMOS outputs can easily supply
voltage (VOH) to satisfy the TTL input requirement in HIGH state (VIH) and also CMOS outputs can
supply enough current (IOH) to meet the TTL input current requirements (IIH). Thus no special
consideration is required for CMOS driving TTL in the HIGH state.
CMOS driving TTL in the LOW state: The parameters in the above table shows that CMOS output voltage
(VOL) satisfies TTL input requirement in the LOW state (VIL). However, the current requirements in the
LOW state are not satisfied. The TTL input has a relatively high input current in the LOW state (1.6mA)
and CMOS output current at LOW state (IOL) is not sufficient to drive even one input of the TTL. In such
situations some type of interface circuit is needed between the CMOS and TTL devices.
As shown in fig.11(c), the CMOS 4050B non-inverting buffer is used as an interfacing circuit.It has an
output current rating of IOL(max) =3mA which satisfies the TTL input current requirement.

Figure 11: (c) CMOS Driving TTL in LOW State
High Voltage CMOS driving TTL: Some IC Manufacturers have provided 74LS TTL devices
operating at 15V, but many of TTLs input can’t tolerate >7V. For such cases Voltage level Translators are
used.
Figure 11: (d) High voltage CMOS Driving TTL
Figure 10: (a) Output and input levels for interfacing TTL and CMOS families.
(b) TTL/CMOS Transfer Characteristics.

Low voltage CMOS Logic and Interfacing:-
√ Interfacing means connecting outputs of one circuit to inputs of another circuit that may have different
electrical characteristics.
√ Two important factors have led the IC industry to move towards lower power supply voltages in
CMOS devices.
● Lower power supply voltage reduces dynamic power dissipation more than proportionally.
● Lower power supply voltages allow to have oxide insulation between CMOS transistors gate and
its source and drain more thinner to get transistor geometries. In other words, device size is
reduced.
√ As a result, JEDEC (Joint Electronic Device Engineering Council) is an IC industry standards group,
selected 3.3V ± 0.3V, 2.5V ± 0.2V, and 1.8V± 0.15V as the next “standard” logic power-supply
voltages.
√ JEDEC standards specify the input and output logic voltage levels for devices operating with these
power-supply voltages.
√ To maintain the compatibility with higher power supply voltage devices, two basic approaches are
used:
● In this approach, the devices operate and produce outputs at the lower voltage but can also
tolerate inputs at the higher voltage. This approach is used in 3.3 V CMOS families to operate
with 5 V CMOS and TTL families.
● This approach is suitable for larger devices. In this approach, the devices are provided with
two power supply voltages. A low voltage, such as 2.5V is supplied to operate the chip’s
internal gates or Core logic. A higher voltage, such as 3.3V is supplied to operate the external
input and output circuits or Pad ring. Special buffer circuits are used internally to translate
safely and quickly between core logic and pad ring logic voltages.
√ HC and VHC families are 5V CMOS families. TTL compatible CMOS families such as HCT, VHCT
and FCT shift the voltage levels downward for compatibility with TTL. This is illustrated in fig.12(b).
√ As shown in fig.12(b) and 12(c), LVTTL levels match with TTL levels. Thus LVTTL can drive a TTL
input with no problem. Similarly, a TTL output can drive an LVTTL input with no problem.
√ To interface 2.5V and 1.8V CMOS logic families with 3.3V CMOS or other higher voltage logic
families, we need level translator or level shifter. It is a device which is powered by both supply
voltages and which internally boosts the lower logic levels to the higher ones.

Figure 12: Comparisons of logic levels (a) 5V CMOS Families; (b) 5V TTL Families; (c) 3.3V LVTTL
Families; (d) 2.5V CMOS Families; (e) 1.8V CMOS Families
Emitter Coupled Logic (ECL) or CML:-
√ TTL Family operates the Transistor in deep saturation mode, results the limitation of Switching speed
by Storage delay time.
√ To overcome this limitation, another circuit structure is used called Current Mode Logic. This logic
family also called as Emitter Coupled Logic.
ECL Characteristics:
√ It is fastest logic family because Propagation delay is short.
√ For 10k, 100k families it is 1ns, for latest ECL it is 500ps or 0.5ns
√ Preventing Transistor from deep saturation by keeping logic levels close to each other.
√ Eliminates the storage delays & increases the Switching Speed.
√ Noise margin is reduced; it is difficult to achieve good noise immunity.
√ Power consumption is more because transistors are not in complete saturation.
√ Switching Transients are less, because power supply current is more stable than TTL, CMOS.

Basic ECL Circuit:
√ The basic idea of current-mode logic is illustrated by the inverter/buffer circuit in Figure 4.35. This
circuit has both an inverting output (OUT1) and a non-inverting output (OUT2).
√ This basic ECL circuit contains two output terminals, so it may provide Inverting and Non-Inverting
operations in the same circuit.
√ So Basic ECL circuit gives Inverter and Buffer operations in the same circuit.
Figure 13(a): Basic ECL inverter/buffer with input HIGH
Figure 13(b): Basic ECL inverter/buffer with input LOW

√ Two transistors are connected as a differential amplifier with a common emitter resistor. The supply
voltages for this example are VCC = 5V, VBB = 4V, and VEE = 0V, and the input LOW and HIGH
levels are defined to be 3.6 and 4.4 V. This circuit actually produces output LOW and HIGH levels
that are 0.6 V higher (4.2 and 5.0 V), but this is corrected in real ECL circuits.
√ When VIN is HIGH, as shown in the figure, transistor Q1 is ON, but not saturated, and transistor Q2
is OFF. Thus, VOUT2 is pulled to 5V (HIGH) through R2, and it can be shown that the voltage drop
across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW).
√ When VIN is LOW, as shown in Figure, transistor Q2 is ON, but not saturated, and transistor Q1 is
OFF. Thus, VOUT1 is pulled to 5V through R1, and it can be shown that VOUT2 is about 4.2 V.
√ The outputs of this inverter are called differential outputs because they are always complementary,
and it is possible to determine the output state by looking at the difference between the output voltages
(VOUT1 - VOUT2) rather than their absolute values.
√ That is, the output is 1 if (VOUT1 - VOUT2) > 0, and it is 0 if (VOUT2 – VOUT1) > 0. It is possible
to build input circuits with two wires per logical input that define the logical signal value in this way;
these are called differential inputs
Table 8: Functional table of Basic ECL gate.
 ECL 100K Family:
Members of the ECL 100K family have 6-digit part numbers of the form “100xxx” (e.g., 100101,
100117, 100170), but in general their functions are different from those of 10K parts with similar numbers.
The 100K family has the following major differences from the 10K family:
Comparison of ECL 10k family with 100K family

Positive Emitter coupled Logic (PECL):
PECL uses a standard +5.2V power supply. Like ECL logic levels, PECL levels are referenced to
VCC, so the PECL HIGH level is about VCC − 0.9 V, and LOW is about VCC − 1.7 V, or about 4.1 V
and 3.3 V with a nominal 5V VCC. Thus, PECL designs require particularly close attention to power-
distribution issues, to prevent noise on VCC from corrupting the logic levels transmitted and received by
PECL devices. PECL is used in High Speed and Clock distribution circuits.
Objective Questions and Answers
S.
No.
Objective Questions
1.
Voltage level representing logic-0 in CMOS logic is
a) 0-1.5V b) 3.5-5V c) 0-0.8V d) 2.0-5.0V
2.
The current that flows from the power supply out of the device o/p and through the load to ground is
a) sourcing current b) Sinking current c) conventional current d) electron current
3.
The basic gate in TTL is _________
a) AND b) OR c) NAND d) NOR
4. When Vin of 0.0V is applied to CMOS circuit, PMOS is______and NMOS is _______
a) off, on b) off, off c) on, off d) on, on
5. Output loading for HC series CMOS with a 5V supply , find maximum low state o/p current(mA)
a) 0.1 b) 0.02 c) -0.02 d) 4.4
6.
Fan out of standard TTL gate is _______
a) 1 b) 2 c) 15 d)10
7. The maximum number of inputs that a gate can handle is____
a) Fan in b) Fan out c) Transition time d) Propagation delay
8. The range of VIH in CMOS is________
a) < 1.5V b) <2.0V c) >3.5v d) <3.5V
9. In TWO i/p CMOS NAND gate,no. of NMOS transistor used are________________
a) 1 b)2 c)3 d)4
10. The expression for dynamic power dissipation in CMOS circuits is__________________
a) P=cvf b) P= (cvf)/2 c) P=cv2
f d) none of the above
11. The range of VIL in CMOS is
a) >1.5v b) <1.5v c) >3.5v d) <3.5v
12. The amount of time taken by the output to transfer from one state to another state is___
a) Propagation delay b) Transition time c) Power consumption d) none
13. Basically the single CE transistor acts as _______ logic circuit
a) Multiplexer b) inverter c) differentiator d) decoder
14. Which of the following family consumes more power --------
a) 74LS b) 74AS c) 74ALS d) 74S
15.
ECL belongs to_______ family
a) bipolar-saturated b) bipolar non saturated
c) unipolar saturated d) unipolar non-saturated

16. Fastest logic family from the following
a) TTL b) Schottky TTL c) RTL d) DTL
17. Which of the following logic families exhibit lowest power dissipation per gate_____
a) TTL b) ECL c) CMOS d) 8nsec-ECL
18. Current mode logic (CML) is the same as _______
a) TTL b) ECL c) CMOS d) I² L
19. The ECL can be used to switch frequencies as high as_____
a) 1 MHz b) 100 MHz c) 500 MHz d) 1GHz
20. 7400 series devices can be safely operated in the temperature range_______
a) 0 to 20ºc b) 0 to 30ºc c) 0 to 70ºc d) 0 to 100ºc
21. Noise margin for HIGH level (logic-1) is__________________
a) VOHMIN-VOLMA X b) VOHMIN-VIHMIN c) VILMAX-VOLMAX d) VIHMIN-VOHMIN
22. Noise margin for LOW level (logic-0) is__________________
a) VOHMIN-VOLMA X b) VOHMIN-VIHMIN c) VILMAX-VOLMAX d) VIHMIN-VOHMIN
23. Dc noise margin of 74LS-TTL family in High State is________
a) 2.0v b) 2.7v c) 0.7v d) 0.3v
24. The overall fan-out of low state and high state fan-out in LS-TTL is ______________
a) 5 b) 10 c) 20 d) 25
25.
The fan out of a logic gate is __________
a) the no. of subsequent ckts which the gate can drive
b) The no.of i/ps divided by the number of o/ps
c) The no.of connections to the package
d) None ofthe above

2 Marks Questions and Answers
UNIT-1
1. Define binary logic?
Ans:-Binary logic consists of binary variables and logical operations. The variables are designated by the
alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0. There
are three basic logic operations: AND, OR, and NOT.
2. What are the basic digital logic gates?
Ans:-The three basic logic gates are
AND gate
OR gate
NOT gate
3. What is a Logic gate?
Ans:-Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that
is able to operate on a number of binary inputs in order to perform a particular logical function.
4.Give the classification of logic families
Ans:- Bipolar Unipolar
Saturated Non Saturated PMOS
NMOS
CMOS
RTL Schottky TTL
ECL DTL
I I L
TTL
5. Which gates are called as the universal gates? What are its advantages?
Ans:-The NAND and NOR gates are called as the universal gates. These gates are used to perform any
type of logic application.
6.Classify the logic family by operation?
Ans:-The Bipolar logic family is classified into
Saturated logic
Unsaturated logic.
The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family.
The Schottky TTL, and ECL logic comes under the unsaturated logic family.
7.State the classifications of FET devices.
Ans:-FET is classified as
a. Junction Field Effect Transistor (JFET)
b. Metal oxide semiconductor family (MOS).
8.Mention the classification of saturated bipolar logic families.
Ans:-The bipolar logic family is classified as follows:
RTL- Resistor Transistor Logic
DTL- Diode Transistor logic
I2L- Integrated Injection Logic
TTL- Transistor Transistor Logic
ECL- Emitter Coupled Logic

9. Mention the important characteristics of digital IC’s?
Ans:- Fan out
Power dissipation
Propagation Delay
Noise Margin
Fan In
Operating temperature
Power supply requirements
10. Define Fan-out?
Ans:-Fan out specifies the number of inputs that the output of the gate can drive with out exceeding the
worst case specifications.
11. Define power dissipation?
Ans:-Power dissipation is measure of power consumed by the gate when fully driven by all its inputs.
12. What is propagation delay?
Ans:-Propagation delay is the average transition delay time for the signal to propagate from input to output
when the signals change in value. It is expressed in ns.
13. Define noise margin?
Ans:-It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an
undesirable change in the circuit output. It is expressed in volts.
14. Define fan in?
Ans:-Fan in is the number of inputs connected to the gate without any degradation in the voltage level.
15. What is Operating temperature?
Ans:-All the gates or semiconductor devices are temperature sensitive in nature. The temperature in which
the performance of the IC is effective is called as operating temperature. Operating temperature of the IC
vary from 00 C to 700 c.
16. What are the types of TTL logic?
Ans:-1. Open collector output
2. Totem-Pole Output
3. Tri-state output.
17. What is depletion mode operation MOS?
Ans:-If the channel is initially doped lightly with p-type impurity a conducting channel exists at zero gate
voltage and the device is said to operate in depletion mode.
18. What is enhancement mode operation of MOS?
Ans:-If the region beneath the gate is left initially uncharged the gate field must induce a channel before
current can flow. Thus the gate voltage enhances the channel current and such a device is said to operate in
the enhancement mode.
19. Mention the characteristics of MOS transistor?
Ans:- 1. The n- channel MOS conducts when its gate- to- source voltage is positive.
2. The p- channel MOS conducts when its gate- to- source voltage is negative
3. Either type of device is turned of if its gate- to- source voltage is zero.

20. List the different versions of TTL?
Ans:- 1.TTL (Std.TTL)
2.LTTL (Low Power TTL)
3.HTTL (High Speed TTL)
4.STTL (Schottky TTL)
5.LSTTL (Low power Schottky TTL)
21.Explain briefly why CMOS cannot drive the TTL directly. .(Nov/Dec 2011)
Ans:CMOS takes a lot less power and is therefore suitable for battery applications, but generally speaking
can't run as fast. TTL devices can drive more power into a load.CMOS chips can be damaged by static
electricity.
22.Compare TTL, CMOS and ECL logic families with respect to power dissipation and propagation
delay.
23.List the salient features of ECL family. .(Nov/Dec 2012)
Ans: 1. It is a nonsaturating logic. That is, the transistors in this logic are always operated in the active
region of their output characteristics. They are never driven to either cut-off or saturation, whichmeans
that logic LOW and HIGH states correspond to different states of conduction of variousbipolar transistors.
2. The logic swing, that is, the difference in the voltage levels corresponding to logic LOW and
HIGHstates, is kept small (typically 0.85 V), with the result that the output capacitance needs to
becharged and discharged by a relatively much smaller voltage differential.
3.The circuit currents are relatively high and the output impedance is low, with the result that theoutput
capacitance can be charged and discharged quickly.
24.Which logic family performs better in a high-noise environment : CMOS or TTL? Why?
(May/June 2013)
Ans: CMOS performs better in a high-noise environment because CMOS has extremely low power
consumption and high noise immunity. It can operate in devices operated in noisy environments, such as
industrial plants.
25.What is the main advantage of ECL over other IC technologies? In what type of application
should ECL not be considered? (May/June 2013)
Ans: ECL's major disadvantage is that each gate continuously draws current, which means it requires (and
dissipates) significantly more power than those of other logic families, especially when quiescent. ECL has

a poor speed-power product, does not provide a high level of integration, has fast edge rates requiring
design for transmission-line effects in most applications
26.Which is faster TTL or ECL? Which requires more power to operate?(May/June 2014)
Ans: ECL is fastest among because the transistors are used in difference amplifier configuration, in which
they are never driven into saturation and thereby the storage time is eliminated. ECL's major disadvantage
is that each gate continuously draws current, which means it requires (and dissipates) significantly more
power than those of other logic families, especially when quiescent. ECL has a poor speed-power product,
does not provide a high level of integration, has fast edge rates requiring design for transmission-line
effects in most applications
27. State advantages and disadvantages of TTL
Ans: Adv: Easily compatible with other ICs, Low output impedance
Disadv: Wired output capability is possible only with tristate and open collector types
Special circuits in Circuit layout and system design are required.
28. State the advantages and disadvantages of a totem-pole output.
Ans: Advantage: Operating speed is high.
Disadvantage: Output of two gates cannot be tied together to form wired-logic connection for the
purpose of forming a common-bus system.
29. How schottky transistors are formed and state its use?
Ans: A schottky diode is formed by the combination of metal and semiconductor. The presence of schottky
diode between the base and the collector prevents the transistor from going into saturation. The resulting
transistor is called as schottky transistor. The use of schottky transistor in TTL decreases the propagation
delay without a sacrifice of power dissipation.
30.Why NAND and NOR gates are preferred over AND and OR logic gates(May/June 2014)
Ans: They are called universal gates as they can be used to design all other logic circuit elements like
XOR,NOR,etc. also these gates can be realized through easy combination of diodes thus making them easy
to use base elements in any chip designing project. With a combination NAND and NOR gates alone, it's
possible to create all other logic gates like AND, OR, XOR etc and you can design any logic circuit.

Descriptive Questions and Answers (University Question Papers)
1) a) Draw and Explain Implementation of 2 Input NOR gate using CMOS logic?
2-Input CMOS NOR GATE:-
√ NOR gate is one of the basic logic gates to perform the digital operation on the input signals.
√ It is the combination of OR Gate followed by NOT gate i.e. it is the opposite operation of OR gate
where
√ the Logic NOR gate is complementary of OR gate.
√ The logic output of NOR gate is HIGH (True) only when the inputs are LOW (False).
√ To implementation 2 Input NOR gate using CMOS logic we require 2 pull-up PMOS and 2 pull-
down
√ NMOS transistors.
√ Fig.(4) shows the function table, logic symbol and circuit diagram for CMOS 2-input NOR gate.
It consists of two P-channel MOSFETs Q2 and Q4, connected in series and two N-channel
MOSFETs, Q1 and Q3 connected in parallel.
Working operation:
Case (i): When A=B=0 V, then both NMOS transistors are in OFF state, since its VGSA = VGSB = 0 V.
Both PMOS transistors (PA, PB) are in ON state. Since its VGSA and VGSB voltage is large negative (-
Case (ii): When A=0 V and B=5 V, then NMOS transistor (NA) is in OFF state, since its input voltage
VGSA= 0 V and NMOS transistor (NB) is in ON state since its VGSB=5V. PMOS transistor (PA) is in
ON state, since its VGSA= -5V and PMOS transistor (PB) is in OFF state since its VGSB=0V. So no
Case (iii): When A=5 V and B=0 V, then NMOS transistor (NA) is in ON state, since its input voltage
VGSA= +5V and NMOS transistor (NB) is in OFF state since its VGSB=0V. PMOS transistor (PA) is in
OFF state, since its VGSA= 0V and PMOS transistor (PB) is in ON state since its VGSB=-5V. So no
VGSB = 0 V. Both NMOS transistors (NA, NB) are in ON state Since its VGSA and VGSB is large
positive (+5V). So an NMOS transistor presents only a small resistance between Output and ground.
Hence output is 0 Volts.

Fig.4(a): 2-input CMOS NOR gate Fig.4(b),(c): Function table and Logic symbol
of NOR Gate
1) b) Designa 4-input CMOS AND-OR-INVERT gate. Explain the circuit with the help of
logic diagram and function table?
Fig.5(a) shows the logic diagram of two-wide, two input AND-OR-INVERT (AOI) gate i.e. four input
AND-OR-INVERT gate using 2-input AND and NOR gates. CMOS circuits can implement two levels
of logic gates with just a single level of transistor. The implementation of two wide two input AND-OR-
INVERT gate and its function table is shown in fig.5(b) and 5(c).
Fig.5(a): AOI Logic gate implementation (or) Logic diagram for AOI gate
√ CMOS AND-OR-INVERT (AOI) gate is implemented by taking a logic function
√ In the above function AB forms a 2 input AND gate and CD also forms another 2 input AND gate.
Both are combined with OR logic and entire function contains Invert or complement operation.
√ Finally they form AND-OR-INVERT Logic.

√ Any given Boolean expression should be expressed in terms of Universal gate (NAND/NOR) format
by using De-Morgan’s principle.
√ All NMOS transistors in NOR gate implementation should be connected in PARALLEL and PMOS
transistors are in SERIES connection.
OFF state, since its VGS=0V and all the PMOS transistors (Q2,Q4,Q6,Q8) are in ON state, since its
VGS=-5V. So all the PMOS transistors presents only a small resistance between VDD and output.
Hence output is 5V(HIGH).
OFF state, since its VGS=0V and all the NMOS transistors (Q1,Q3,Q5,Q7) are in ON state, since its
VGS=+5V . So all the NMOS transistors presents only a small resistance between output and
(or)
Fig.5(b): CMOS AND-OR-INVERT gate

Fig.5(c): Function table of AOI gate
2. a) Explain the principle of a Emitter-Coupled Logic (ECL/CML) through Basic ECL
inverter/buffer circuit with input HIGH and LOW. (R13 Reg Dec 2015)
√ TTL Family operates the Transistor in deep saturation mode, results the limitation of Switching speed
by Storage delay time.
√ To overcome this limitation, another circuit structure is used called Current Mode Logic. This logic
family also called as Emitter Coupled Logic.
ECL Characteristics:
√ It is fastest logic family because Propagation delay is short.
√ For 10k, 100k families it is 1ns, for latest ECL it is 500ps.
√ Preventing Transistor from deep saturation by keeping logic levels close to each other.
√ Eliminates the storage delays & increases the Switching Speed.
√ Noise margin is reduced; it is difficult to achieve good noise immunity.
√ Power consumption is more because transistors are not in complete saturation.
√ Switching Transients are less, because power supply current is more stable than TTL, CMOS.
Basic ECL Circuit:
√ The basic idea of current-mode logic is illustrated by the inverter/buffer circuit in Figure 4.35. This
circuit has both an inverting output (OUT1) and a non-inverting output (OUT2).

√ This basic ECL circuit contains two output terminals, so it may provide Inverting and Non-Inverting
operations in the same circuit.
√ So Basic ECL circuit gives Inverter and Buffer operations in the same circuit.
Figure 13(a): Basic ECL inverter/buffer with input HIGH
Figure 13(b): Basic ECL inverter/buffer with input LOW
√ Two transistors are connected as a differential amplifier with a common emitter resistor. The supply
voltages for this example are VCC = 5V, VBB = 4V, and VEE = 0V, and the input LOW and HIGH
levels are defined to be 3.6 and 4.4 V. This circuit actually produces output LOW and HIGH levels
that are 0.6 V higher (4.2 and 5.0 V), but this is corrected in real ECL circuits.

√ When VIN is HIGH, as shown in the figure, transistor Q1 is ON, but not saturated, and transistor Q2
is OFF. Thus, VOUT2 is pulled to 5V (HIGH) through R2, and it can be shown that the voltage drop
across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW).
√ When VIN is LOW, as shown in Figure, transistor Q2 is ON, but not saturated, and transistor Q1 is
OFF. Thus, VOUT1 is pulled to 5V through R1, and it can be shown that VOUT2 is about 4.2 V.
√ The outputs of this inverter are called differential outputs because they are always complementary,
and it is possible to determine the output state by looking at the difference between the output voltages
(VOUT1 - VOUT2) rather than their absolute values.
√ That is, the output is 1 if (VOUT1 - VOUT2) > 0, and it is 0 if (VOUT2 – VOUT1) > 0. It is possible
to build input circuits with two wires per logical input that define the logical signal value in this way;
these are called differential inputs
Table 8: Functional table of Basic ECL gate.
2. b) What are the advantages and disadvantages of ECL? (R13 Reg Dec 2015)
ECL's major disadvantage is that each gate continuously draws current, which means it requires
(and dissipates) significantly more power than those of other logic families, especially when quiescent.
ECL has a poor speed-power product, does not provide a high level of integration, has fast edge rates
requiring design for transmission-line effects in most applications
3. (a) Draw the circuit diagram of a two-input LS-TTL NOR gate and explain the
functional behavior. (R09 Supple Jun 2016) (R13 Reg Dec 2016)
√ The NOR function is obtained by connecting OR gate with an inverting circuit.
4) Diode inputs and input protection.
5) OR function and Phase splitter.
6) Output stage.
√ If either input X or Y is HIGH, the corresponding phase-splitter transistor Q2X or Q2Y is turned on,
which turns off Q3 and Q4 while turning on Q5 and Q6, and the output is LOW.
√ If both inputs are LOW, then both phase-splitter transistors are off, and the output is forced HIGH.

√ The speed, input, and output characteristics of a TTL NOR gate are comparable to those of a TTL
NAND.
√ The TTL NOR gate’s input circuits, phase splitter, and output stage are almost identical to those of an
TTL NAND gate. The difference is that TTL NAND gate uses diodes to perform the AND function,
while TTL NOR gate uses parallel transistors in the phase splitter to perform the OR function.
√ An n-input NOR gate uses more transistors and resistors and is thus more expensive in silicon area than
an n-input NAND. Internal leakage current limits the number of Q2 transistors that can be placed in
parallel, so NOR gates have poor fan-in. As a result, NOR gates are less commonly used than NAND
gates in TTL designs.
√ The most “natural” TTL gates are inverting gates like NAND and NOR. Non-inverting TTL gates
include an extra inverting stage, typically between the input stage and the phase splitter. As a result,
non-inverting TTL gates are typically larger and slower than the inverting gates.
Table 4: Functional table of TTL-2 input NOR gate.
Figure 6: TTL-2 Input NOR gate
A B VAX Q2X VAY Q2Y Q3 Q4 Q5 Q6 Vz VOUT
L L ≤ 1.05 off ≤ 1.05 off on on off off ≥ 2.7 HIGH (5V)
L H ≤ 1.05 off 1.2 on off off on on ≤ 0.35 LOW (0V)
H L 1.2 on ≤ 1.05 off off off on on ≤ 0.35 LOW (0V)
H H 1.2 on 1.2 on off off on on ≤ 0.35 LOW (0V)

3. b) Mention the DC noise margin levels of ECL 10K family. (R09 Supple Jun 2016)
(R13 Reg Dec 2016)
Logic LOW and HIGH levels are defined in the ECL 10K family as shown in Fig. 15(a).DC noise
margins in ECL 10K are much less than in CMOS and TTL, only 0.155V in the LOW state and 0.125V in
the HIGH state. Unlike CMOS and TTL, an ECL gate generates very little power-supply and ground noise
when it changes state. Also, ECL’s emitter-follower outputs have very low impedance in either state, and it
is difficult to couple noise from an external source into a signal line driven by such a low-impedance
output.
Figure 15(a): ECL 10K Logic Levels
1. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to TTL
gate? Draw the interface circuit and explain the operation. (R13 Supple Jun 2016)
Ans: INTERFACING: Connecting outputs of one circuit to inputs of another circuit that
may have different electrical characteristics.
√ If two circuits that are going to interface have different Electrical characteristics, then
direct contact can’t be made.
√ In such cases Driver and Load circuits are connected through INTERFACE. Interface
circuitry shifts levels of voltage & current for compatibility.
√ Driver output signal must satisfy the requirements of load circuit.
√ If both driver and load require different power supplies, then outputs of both circuits must
swing between its specified voltage ranges

√ The interfacing may done in between two different logic families or with in the same logic
families.
√ Interfacing in between CMOS and TTL logic families is achieved in ways as
(a) TTL Driving CMOS circuits.
(b) CMOS driving TTL circuits.
(a) TTL Driving CMOS circuits:
√ In this TTL circuit is acts as a driver and CMOS circuit acts as Load circuit.
√ These two different family circuits must meet the voltage and current requirements.
√ Driver output signal must satisfy the requirements of load circuit.
Figure 4.30: (a) Output and input levels for interfacing TTL and CMOS families.
(b) TTL/CMOS Transfer Characteristics.
Table 4.18(a) Current comparisons of CMOS and TTL families

Table 4.18(b) Voltage levels comparisons of CMOS and TTL families
● From the above tables IIH(max), IIL(max) values for CMOS are extremely low as compared
with IOH(max), IOL(max) values of TTL, So here have the Compatibility.
● But VOH(min) for TTL less than to VIH(min) for CMOS, here voltage requirements are not
satisfied, in such cases compatibility can be done by connecting RPU
● RPU raises TTL Output to Approximately 5V in ‘HIGH’ state.
Figure 4.31: Interfacing of TTL NAND gate with CMOS NAND gate
TTL Driving HIGH Voltage CMOS:
● Sometimes we face a difficult situation that CMOS output operated with VDD > 5v.
Outputs of many TTL families can’t operate more than 5v. So we have two alternatives
(1) Use of Open collector buffer as Interface:
(2) Level Translator: It shifts the low voltage output from TTL into High voltage input for
CMOS
(a) (b)
Figure 4.32: (a) Use of Open collector buffer as Interface, (b) Level Translator

(b) CMOS Driving TTL circuits:
● CMOS Driving TTL in HIGH State: To Drive TTL in High State from tables 4.18(a) &
4.18(b) VOH(min) of CMOS, VIH(min) of TTL and IOH(max) of CMOS, IIH(max) of
TTL are Satisfied. So no Interface is required.
Figure 4.33: (b) CMOS Driving TTL in LOW State
High Voltage CMOS driving TTL: Some Manufacturers provide 74LS TTLS operating at 15v,
but many of TTLs can’t tolerate >7V. For such cases Voltage level Translators are used.
Figure 4.33: (c) High voltage CMOS Driving TTL
4. b) Explain how a CMOS device is destroyed. (R13 Supple Jun 2016)
Hit it with a sledge hammer. Or simply walk across a carpet and then touch an input pin
with your finger. Because CMOS device inputs have such high impedance, they are subject to
damage from electrostatic discharge (ESD). ESD occurs when a buildup of charge on one
surface arcs through a dielectric to another surface with the opposite charge. In the case of a
CMOS input, the dielectric is the insulation between an input transistor’s gate and its source and
drain. ESD may damage this insulation, causing a short-circuit between the device’s input and
output.

The input structures of modern CMOS devices use various measures to reduce their
susceptibility to ESD damage, but no device is completely immune. Therefore, to protect
CMOS devices from ESD damage during shipment and handling, manufacturers normally
package their devices in conductive bags, tubes, or foam. To prevent ESD damage when
handling loose CMOS devices, circuit assemblers and technicians usually wear conductive wrist
straps that are connected by a coil cord to earth ground; this prevents a static charge from
building up on their bodies as they move around the factory or lab.
Once a CMOS device is installed in a system, another possible source of damage is
latch-up. The physical input structure of just about any CMOS device contains parasitic bipolar
transistors between VCC and ground configured as a silicon-controlled rectifier (SCR).‖ In
normal operation, this “parasitic SCR” has no effect on device operation. However, an input
voltage that is less than ground or more than VCC can “trigger” the SCR, creating a virtual
short-circuit between VCC and ground. Once the SCR is triggered, the only way to turn it off is
to turn off the power supply. Before you have a chance to do this, enough power may be
dissipated to destroy the device (i.e., you may see smoke). One possible trigger for latch-up is
“undershoot” on high-speed HIGH-to- LOW signal transitions.
In this situation, the input signal may go several volts below ground for several
nanoseconds before settling into the normal LOW range. However, modern CMOS logic
circuits are fabricated with special structures that prevent latch-up in this transient case. Latch-
up can also occur when CMOS inputs are driven by the outputs of another system or subsystem
with a separate power supply. If a HIGH input is applied to a CMOS gate before power is
present, the gate may come up in the “latched-up” state when power is applied. Again, modern
CMOS logic circuits are fabricated with special structures that prevent this in most cases.
However, if the driving output is capable of sourcing lots of current (e.g., tens of mA), latchup
is still possible. One solution to this problem is to apply power before hooking up input cables.
5.(a) Discuss about CMOS dynamic electrical behavior with characteristics.
(R13 Supple Jun 2016)
The behaviour of a circuit in which the electrical state of the inputs and outputs fluctuate (vary) is referred
to a CMOS dynamic or AC electrical behaviour. The various CMOS dynamic electrical characteristics are
described as follows,
2.Transition Time (Tt):- The Speed of the CMOS device depends on two characteristics: Transition time
and Propagation delay. The amount of time that the output of a logic circuit takes to change from one
state to another is called the “transition time”. The fig.9 (a) shows the actual transition times. In
practice, the outputs cannot change instantaneously, because they need time to charge the stray
capacitance of the wires and other components that they drive. The stray capacitance is also called a
“Capacitive Load” or an “AC Load” of the logic circuit.
Rise time (tr): It is the time taken by the output to change from LOW to HIGH.
Fall time (tf): It is the time taken by the output to change from HIGH to LOW.

The rise time and fall time of a CMOS output depends mainly on two factors, the ON transistor
resistance and the Load capacitance. Since increase in load capacitance increase in transition time, it is
not desirable to connect a capacitor to the output of logic circuit. However, the stray capacitance is
present in every circuit.
Fig. 9(a): Transition times
The fig. 9(b) shows the equivalent circuit for analyzing transition times of a CMOS output. As shown in
fig. 9(b), the equivalent load circuit consists of three components, RL, VL and CL. The RL and VL represent
the DC Load. They determine the voltages and currents that are present when the output has settled into a
stable HIGH or LOW state. The CL represents the AC Load. It determines the voltages and currents that
are present when the output is changing i.e. during transitions.
Fig. 9(b): Circuit for Transient time analysis
Analysis ofFall time (tf): Assume RL= ∞,VL=0, CL=100pF and Rn=100Ω for this analysis and fig.9 (c)
shows the circuit for the analysis of fall time.
Fig. 9(c): Circuit for analysis of fall time

Fig.9(d): Output for Fall time
At time t=0, VOUT is 5.0V and t=∞, VOUT is 0V as shown in fig.9 (d). In between, the capacitor is
discharged and the value of VOUT is governed by an exponential law:
VOUT = VDD e-t / Rn CL
= 5.0 V
= 5.0 V
The Product Rn CL is the time constant. Here, for HIGH to LOW transition the time constant is
. Solving the above equation for VOUT =3.5V and VOUT =1.5V we get,
t3.5 = - Rn CL ln
= -10 10-9
ln
= 3.57 ns
t1.5 = - Rn CL ln
= -10 10-9
ln
= 12.04 ns
Therefore,Fall time (tf) = t1.5 - t3.5
= 12.04 ns - 3.57 ns
= 8.47 ns
Analysis ofRise time (tr): Assume RL= ∞,VL=0,CL=100pF and Rp=200Ω for this analysis and fig.9 (e)
shows the circuit for the analysis of Rise time.
Fig. 9(e): Circuit for analysis of Rise time

Fig. 9(f): Output for Rise time
At time t=0, VOUT is 0V and t=∞, VOUT is 5.0V as shown in fig.9 (f). In between, the capacitor is
discharged and the value of VOUT is governed by an exponential law:
VOUT = VDD (1-e-t / Rp CL
)
= 5.0 V
= 5.0 V
The Product Rp CL is the time constant. Here, for LOW to HIGH transition the time constant is
. Solving the above equation for VOUT =3.5V and VOUT =1.5V we get,
t3.5 = - Rp CL ln
= -20 10-9
ln
= 24.08 ns
t1.5 = - Rp CL ln
= -10 10-9
ln
= 7.13 ns
Therefore,Rise time (tr) = t3.5 – t1.5
= 24.08 ns – 7.13 ns
= 16.95 ns
3. Propagation Delay (tP):- The propagation delay is the amount of time that it takes for a change in the
input signal to produce a change in the output signal. The propagation delay of a gate is basically the
time interval between the application of an input pulse and the occurrence of the resulting
output pulse. The propagation delay is a very important characteristic of logic circuits because it limits
the speed at which they can operate. The shorter the propagation delay, the higher the speed of the
circuit and vice-versa. The propagation delay is determined using two basic time intervals as shown in
fig. 10(a).
a) tPLH : It is the delay time measured when output is changing from logic0 to logic1 state (LOW to
HIGH).

b) tPHL : It is the delay time measured when output is changing from logic1 to logic0 state (HIGH to
LOW).
Fig. 10(a): propagation delay times of Inverter
The propagation delays are measured between 50 percent points on the input and output transitions.
Sometimes the propagation delay is taken as simple average of the two.
tP = (tPHL+ tPLH)
4. Power Dissipation(PD):-
The power consumption of a CMOS circuit whose output is not changing is called static power
dissipation or quiescent power dissipation. Most of the CMOS circuits have very low static power
dissipation. On the other hand, the power consumption of a CMOS circuit during transition is known as
dynamic power dissipation.
The power dissipation during transition is given by
PT =
Where, PT = Internal power dissipation during transitions
= Power dissipation capacitance. It is specified by the manufacturer. for HC CMOS series
gate is typically 20-24pF.
VCC = Power supply voltage
f = Transition frequency of the output signal.
The above formula is valid for only if input transitions are fast enough, leading to fast output transitions. If
the input transitions are too slow, then the output transistors stay ON for longer time, and power
consumption increases.
The second source of power consumption is due to capacitive load (CL). During a LOW-to-HIGH
transition CL charges through a p-channel transistor and it discharges through n-channel transistor during
HIGH-to-LOW transition. The power dissipation due to capacitive load is given by,
PL =
The total dynamic power dissipation of a CMOS circuit is the sum of PT and PL.
PD = PT + PL

= +
= where C = ) and V = VCC
= C V2
f
5.(b) Explain the following terms with reference to CMOS logic:
i) Logic Levels. ii) Noise margin. iii) Power supply rails. iv) Fan-in v) Fan-out
Ans: i) Logic Levels:- The CMOS device manufacturers specify the four voltage parameters. They are,
VOH (min)high-level output voltage, the minimum voltage level that a logic gate will produce
a logic 1 output.
VIH (min) high-level input voltage, the minimum voltage level that a logic gate will recognize
as a logic 1 input. Voltage below this level will not be accepted as high.
VOL (max) low-level output voltage, the maximum voltage level that a logic gate will produce
a logic 0 output.
VIL (max) low-level input voltage, the maximum voltage level that a logic gate will recognize
as a logic 0 input. Voltage above this value will not be accepted as low.
The input voltages are determined mainly by switching thresholds of the two transistors, while the
output voltages are determined mainly by the “on” resistance of the transistors.
The power-supply voltage VCC and ground are often called the power supply rails. CMOS levels are
typically a function of the power-supply rails:
IOH high-level output current, current that flows from an output in the logic 1 state under
specified load conditions.
IIH high-level input current, current that flows into an input when logic 1 voltage is applied to
that input.
IOL  low-level output current, current that flows from an output in the logic 0 state under
specified load conditions.
IIL  low-level input current, current that flows into an input when a logic 0 voltage is applied to
that input.

Fig.7(a): Current and Voltages in the two logic gates
ii) Power supply rails: The power-supply voltage VCC and ground are often called the power supply
rails.
iii) Noise Margin:- In Practice, due to the unwanted signal called noise, sometimes the voltage at the input
drops below VIH (min) or rise above VIL (max), which produces unpredictable operation. Noise immunity
of a logic circuit refers to the circuit’s ability to tolerate noise without causing spurious changes in the
output voltage. A quantitative measure of noise immunity is called “noise margin”.
To avoid this problem due to noise, voltage level VIH (min) is kept a few fraction of volts below
VOH (min) and voltage level VIL (max) is kept above VOL (max), at the design time as shown in fig.7(a).
As shown in fig.7(a), VNH is the difference between the lowest possible HIGH output, VOH (min)
and the minimum voltage, VIH (min) required for a HIGH input. This voltage difference, VNH is called
“HIGH-state DC noise margin”. Similarly, we have LOW-state DC noise margin and it is the voltage
difference between the largest possible low output, VOL (max) and the maximum voltage, VIL (max)
required for a LOW input.
High Level Noise Margin, VNH = VOH (min) - VIH (min)
Low Level Noise Margin, VNL = VIL (max) - VOL (max)
iv) Fan-In:- The maximum number of inputs available on any one gate is called Fan-in.
(or)
The number of inputs that a gate can have in a particular logic family is called fan-in of that logic family.
The k n-channel transistors connected in series have lower ‘ON’ resistance than the k p-
channel transistors connected in series. As a result, a k-input NAND gate which uses n-channel transistors
in series is generally faster than and preferred over k-input NOR gate. The additive ON resistance of series

transistors limits the fan-in of CMOS gates. Typically fan-in for NAND gates is 6 and fan-in for NOR
gates is 4.
One way to increase the fan-in is to increase the size of the series transistor reducing their
resistance. However, it is not always practical. Thus, gates with a large number of inputs are used by
cascading gates with fewer inputs.
v) Fan-Out:- The fan out of a logic gate is the number of inputs that the gate can drive without exceeding
worst-case specifications.
(or)
The number of inputs that an output can drive with the output in a constant state (HIGH or LOW) is called
“DC fan-out”. The fan-out depends not only on the characteristics of the output, but also on the inputs that
it is driving.
The ability of an output to charge and discharge stray capacitance is sometime called “AC fan-out”.
6.a)Draw neat circuit diagram, function table and logic symbol of a 2- input CMOS NAND
gate. (R13 Reg Dec 2015)
√ NAND gate is one of the basic logic gates to perform the digital operation on the input signals.
√ It is the combination of AND Gate followed by NOT gate i.e. it is the opposite operation of AND
gate where the Logic NAND gate is complementary of AND gate.
√ The logic output of NAND gate is low (FALSE) only when the inputs are high (TRUE).
√ To implement 2-Input NAND gate using CMOS logic we require 2 pull-up PMOS and 2 pull-
√ Fig.(3) shows the function table, logic symbol and circuit diagram for CMOS 2-input NAND gate.
It consists of two P-channel MOSFETs Q2 and Q4, connected in parallel and two N-channel
MOSFETs, Q1 and Q3 connected in series.
√ Fig.3(d) shows the switch model for 2-input NAND gate.

Fig.3(a): Switch model for 2-input CMOS NAND gate
6.b) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the
help of functional operation?
√ The NAND function is obtained by connecting AND gate with an inverting circuit.
4) Diode AND gate and input protection.
5) Phase splitter.
6) Output stage.
Diode AND gate and input protection: Diodes D1, D2 and resistor R1 form a diode AND gate, Clamp
diodes D5 and D6 do nothing in normal operation, but limit undesirable large negative voltages may occur
on HIGH-to-LOW input transitions as a result of transmission-line effects. They are called as protective
diodes.
Phase splitter: Transistor Q2 and the surrounding R2, R3 and R4 resistors form a phase splitter that
controls the output stage. Depending on whether the diode AND gate produces a “low” or a “high” voltage
at VA, Q2 is either cut off or turned on. Diode AND gate and input protection and Phase splitter form
NAND gate.
Output stage: The output stage has two transistors, Q4 and Q5, only one of which is ON at any time. The
TTL output stage is sometimes called a totem-pole or push-pull output which is similar to the p-channel
and n-channel transistors in CMOS. Q4 and Q5 transistors provide active pull-up and pull-down to the
HIGH and LOW states, respectively. Except Q4 remaining all transistors are Schottky clamped transistors
because it can’t saturate. Q3 and Q4 connected in Darlington pair which may provide shorter output rise

time when switching from OFF to ON. Q6 regulates current flow into base of Q5 and helps to it in turning
to OFF.
Figure 4(c): TTL-2 input NAND gate
Table 3: Functional table of TTL-2 input NAND gate.
Inputs
VA
Transistors
VZ
Output
A B Q2 Q3 Q4 Q5 Q6 VOUT
L L ≤ 1.05 off on on off off 2.7 HIGH (5V)
L H ≤ 1.05 off on on off off 2.7 HIGH (5V)
H L ≤ 1.05 off on on off off 2.7 HIGH (5V)
H H 1.2 on off off on on ≤ 0.35 LOW (0V)

UNIT-I
IMPORTANT QUESTIONS
1.a) Design a 4 input CMOS AND-OR-INVERT gate. Draw the logic diagram and explain the operation
with the help of function table.
b) Explain the parameters that are necessary to define the electrical Behaviour of CMOS circuits?
(R13 Reg Dec 2016)
2. Design a transistor circuit of 2-input TTL NOR gate. Explain the operation with the help of function
table. (R13 Reg Dec 2016)
3. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to TTL gate?Draw the
interface circuit and explain the operation.
b) Explain how a CMOS device is destroyed. (R13 Supple Jun 2016)
4. (a) Discuss about CMOS dynamic electrical behavior with characteristics.
b) Mention the DC noise margin levels of ECL 10K family. (R13 Supple Jun 2016)
5.a) Design a CMOS transistor circuit that has the functional behavior:
b) Design a 4-input CMOS AND-OR-INVERT gate? Draw the logic diagram and function table
(R09 Supple Jun 2016)
6. (a) Draw the circuit diagram of a two-input LS-TTL NOR gate and explain the functional behavior.
7. (a) Explain the following terms with reference to CMOS logic:
i) Logic Levels. Ii) Noise margin. iii) Power supply rails. iv) Propagation delay.
(R09 Supple Dec 2016)
b) What is the difference between transmission time and propagation delay? Explain.
8.a) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help of
functional operation?
b) List out TTL families and compare them with reference to propagation delay, power consumption,
speed-power product and low level input current. (R09 Supple Dec 2016)
9.a) Compare the characteristics of the different types of MOS inverters in terms of noise margin and
power dissipation.
b) Draw neat circuit diagram, function table and logic symbol of a 2- input CMOS NAND gate.
(R13 Reg Dec 2015)
10.a) Explain the principle of a Emitter-Coupled Logic (ECL/CML) through Basic ECL inverter/buffer
circuit with input HIGH and LOW.
b) What are the advantages and disadvantages of ECL? (R13 Reg Dec 2015)
11. a) Design a CMOS transistor circuit with the functional behavior:
b) Distinguish between static and dynamic power dissipation of a CMOS circuit. Derive the expression for
dynamic power dissipation. (R09 Supple Dec 2015)
12. a) Draw the circuit diagram of two-input 10K ECL OR gate and explain the circuit.
b) Explain sinking current and sourcing current of TTL output. Which of the above parameters decide the
fan-out and how? (R09 Supple Dec 2015)
13. (a) Draw the transistor logic inverter circuit and analyze the circuit behavior with the help of transfer
characteristics.
b) Design a CMOS transistor circuit that has the functional behavior: (R09 Supple Dec 2015)

14. a) Draw the transistor logic inverter circuit and analyze the circuit behavior with the help of transfer
characteristics.
b) Design CMOS transistor circuit for 2-input AND gate. Explain the circuit with the help of function
15. a) Explain the following terms with reference to TTL gate:
(i) Logic levels.
(ii) DC Noise margin.
(iii) Low-state unit load.
(iv) High-state fan-out
b) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation with the help of function
16. Design a CMOS transistor circuit with the functional behavior:
f(X) = (A + )(B + C + )(A + ). (R09 Supple Jun 2014)
17. a) Draw the circuit diagram of a two-input LS-TTL NOR gate. Explain the functional behavior.
18. a) Explain how a CMOS device is destroyed.
b) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the help of logic diagram and
function table. (R09 Reg Dec 2013)
19. a) Design a TTL three-state NAND gate and explain the operation with the help of function table.
b) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation with the help of function
20.a) Design a three input NAND gate using diode logic and a transistor inverter. Analyze the circuit with
the help of transfer characteristics.
b) Explain how a CMOS device is destroyed. (R09 Reg Dec 2013)
21. a) Draw the circuit diagram of basic CMS gate and explain the operation.
b) Mention the DC noise margin levels of ECL 10K family. (R09 Reg Dec 2013)
22.a) Explain the effect of floating inputs on CMOS gate. Explain how a CMOS device is destroyed.
b) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the help of logic diagram and
function table. (R09 Reg Dec 2013)
23. a) Explain the effect of floating inputs on CMOS gate.
b) Explain how a CMOS device is destroyed.
c) What is the difference between transmission time and propagation delay? Explain these two parameters
with reference to CMOS logic. (R09 Supple May 2013)
24. a) Compare CMOS, TTL and ECL with reference to logic levels, DC noise margin, propagation delay
and fan-out. (R09 Supple May 2013)
b) Draw the circuit diagram of basic CMS gate and explain the operation.
25. a) Draw the logic diagram equivalent to the internal structure of an 8-input CMOS NAND gate.
b) Show the transistor circuit for this gate and explain the operation with the help of function table.
(R09 Reg Dec 2012)
26. a) Draw the circuit diagram of basic CMOS gate and explain its operation.
b) What are the typical parts of a TTL data sheet and discuss their importance in circuit design?
(R09 Reg Dec 2012)
27. a) Design a 4-input CMOS AND-OR-INVERT gate. Draw the logic diagram and function table.
b) Draw the resistive model of a CMOS inverter and explain its behavior for LOW and HIGH outputs.
(R09 Reg Dec 2012)
28. a) Design CMOS transistor circuit for 3-input AND gate. With the help of function table explain the

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