On verification and validation methods in v-system model

1. 1
Investigation on V­System Model in
System Engineering.
Prof. Frank Appiah, AKA FAEng PhD
Rough Draft
(2020/2021)

2. 2
UCL, CENTRE OF SYSTEMS
ENGINEERING
●
Crash course on
system engineering
●
Outline on verfication
and validation.
●
On V­system model
in system
engineering.
●
Software Verification
and Software
Validation.
●
Centre with interest in
the development of
complex hetero­
genous systems.

3. 3
Lets Begin on Approaches
●
Verification ●
Validation
V

4. 4
Two Approaches: Which first?
●
Verification(v)
●
Validation(V)
V­2­V: Convergent Approach

5. 5
V­2­V Graph

6. 6
System Model
●
Verification has a negative gradient in system
model.
●
Validation has a positive gradient in system
model.

7. 7
System Work(1)
●
On verification coding, there are a lot of work in
achieving success in this phase.
●
That account for the negative gradient; many
negative choices or decisions to come to a
plan.
●
Coding of verification is approached after 4
main system process models.

8. 8
System Model(2)
●
On validation coding, there is a positive and
easy means to find solutions to problems or
user requirements.
●
This has positive gradient in system model.
●
Coding of validation can be approached from 4
system models aside coding itself.
●
There are less solutions available to deal with
from the on­start.
●
There is a gradual increase in system solutions
after contigent planning.

9. 9
Convergent System Model
The convergent system model is the coding
model in the system. Verification and Validation
will convergent on coding system in V­System.
Coding system is a convergent approach in the
baseline of V­system architecture.

10. 10
Integration Testing Equilibrium
(ITE)
> High Level Design (HLD)
> Integration Testing Plan (ITP)
> Integration Testing (IT)
This is roughly assumed on the middle line of
V­system model.

11. 11
HLD is a verfication system approach and IT is a
validation system approach. The two is
connected by ITP in middle­level approach in V­
system model.

12. 12
V­2­V System Lines
There are about 5 levels of system model from
V­architecture. There are two sides to the
architecture. Left­level systems approaching
downwards and Right­level systems
approaching as well.

13. 13
Verification­2­Validation System
Lines (SL).
●
SL5: User Requirement – Acceptance Test
Plan – Acceptance Testing
●
SL4: Software Application – System Test Plan
– System Testing
●
SL3: High Level Design – Integration Test Plan
– Integration Testing
●
SL2: Detailed Design – Unit Testing Plan –
Unit Testing
●
SL1: Coding

14. 14
L5­L1 System Model
L5: User Requirement (UR)
L4: Software Application (SA)
L3: High Level Design (HLD)
L2: Detailed Design (DD)
L1: Coding (C)
(Top):UR < SA < HLD < DD < C :(Bottom)

15. 15
R5­R1 System Model
R5: Acceptance Testing (AT)
R4: System Testing (ST)
R3: Integration Testing (IT)
R2: Unit Testing (UT)
R1: Coding (C)
(Top):AT < ST < IT < UT < C :(Bottom)

16. 16
System Modes
●
V2V SL Model
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L5­L1System Model
●
R5­R1System Model
These altogether forms the V­system model in one
architecture.

17. 17
Grading System Models in V­
architecture.
Software Application Grade
SA­Grade is user requirement size(ur) over high
level design size(hld) in a system model.
SAGrade=
UR
HLD

18. 18
Detailed Design Grade
Detailed Design Grade is high level design(hld)
size over length of coding in a system model.
DDgrade=
HLD
Clength

19. 19
High Level Design Grade
High Leve Design(HLD) Grade is byte size of
software application (SA) over detailed
design(DD) size in a system model.
HLDgrade=
SA
DD

20. 20
On Validation Grades
Unit Testing(UT) Grade is size of integration
testing(IT) over the length of codes(C) in a
system model.
UTgrade=
IT
C

21. 21
Integration Testing Grade
Integration Testing grade is size of system
testing over sizee of unit testing is a system
model.
IT grade=
ST
UT

22. 22
System Testing Grade
System Testing Grade is the size of acceptance
testing over size of integration testing.
ST grade=
AT
IT

23. 23
Grade Ratios
●
System Testing Grade
●
Integration Testing Grade
●
Unit Testing Grade
●
High Level Design Grade
●
Software Application Grade
●
Detailed Design Grade.

24. 24
Detailed Design Grade Ratios
This means that it is a valid and verified to have a
detailed design grade if the UR size is known then
SA holds to be checked and if SA is byte size is
known then C holds to be checked.
UR
SA
C
=DD

25. 25
DD­Grade Ratio 2
DD Grade Ratio 2 is valid and verified if UR size
is known then SA is checked, if SA byte size is
known then HLD is checked and finally if HLD
size is known then DD is checked.
Roughly, DD is the root of the DD­grade ratio 1.
The root analysis of V­system model is by
grading a detailed design model.
UR
SA
HLD
DD
=DD

26. 26
DD2 Root Analysis
Similar Root Analysis can be the distance among
UR, SA, HLD.
DD2
=
UR
SA
HLD
=

UR
SA
HLD

=UR/SA/HLD
DD=UR2
SA2
HLD2


27. 27
SHAPING V­2­V MODELS
In shaping the V­2­V models, several shapes of
formation are employed in the analysis of the
models in general.

28. 28
Shapes
●
Diamond(◊) shape
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Trapezium shape
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Triangle(∆) shape
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V­shape
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^­shape
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/­shape
●
­shape
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Area Shape

29. 29
●
●
●
V­system scatter
depicts a scatter
system model in an
unorganised manner
without any
hierarchical role of
assignment.

30. 30
V­System
Network
●
There are four areas in the
network model of v­system.
●
R1, R2, R3 and R4 forms the
system model.
●
R1:C­>UT­>UTP­>DD
●
R2:DD­>UTP­>UT­>IT­>ITP­
>HLD
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R3:HLD­>ITP­>IT­>ST­
>STP­>SA
●
R4:SA­>STP­>ST­>AT­
>ATP­>UR.

31. 31
R1: Wide Network Users
V­system network is formed from area regions
formed in the main v­system itself;
R1 is the widely used in practice­ This means
that you start coding then you do unit testing,
then to unit testing plan and finally detailed
design is made.

32. 32
R4: Software Architect
Software Architects like myself will definitely start
with SA then to STP following on to system test
then to acceptance testing following onto
acceptane testing plan and finally user
requirement.

33. 33
●
This is a hierarchical model of v­
system.
●
There are 9­levels in the system
model itself.
●
Level 1­ Coding
●
Level 2­ Unit Testing(UT) and
Detailed Design
●
Level 3­ UT Plan
●
Level 4­ Integration Testing and
High Level Design
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Level 5­ Integration Testing Plan
●
Level 6­ Software Architecture and
System Test

34. 34
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Level 7­ System Test Planning
●
Level 8­ User Requirement and Acceptance
Testing
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Level 9­ Acceptance Testing Plan.

35. 35
On Shaping
V­2­V
●
◊ Shaping V­2­V,
●
Same as R1 in
system network.
◊

36. 36
On Shaping
V­2­V
●
Trapezium Shaping
●
V­2­V,
●
Same as R1 in
system network.
◊

37. 37
V­Shape V2V System Model
●
VSM1:: DD – UTP – UT
●
VSM2:: HLD – ITP – IT
●
VSM3:: SA – STP – ST
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VSM4:: UR – ATP – AT
These are the VSMs in V2V system model.

38. 38
Logical Shaping
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VSM1:: DD V UTP V UT ­­> DD or UTP or UR
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VSM2:: HLD V ITP V IT ­­> HLD or ITP or IT
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VSM3:: SA V STP V ST ­­> SA or STP or ST
●
VSM4:: UR V ATP V AT ­­> UR or ATP or AT
Logical shaping a V2V system model can
interpret V as a logical or. This will mean to
separate each system model into independent
system models.

39. 39
Interpretation
●
VSM1 can be either a DD or UTP or UT
●
VSM2 can be either a HLD or ITP or IT
●
VSM3 can be either a SA or STP or ST
●
VSM4 can be wither a UR or ATP or AT.

40. 40
^­Shape in System Model
It is shaped as C­DD, C­UT, UT­C­DD=TD, HLD­
TD­IT=HT, SA­HT­ST=SS and UR­SS­AT=RT.
There are six branches in this system model:
(1) Coding to Detailed Design.
(2) Coding to Unit Testing.
(3) Unit Testing to Coding to Detailed Design is Test Design(TD).
(4) High­Level Design to Test Design to Integration Testing is High­Design
Testing.
(5) Software Architecture to High Design Testing to System Test is Software
System.
(6) User Requirement to Software System to Acceptance Testing is
Requirement Testing.

41. 41
(/)Slant­Forward System Model
●
UR – SA – HLD – DD – C .
User Requirement then to Software Architecture
to High­Level Design then to Detailed Design to
Coding.
●
UTP – UT
●
ITP – IT
●
STP – ST
●
ATP – AT.

42. 42
()Slant­Backward System Model
●
AT – ST – IT – UT – C.
Acceptance testing then to System Test to
Integration Testing to Unit Testing to Coding.

43. 43
Reverse System Model
●
C – DD – HLD – SA – UR .
●
User Requirement then to Software
Architecture to High­Level Design then to
Detailed Design to Coding is a reverse process.

44. 44
System Model Plans
ATP – STP – ITP – UTP – C
Acceptance Testing Plan to System Testing Plan
to Integration Testing Plan to Unit Testing Plan
finally to Coding.

45. 45
Transversal Method
It is simply methodized on selecting a connection
on the rule of node­path­node. Indications of a
last system node has double circle just like
automaton.

46. 46
●
System
Integrations

47. 47

48. 48

49. 49

50. 50

51. 51
System Implementations

52. 52

53. 53

54. 54

55. 55
System Integration Approaches
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Middle­out Approach
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Top­Down Approach
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Bottom­up Approach
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End of Rough
course on system
model with V­
Architecture.
V­SYSTEM MODEL IS AN INTEGRATION OF SOFTWARE APPLICATIONS BASED ON
A COMPUTER SYSTEM. THIS CAN BE A COMPILER, TRANSLATOR, INTERPRETER,
CODING DOMAIN­SPECIFIC LANGUAGE, INTERGRATED DEVELOPMENT ENVIRON­
MENT AND SYSTEM THEORY IN ONE WHOLE SYSTEM DEVELOPMENT.

56. 56
CIGSIQ System Development
●
Fresh outlook on
development and now
a systematic
development for a
team model.
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CIGSIQ means
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C: Change
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I:Improve
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G:Grow
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S: Skill
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I:Idea
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Q:Quality

57. 57
CIGSIQ StrawCourtesy: Prof F. Appiah

58. 58
CIGSIQ STRAW
This is a means of illustration where you have
about 10 straws placed in a jar ready to sip some
juice. Each straw has a node name taped to it at
the top. The arrangement forms a spiral formation
with each other following a C­I­G­S­I­Q Straw.
Do it at home as practice.

59. 59
UCL Centre of
Systems
Engineering,
UK.
Final Message
●
Thanks for
attending!!!!!!!!
●
●
Virtual Event :
Eventbrite
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Title: Investigation
into V­systems model
in system engineering
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Twitter: @frankappiah