Clark Shepard is an electrical engineer seeking a position where he can develop novel and sustainable product test and manufacturing solutions. He has over 15 years of experience in product and test development at Freescale Semiconductor and Motorola, where he led teams to improve quality, meet schedules, and address design issues. Some of his accomplishments include developing low-cost test solutions, analyzing testability features, improving yield, and specifying internal timing constraints to test parts at full speed.
IRJET- A Review- FPGA based Architectures for Image Capturing Consequently Pr...IRJET Journal
This document presents a review of FPGA-based architectures for image capturing, processing, and display using a VGA monitor. It discusses using the Xilinx AccelDSP tool to develop the system on a Spartan 3E FPGA. The AccelDSP tool allows converting a MATLAB design into HDL for implementation on the FPGA. It summarizes the FPGA-based system architecture, which includes units for initialization, data transfer, image processing, and memory management. It then outlines the Xilinx AccelDSP design flow, which verifies the functionality at each stage of converting the floating-point MATLAB model to a fixed-point hardware implementation on the FPGA. The goal is to accelerate image processing applications using the parallel
Sajeeda Parveen B K has over 5 years of experience in storage domain testing and quality assurance. She has hands-on experience with NetApp storage systems, LSI storage arrays, and testing methodologies like STLC, functional testing, and automation testing using tools like ALM, BURT, and ELMS. She is proficient in NetApp ONTAP, Linux, Windows and storage protocols like SCSI, FC, and SAS. She aims to take up a role in software engineering testing or quality assurance with a leading IT organization.
Learn an overview of design trends and designer challenges, simulator extensions for models and abstraction levels in PSpice, and examples of a coding algorithm models into PSpice PCB level cycle
Gary O'Gorman has over 14 years of experience with Emerson's DeltaV DCS. He has worked on numerous projects as a control system engineer and FDS author for companies like Zenith Technologies, Pfizer, GSK, Eli Lilly and more. His roles have included designing control strategies, configuring equipment modules, authoring procedures and supporting commissioning teams. He also has experience training others and implementing validation protocols.
The document provides profile information and career details for Chandan Merwade. It summarizes his education as an Electronics and Communication Engineering graduate with experience in ASIC design physical layout. His core competencies include understanding CMOS theory, the physical design flow, placement and routing. Projects involved block-level design of circuits using Synopsys and Cadence tools, addressing challenges like timing closure and design rule violations.
Nagesh Kalal has over 8 years of experience in software testing, including automation testing on Nutanix storage clusters, Cisco Nexus switches, and embedded software. He has expertise in test planning, execution, defect tracking, and automation using tools like Selenium, Python, and TCL scripting. Currently he is leading a team performing automation testing on Cisco Nexus switches using the PyATS framework.
Ganesh Machavarapu is seeking a role in the VLSI industry to further develop his professional skills. He has 1.5 years of experience in physical design using tools like Cadence and Synopsys. His experience includes floorplanning, placement, routing, timing closure and layout verification for designs up to 14nm processes. He completed internships at Intel and local companies where he worked on full chip implementation and verification flows. Ganesh holds an MTech in VLSI design and has skills in Verilog, Perl, Tcl and Python.
Clark Shepard is an electrical engineer seeking a position where he can develop novel and sustainable product test and manufacturing solutions. He has over 15 years of experience in product and test development at Freescale Semiconductor and Motorola, where he led teams to improve quality, meet schedules, and address design issues. Some of his accomplishments include developing low-cost test solutions, analyzing testability features, improving yield, and specifying internal timing constraints to test parts at full speed.
IRJET- A Review- FPGA based Architectures for Image Capturing Consequently Pr...IRJET Journal
This document presents a review of FPGA-based architectures for image capturing, processing, and display using a VGA monitor. It discusses using the Xilinx AccelDSP tool to develop the system on a Spartan 3E FPGA. The AccelDSP tool allows converting a MATLAB design into HDL for implementation on the FPGA. It summarizes the FPGA-based system architecture, which includes units for initialization, data transfer, image processing, and memory management. It then outlines the Xilinx AccelDSP design flow, which verifies the functionality at each stage of converting the floating-point MATLAB model to a fixed-point hardware implementation on the FPGA. The goal is to accelerate image processing applications using the parallel
Sajeeda Parveen B K has over 5 years of experience in storage domain testing and quality assurance. She has hands-on experience with NetApp storage systems, LSI storage arrays, and testing methodologies like STLC, functional testing, and automation testing using tools like ALM, BURT, and ELMS. She is proficient in NetApp ONTAP, Linux, Windows and storage protocols like SCSI, FC, and SAS. She aims to take up a role in software engineering testing or quality assurance with a leading IT organization.
Learn an overview of design trends and designer challenges, simulator extensions for models and abstraction levels in PSpice, and examples of a coding algorithm models into PSpice PCB level cycle
Gary O'Gorman has over 14 years of experience with Emerson's DeltaV DCS. He has worked on numerous projects as a control system engineer and FDS author for companies like Zenith Technologies, Pfizer, GSK, Eli Lilly and more. His roles have included designing control strategies, configuring equipment modules, authoring procedures and supporting commissioning teams. He also has experience training others and implementing validation protocols.
The document provides profile information and career details for Chandan Merwade. It summarizes his education as an Electronics and Communication Engineering graduate with experience in ASIC design physical layout. His core competencies include understanding CMOS theory, the physical design flow, placement and routing. Projects involved block-level design of circuits using Synopsys and Cadence tools, addressing challenges like timing closure and design rule violations.
Nagesh Kalal has over 8 years of experience in software testing, including automation testing on Nutanix storage clusters, Cisco Nexus switches, and embedded software. He has expertise in test planning, execution, defect tracking, and automation using tools like Selenium, Python, and TCL scripting. Currently he is leading a team performing automation testing on Cisco Nexus switches using the PyATS framework.
Ganesh Machavarapu is seeking a role in the VLSI industry to further develop his professional skills. He has 1.5 years of experience in physical design using tools like Cadence and Synopsys. His experience includes floorplanning, placement, routing, timing closure and layout verification for designs up to 14nm processes. He completed internships at Intel and local companies where he worked on full chip implementation and verification flows. Ganesh holds an MTech in VLSI design and has skills in Verilog, Perl, Tcl and Python.
Naveen Reddy has over 15 years of experience in semiconductor test engineering. He holds an MS in Computer & Electrical Engineering from Illinois Institute of Technology and a Bachelor's degree in Electronics and Communications from Dayananda Sagar College of Engineering in India. Currently he works as a Principal Test Engineer at Broadcom, where he develops test programs for digital front end and networking chip products. Previously he held test engineering roles at companies including Optichron, Centillium, Integrated Device Technology, and Advantest America.
Dayashankar Srinivasan is a R&D Engineer with over 4 years of experience in FPGA design, RTL coding, verification, and algorithm development. He currently works for Logic-fruit Technologies in Gurgaon/Bangalore and has previously worked for SAMEER CEM, the research division of the Government of India. He has extensive experience with Xilinx FPGAs including the Spartan 6, Virtex 6, and Kintex 7, as well as languages like VHDL, Verilog, C, and MATLAB. His projects include work on LTE communication systems, image processing, TWT systems for DRDO, and OFDM protocols. He has a Master's in VLSI
This document is a resume for Christopher J. Reder. It summarizes his education, work experience, and technical skills. He has a B.S. in Electrical Engineering from Auburn University and over 15 years of experience in software engineering roles developing networking hardware and software. His experience includes work at Cisco Systems, Extreme Networks, Overture Networks, Hatteras Networks, Digital Concepts Inc., and ADTRAN Inc., where he has led projects, mentored other engineers, implemented new features, found and fixed bugs, and interfaced with customers.
Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the modular netlist and test languages (ICL and PDL) to facilitate the description of the components involved in analog tests as well as the content of the tests themselves.
This document summarizes a presentation given at the 3rd Asia Academic Forum in Kuala Lumpur from November 13-15, 2006. The presentation introduces process control systems (PCS) and their importance to Intel's assembly and test operations. It discusses challenges faced by PCS including poor signal detection, data system limitations, and human errors. It outlines Intel's PCS strategy to improve detection and prevention, deliver automation solutions, and build a high performance PCS culture. The presentation shows how PCS has evolved and will continue to advance with new technologies. It proposes areas of joint opportunity between Intel and universities.
The document discusses validation and design in small teams with limited resources. It proposes constraining designs to a single clock rate, using FIFO interfaces between blocks, and separating algorithm from IO verification to simplify validation. This approach allows designs to be completed more quickly with fewer verification engineers through standardized, repeatable validation methods at the cost of optimal performance.
Join us for a presentation on the benefits of using PSpice® in an integrated OrCAD flow. For new users, we’ll cover how to get started and where to find working examples. The next step is where to find specific models and how to create them if they’re not available anywhere. Finally we’ll go deeper into the tool to see how it can help us if we run into trouble by identifying parts that are close to failure.
Combining requirements engineering and testing in agile. SYSQA BV
Agile Testing Days Berlin, november 2012
Projects that use agile have small, multidisciplinary teams. When every discipline has its own specialist in the team, the team becomes bigger and bigger leading to more communication, coordination and more need for documentation. Combining programming and testing is not a wise decision but combining requirements engineering and testing is very well possible. It even turns out that a lot of communication, documentation and coordination is not necessary. So a lot of time and effort can be saved. During his presentation Jan Jaap tells why testers are excellent requirements engineers (and vice versa) and what the advantages of combining requirements engineering and testing can be. He also addresses what testers should do to get this combined role. With agile becoming more and more popular this can be a possible future for testers.
The idea of combining requirements engineering and testing started with a vision. By now we have enough practical experience to show that is actually works! During the presentation Jan Jaap shares vision and practical experiences.
Sr. Kakarla is a physical design engineer with over 6 years of experience in roles including IC physical design, CAD STA, layout design automation, and corporate design solutions. He has worked at Qualcomm and Intel on projects ranging from 32nm to 10nm technology nodes. Sr. Kakarla seeks a challenging role implementing high performance and low power SOC designs.
The curriculum vitae outlines the professional experience and qualifications of Nidhin Joe Kuttikatt, including over 11 years of experience in hardware validation and testing roles working on various projects for companies like Tessolve Semiconductors, NXP, and TI, with a focus on tasks like test planning, equipment operation, automation development, and data analysis. The document also provides details on his educational background, including a Bachelor's degree in electronics and communications engineering and a Master's degree in VLSI design.
Nidhin Joe Kuttikkat is a senior test engineer with over 11 years of experience in post-silicon validation and system-level testing. He has worked extensively on characterization of DC-DC converters, ADCs, and GPS systems at the bench level and in field trials. He is proficient in test automation using LabVIEW and has experience developing test plans and procedures. Previously he worked as an assistant professor teaching electronics.
Madhulatha has over 7 years of experience in information technology, specializing in data warehousing. She is proficient in ETL tools like Datastage and Talend, databases like Oracle and Teradata, and reporting tools like Qlik View. She seeks a challenging role in software development utilizing her skills in programming languages, data analysis and design, and project experience across various domains.
This document provides a summary of an engineering professional's experience including 20 years in vehicle systems and electrical design engineering. Key skills include electrical design, test equipment development, interdisciplinary technical abilities, and business knowledge. Specialized expertise is demonstrated in various communication protocols, sensors, and design/documentation. Professional experience highlights leadership roles managing integration and testing of automotive systems at major automotive suppliers.
The document describes Cisco's Base Environment methodology for digital verification. It aims to standardize the verification process, promote reuse, and improve predictability. The methodology defines a common testbench topology and infrastructure that is vertically scalable from unit to system level and horizontally scalable across projects. It provides templates, scripts, verification IP and documentation to help teams set up verification environments quickly and leverage existing best practices. The standardized approach facilitates extensive code and test reuse and delivers benefits such as faster ramp-up times, improved planning, and higher return on verification IP development.
The document provides a summary and details of Ananth Chellappa's professional experience and qualifications as an analog design engineer. It outlines his 10 years of industry experience at various companies designing analog circuits like PLLs, ADCs, DACs, and switching regulators. It also provides examples of initiatives and innovations he has led at Maxim Integrated to improve designs and processes. Project details are given for some of his work on touchscreen interfaces, battery chargers, and other mixed-signal chips.
Energy management awareness program for decision makersZAINI ABDUL WAHAB
Presentation materials to introduce to decision makers of organizations to trigger the awareness among them with less technical contents and more on commitment required from them
360 degree feedback involves collecting performance feedback on an individual from their manager, peers, direct reports, and other people who interact with them. This feedback is collected through questionnaires that rate things like leadership, communication skills, decision making, and expertise. The feedback is then analyzed and presented back to the individual and their manager. It is used primarily for development purposes like identifying strengths and weaknesses, but some organizations also use it for appraisal, pay, and promotion decisions. Key steps in implementing a 360 degree feedback program include defining objectives, selecting participants, developing the questionnaire, collecting and analyzing data, and providing feedback sessions.
The document provides information about conducting effective performance appraisals. It discusses the objectives of performance appraisals, what should be appraised, and barriers to effective appraisals such as biases. It also outlines the key components of an appraisal, including planning, conducting the discussion, and follow up. Managers are advised to focus discussions on future improvements rather than past performance and document agreed upon goals.
This solution set will assist you in sifting through the mess and understanding the basics of performance appraisal, recognizing the various formal methods that are out there and determining what components you need to build a performance appraisal program that meets the goals of your organization.
The information in this report will provide:
•The benefits and challenges of performance appraisal methods, when to draw from them and how to overcome the limitations of rater biases.
•Advice on the contested use of forced ranking and 360-degree feedback.
•Short term activities that will get you started on effective performance appraisal practices.
Use this knowledge to prepare yourself in order to create an effective performance appraisal program.
The document discusses strategies for conducting a fair performance appraisal of nurses who felt their previous appraisal was unfair. The new appraiser would:
1) Analyze objective and subjective performance data like records and interviews to substantiate any rating changes.
2) Interview staff and the previous appraiser to understand the reasons for grievances like personality clashes or errors in rating.
3) Address any performance issues by determining the root cause such as skills, motivation, or opportunity factors, and taking actions like training, coaching, clarifying expectations.
4) Conduct the re-appraisal with effective communication skills and an understanding of common rater errors to avoid inaccurate assessments. The focus would be on organizational objectives and
Naveen Reddy has over 15 years of experience in semiconductor test engineering. He holds an MS in Computer & Electrical Engineering from Illinois Institute of Technology and a Bachelor's degree in Electronics and Communications from Dayananda Sagar College of Engineering in India. Currently he works as a Principal Test Engineer at Broadcom, where he develops test programs for digital front end and networking chip products. Previously he held test engineering roles at companies including Optichron, Centillium, Integrated Device Technology, and Advantest America.
Dayashankar Srinivasan is a R&D Engineer with over 4 years of experience in FPGA design, RTL coding, verification, and algorithm development. He currently works for Logic-fruit Technologies in Gurgaon/Bangalore and has previously worked for SAMEER CEM, the research division of the Government of India. He has extensive experience with Xilinx FPGAs including the Spartan 6, Virtex 6, and Kintex 7, as well as languages like VHDL, Verilog, C, and MATLAB. His projects include work on LTE communication systems, image processing, TWT systems for DRDO, and OFDM protocols. He has a Master's in VLSI
This document is a resume for Christopher J. Reder. It summarizes his education, work experience, and technical skills. He has a B.S. in Electrical Engineering from Auburn University and over 15 years of experience in software engineering roles developing networking hardware and software. His experience includes work at Cisco Systems, Extreme Networks, Overture Networks, Hatteras Networks, Digital Concepts Inc., and ADTRAN Inc., where he has led projects, mentored other engineers, implemented new features, found and fixed bugs, and interfaced with customers.
Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the modular netlist and test languages (ICL and PDL) to facilitate the description of the components involved in analog tests as well as the content of the tests themselves.
This document summarizes a presentation given at the 3rd Asia Academic Forum in Kuala Lumpur from November 13-15, 2006. The presentation introduces process control systems (PCS) and their importance to Intel's assembly and test operations. It discusses challenges faced by PCS including poor signal detection, data system limitations, and human errors. It outlines Intel's PCS strategy to improve detection and prevention, deliver automation solutions, and build a high performance PCS culture. The presentation shows how PCS has evolved and will continue to advance with new technologies. It proposes areas of joint opportunity between Intel and universities.
The document discusses validation and design in small teams with limited resources. It proposes constraining designs to a single clock rate, using FIFO interfaces between blocks, and separating algorithm from IO verification to simplify validation. This approach allows designs to be completed more quickly with fewer verification engineers through standardized, repeatable validation methods at the cost of optimal performance.
Join us for a presentation on the benefits of using PSpice® in an integrated OrCAD flow. For new users, we’ll cover how to get started and where to find working examples. The next step is where to find specific models and how to create them if they’re not available anywhere. Finally we’ll go deeper into the tool to see how it can help us if we run into trouble by identifying parts that are close to failure.
Combining requirements engineering and testing in agile. SYSQA BV
Agile Testing Days Berlin, november 2012
Projects that use agile have small, multidisciplinary teams. When every discipline has its own specialist in the team, the team becomes bigger and bigger leading to more communication, coordination and more need for documentation. Combining programming and testing is not a wise decision but combining requirements engineering and testing is very well possible. It even turns out that a lot of communication, documentation and coordination is not necessary. So a lot of time and effort can be saved. During his presentation Jan Jaap tells why testers are excellent requirements engineers (and vice versa) and what the advantages of combining requirements engineering and testing can be. He also addresses what testers should do to get this combined role. With agile becoming more and more popular this can be a possible future for testers.
The idea of combining requirements engineering and testing started with a vision. By now we have enough practical experience to show that is actually works! During the presentation Jan Jaap shares vision and practical experiences.
Sr. Kakarla is a physical design engineer with over 6 years of experience in roles including IC physical design, CAD STA, layout design automation, and corporate design solutions. He has worked at Qualcomm and Intel on projects ranging from 32nm to 10nm technology nodes. Sr. Kakarla seeks a challenging role implementing high performance and low power SOC designs.
The curriculum vitae outlines the professional experience and qualifications of Nidhin Joe Kuttikatt, including over 11 years of experience in hardware validation and testing roles working on various projects for companies like Tessolve Semiconductors, NXP, and TI, with a focus on tasks like test planning, equipment operation, automation development, and data analysis. The document also provides details on his educational background, including a Bachelor's degree in electronics and communications engineering and a Master's degree in VLSI design.
Nidhin Joe Kuttikkat is a senior test engineer with over 11 years of experience in post-silicon validation and system-level testing. He has worked extensively on characterization of DC-DC converters, ADCs, and GPS systems at the bench level and in field trials. He is proficient in test automation using LabVIEW and has experience developing test plans and procedures. Previously he worked as an assistant professor teaching electronics.
Madhulatha has over 7 years of experience in information technology, specializing in data warehousing. She is proficient in ETL tools like Datastage and Talend, databases like Oracle and Teradata, and reporting tools like Qlik View. She seeks a challenging role in software development utilizing her skills in programming languages, data analysis and design, and project experience across various domains.
This document provides a summary of an engineering professional's experience including 20 years in vehicle systems and electrical design engineering. Key skills include electrical design, test equipment development, interdisciplinary technical abilities, and business knowledge. Specialized expertise is demonstrated in various communication protocols, sensors, and design/documentation. Professional experience highlights leadership roles managing integration and testing of automotive systems at major automotive suppliers.
The document describes Cisco's Base Environment methodology for digital verification. It aims to standardize the verification process, promote reuse, and improve predictability. The methodology defines a common testbench topology and infrastructure that is vertically scalable from unit to system level and horizontally scalable across projects. It provides templates, scripts, verification IP and documentation to help teams set up verification environments quickly and leverage existing best practices. The standardized approach facilitates extensive code and test reuse and delivers benefits such as faster ramp-up times, improved planning, and higher return on verification IP development.
The document provides a summary and details of Ananth Chellappa's professional experience and qualifications as an analog design engineer. It outlines his 10 years of industry experience at various companies designing analog circuits like PLLs, ADCs, DACs, and switching regulators. It also provides examples of initiatives and innovations he has led at Maxim Integrated to improve designs and processes. Project details are given for some of his work on touchscreen interfaces, battery chargers, and other mixed-signal chips.
Energy management awareness program for decision makersZAINI ABDUL WAHAB
Presentation materials to introduce to decision makers of organizations to trigger the awareness among them with less technical contents and more on commitment required from them
360 degree feedback involves collecting performance feedback on an individual from their manager, peers, direct reports, and other people who interact with them. This feedback is collected through questionnaires that rate things like leadership, communication skills, decision making, and expertise. The feedback is then analyzed and presented back to the individual and their manager. It is used primarily for development purposes like identifying strengths and weaknesses, but some organizations also use it for appraisal, pay, and promotion decisions. Key steps in implementing a 360 degree feedback program include defining objectives, selecting participants, developing the questionnaire, collecting and analyzing data, and providing feedback sessions.
The document provides information about conducting effective performance appraisals. It discusses the objectives of performance appraisals, what should be appraised, and barriers to effective appraisals such as biases. It also outlines the key components of an appraisal, including planning, conducting the discussion, and follow up. Managers are advised to focus discussions on future improvements rather than past performance and document agreed upon goals.
This solution set will assist you in sifting through the mess and understanding the basics of performance appraisal, recognizing the various formal methods that are out there and determining what components you need to build a performance appraisal program that meets the goals of your organization.
The information in this report will provide:
•The benefits and challenges of performance appraisal methods, when to draw from them and how to overcome the limitations of rater biases.
•Advice on the contested use of forced ranking and 360-degree feedback.
•Short term activities that will get you started on effective performance appraisal practices.
Use this knowledge to prepare yourself in order to create an effective performance appraisal program.
The document discusses strategies for conducting a fair performance appraisal of nurses who felt their previous appraisal was unfair. The new appraiser would:
1) Analyze objective and subjective performance data like records and interviews to substantiate any rating changes.
2) Interview staff and the previous appraiser to understand the reasons for grievances like personality clashes or errors in rating.
3) Address any performance issues by determining the root cause such as skills, motivation, or opportunity factors, and taking actions like training, coaching, clarifying expectations.
4) Conduct the re-appraisal with effective communication skills and an understanding of common rater errors to avoid inaccurate assessments. The focus would be on organizational objectives and
Performance Evaluation PowerPoint PPT Content Modern SampleAndrew Schwartz
136 slides include: 4 benefits and 11 additional values of performance appraisals, performance interviews, ground rules for performance evaluation, building performance contracts, developing work plans, setting the stage for a performance appraisal meeting, opening and closing your appraisal session, handling poor performance, conducting a feedback meeting, how to conduct a performance appraisal discussion, how to's and more.
The document discusses various aspects of performance appraisal including definitions, objectives, processes, methods, issues, advantages, and disadvantages. Specifically, it defines performance appraisal as evaluating an employee's job performance and sharing feedback to improve. It lists objectives for both employees and organizations. It outlines the typical performance appraisal process and describes traditional and modern methods like graphic rating scales, forced choice, critical incidents, field review, behavioral anchored rating scales, and 360 degree/MBO approaches. It also notes some common issues and both advantages like motivating employees and disadvantages like potential bias.
Legacy Renewal of Central Framework in the EnterpriseAnatole Tresch
Speak done at GeeCon and other Conferences in 2014 showing an experience report of some of the complexities to be faced when changing commonly used frameworks and runtime components in Credit Suisse and how issues were solved finally.
FlexPod delivers new integrated infrastructure validated designs with NetApp All-Flash and Cisco ACI that deliver new levels of performance and the ability to meet business objectives
SiriusCon2016 - Modelling Spacecraft On-board Software with SiriusObeo
>> These slides were presented at SiriusCon Paris 2016, on November 15th by Andreas Jung (European Space Agency)
The European Space Agency, together with industry, has lead an analysis into the issues faced by spacecraft software developers now and in the future, considering several aspects as for example raising complexity of the software, shorter development life cycles, etc. The analysis resulted in the development of an On-board Software Reference Architecture (OSRA) founded on the principles of component-based software engineering (CBSE) and strong separation of concerns.
A dedicated Domain Specific Language for the component model was developed, called Space Component Model (SCM), to allow the precise definition with clear semantical meaning, in particular considering the domain specific elements like observability and commandability of spacecrafts via Telemetry and Telecommand. The SCM was implemented as a meta-model in ecore. The R&D activity that have developed the OSRA and the SCM have also prototyped a graphical editor to experiment and test the complete approach, from modelling down to code generation for the target.
The original prototype of the graphical editor was based on Eclipse and Obeo Designer, which allowed very quick and simple prototyping of a graphical editor. Following the R&D activities, it was clear that an improved version of the editor, in terms of usability, is needed. An improvement activity has been started with Obeo, using now the open source version of Obeo Designer, namely Sirius. The intention was also to push Obeo's technology further to evaluate it for applicability in a commercial tool.
This talk will give a brief overview of the challenges of spacecraft software development, the needs for a graphical editor, present the results of the improvement activity, show the benefits of the Eclipse and Sirius frameworks and provide an overall evaluation.
This document contains a resume for Allan John R. Salgado. It outlines his professional experience including 12 years of enterprise software development and 7 years of software development leadership experience. It details his technical skills and certifications in Microsoft technologies like .NET, SQL Server, and Oracle. It also lists his educational background and work history at various companies in roles like senior analyst programmer, senior software engineer, and technical analyst.
Migrating Mission-Critical Workloads to Intel ArchitectureIntel IT Center
Based on Intel's RISC/UNIX Migration Planning Guide, this powerpoint can be used to simplify your RISC/UNIX* migration to Intel® Xeon® processor-based solutions running Linux* or Windows* operating systems. You’ll gain practical guidance, including the steps needed to create a solid project plan.
In his report, Orkhan Gasimov (Digital Transformation Architect, Consultant, GlobalLogic, Kyiv) talked to the participants about the willingness of developers to go to Serverless, talked about the new Spring Cloud Function project, and the ability to reuse the code as an http endpoint, a stream handler, or as a cloud serverless function. The report also addressed the features of the Spring Cloud Function and how to use it to improve development performance.
This presentation was delivered at GlobalLogic Kharkiv Java TechTalk #1 on February 5, 2019.
Video: https://youtu.be/WLojSXqCvSE
How CapitalOne Transformed DevTest or Continuous Delivery - AppSphere16AppDynamics
Making the leap to continuous delivery is precarious for any organization, but the concerns are greatly exacerbated when your organization services approximately 45 million bank accounts. Committed to maintaining flawless user experiences while accelerating release cadence, Capital One faced a daunting challenge as it transformed culture, processes, and technical infrastructure in its evolution to continuous delivery.
Join this session with Capital One's Michael Bonamassa and Parasoft's Wayne Airole and learn from their insights on what DevTest changes are critical for responding to extreme digital disruption.
Key takeaways:
o The changing responsibilities of DevTest in a "continuous everything" world
o What skill sets software testers need to ride the wave of digital transformation
o How service virtualization and continuous testing measure the risk of a release candidate
o How to evolve the culture and process to support continuous delivery
o What technical infrastructure is required for real-time test automation and continuous delivery maturation
For more information, go to: www.appdynamics.com
Continuous Delivery series: How to automate your infrastructure toolchainSerena Software
This document summarizes a presentation about automating infrastructure toolchains. It discusses:
1) Moving fast without breaking things in highly regulated large enterprises through speed without risk, end-to-end automation that is practitioner specific, collaboration enabled, and enterprise scaled.
2) The presenter, Darryl Bowler, solutions architect at Serena Software, Inc.
3) The differences between system configuration management versus workflow driven automation, including benefits like idempotency but challenges around complex orchestration and limited collaboration.
Transform Software Testing and Quality with the Neotys-Inflectra PlatformInflectra
On July 17, 2019 Inflectra and Neotys hosted a joint webinar called: Transform Software Testing & Quality with the Neotys-Inflectra Platform. The webinar demonstrated the powerful capabilities of this combined QA and performance testing platform vis-a-vis legacy tools.
The is the presentation used in this webinar.
ESEconf2011 - Hanin Makram: "Embedding Performance into Continuous Integratio...Aberla
The document discusses embedding performance testing into continuous integration processes. It outlines how performance engineering tools can be integrated into development and testing environments to enable continuous performance regression testing. This helps minimize time and effort spent detecting performance regressions caused by code changes later in the development cycle. The document advocates for treating performance testing as a first-class citizen alongside other testing practices in continuous integration workflows.
Faster, more Secure Application Modernization and Replatforming with PKS - Ku...VMware Tanzu
Faster, more Secure Application Modernization and Replatforming with PKS - Kubernetes for the Enterprise - London
Alex Ley
Associate Director, App Transformation, Pivotal EMEA
28th March 2018
This document discusses strategies for modernizing applications and moving workloads to Kubernetes and container platforms like Pivotal Container Service (PKS). It recommends identifying candidate applications using buckets based on factors like programming language, dependencies, and access to source code. It outlines assessing applications' business value and technical quality using Gartner's TIME methodology to prioritize efforts. The document provides an overview of PKS and how it can provide benefits like increased speed, stability, scalability and cost savings. It recommends starting projects by pushing a few applications to production on PKS to measure ROI metrics.
This document discusses strategies for modernizing applications and moving workloads to Kubernetes and container platforms like Pivotal Container Service (PKS). It recommends identifying candidate applications using buckets based on factors like programming language, dependencies, and access to source code. It outlines assessing applications' business value and technical quality using Gartner's TIME methodology to prioritize efforts. The document provides an overview of PKS and how it can provide benefits like increased speed, security, scalability and cost savings. It recommends starting projects by pushing a few applications to production on PKS to measure ROI metrics.
This webinar presented a DevOps platform from Clarive and DBmaestro for continuous delivery of database changes. It discussed challenges with traditional database development and deployment processes. The platform provides coordination, collaboration, integration and automation capabilities to standardize processes across teams and tools. It also offers insights, approvals and release automation to safely deploy database changes.
Oracle EBS R12.2 - The Upgrade Know-How Factorypanayaofficial
For Oracle EBS customers on R12.1 or lower, the upgrade to R12.2 may seem like an inconvenient necessity. However, when coupling Infosys know-how and Panaya's Change Intelligence technology, they can easily turn a necessity into an opportunity.
Planning guide sap business suite 7 2013 landscape implementationLeonardo Parpal Roig
This document provides an overview of planning system landscapes for SAP Business Suite. It defines important terminology used in landscape planning like system, instance, and stack. It describes different types of systems like single stack, dual stack, hub, and sidecar systems. It also explains the methodology used for recommending landscape layouts and system distributions.
A Software Factory Integrating Rational & WebSphere Toolsghodgkinson
The document discusses how a large automotive retailer integrated Rational Software Architect, WebSphere Message Broker, and Rational Team Concert into a software factory to develop an integration layer between a new point of sale system and SAP backend. Key challenges included a multi-vendor global team and parallel development of UI, integration, and backend layers. The software factory employed model-driven development, continuous integration, and practices like architectural modeling in UML, automated WSDL generation, tracking work items and impediments, and collaborative configuration management to help coordinate distributed development and integrate results.
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2. Introducing Performance Awareness in an Integrated Specification Environment 2
Fabian Keller
University of
Stuttgart
D-70569 Stuttgart
Markus Völter
voelter –
Ingenieurbüro für
Softwaretechnologie
D-70327 Stuttgart
André van Hoorn
University of
Stuttgart
D-70569 Stuttgart
Klaus Birken
itemis AG
D-70565 Stuttgart
Hello
3. Building Software with
Performance in Mind
State of the Art
Introducing Performance Awareness in an Integrated Specification Environment 3
4. Introducing Performance Awareness in an Integrated Specification Environment 4
Performance prediction at its finest
Palladio
Becker et al. [2009]
5. Introducing Performance Awareness in an Integrated Specification Environment 5
Or how to ship performant code
Software Performance Engineering
RE
6. Introducing Performance Awareness in an Integrated Specification Environment 5
Or how to ship performant code
Software Performance Engineering
RE
SPL
7. Introducing Performance Awareness in an Integrated Specification Environment 5
Or how to ship performant code
Software Performance Engineering
RE
SPL
SA
8. Introducing Performance Awareness in an Integrated Specification Environment 5
Or how to ship performant code
Software Performance Engineering
RE
SPL
SA
NFR
9. Introducing Performance Awareness in an Integrated Specification Environment 5
Or how to ship performant code
Software Performance Engineering
RE
SPL
SA
NFR
IDE
10. Introducing Performance Awareness in an Integrated Specification Environment 6
Integration of performance awareness in Java EE development
environments
– Chrusciel, 2015 –
Related Work
11. Introducing Performance Awareness in an Integrated Specification Environment 7
In Situ Understanding of Performance Bottlenecks through Visually
Augmented Code – Beck et al., 2013 –
Related Work
13. Straight from the ISE*, not IDE
Performance Awareness
Introducing Performance Awareness in an Integrated Specification Environment 9
* ISE = Integrated Specification
Environment
14. Straight from the ISE*, not IDE
Performance Awareness
Introducing Performance Awareness in an Integrated Specification Environment 9
* ISE = Integrated Specification
Environment
16. • What impact does this decision have on the performance?
• Are all performance requirements fulfilled?
• Are all performance requirements fulfilled for all relevant configurations?
• Having an incomplete configuration, which features yield the best
performance?
• Oh this is interesting, can we have a thorough analysis?
Introducing Performance Awareness in an Integrated Specification Environment 11
Immediate feedback raises performance awareness
Questions
41. • Palladio can provide real-time diagnostics
• Variability analysis in IETS
3
• [Yes] What impact does this decision have on the performance?
• [Yes] Are all performance requirements fulfilled?
• [Yes] Are all performance requirements fulfilled for all relevant
configurations?
• [Not yet] Having an incomplete configuration, which features yield the best
performance?
Results & Conclusion
Introducing Performance Awareness in an Integrated Specification Environment 27
42. • Slide 1: https://commons.wikimedia.org/wiki/File:Fale_F1_Monza_2004_73.jpg
• Slide 4: Becker, Steffen, Heiko Koziolek, and Ralf Reussner. "The Palladio component
model for model-driven performance prediction." Journal of Systems and Software 82.1
(2009): 3-22.
• Slide 5: Doors Screenshot:
https://www.ibm.com/developerworks/mydeveloperworks/blogs/requirementsmanageme
nt/resource/BLOGS_UPLOADED_IMAGES/seg2.jpg
• Slide 5: ArchStudio Screenshot:
http://y.web.umkc.edu/yzheng/img/archfeature/ArchFeature.PNG
• Slide 5: EnterpriseArchitect Screenshot:
http://assets.devx.com/articlefigs/Fig3_DetailedClassDiagrams.jpg
• Slide 5: Palladio Bench Screenshot: http://sdq.ipd.kit.edu/uploads/media/palladio-
bench_3.4_screenshot_01.jpg
• Slide 5: IntelliJ IDEA Screenshot:
https://www.jetbrains.com/idea/img/screenshots/idea_overview_5_1@2x.png
Introducing Performance Awareness in an Integrated Specification Environment 28
Image References