This document describes a research paper on designing a high-speed application-specific integrated circuit (ASIC) for complex number multiplication using concepts from Vedic mathematics. The paper aims to improve multiplication speed by eliminating carry propagation delays. It proposes a design that uses Vedic sutras to transform complex number multiplication into four real number multiplications and three additions. The design is implemented in VHDL or Verilog and synthesized using Xilinx tools. Simulation results show improvements in propagation delay, power consumption, and area compared to other complex multiplier designs.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
High speed multiplier using vedic mathematicseSAT Journals
Abstract
The digital signal processing in today’s time need high speed computation. The basic building block of signal processing in
Communication, Biomedical signal processing, and Image processing remains Fast Fourier Transform (FFT). FFT computation
involves multiplications and additions. Speed of the DSP processor mainly depends on the speed of the multiplier. Time delay, power
dissipation and the silicon chip area. These are the most important parameters for the fast growing technology. The conventional
multiplication method requires more time and area and hence more power dissipation. In this paper an ancient Vedic multiplication
method called “Urdhva Triyakbhyam” is implemented. It is a method based on 16 sutras of Vedic mathematics. Vedic Mathematics
reduces the number of operations to be carried out compared to the conventional method. The code description is simulated and
synthesized using FPGA device Spartan XC3S400-PQ208.
Keywords— Vedic Multiplication, Urdhva Tiryakbhayam , FFT
Kernal based speaker specific feature extraction and its applications in iTau...TELKOMNIKA JOURNAL
Extraction and classification algorithms based on kernel nonlinear features are popular in the new direction of research in machine learning. This research paper considers their practical application in the iTaukei automatic speaker recognition system (ASR) for cross-language speech recognition. Second, nonlinear speaker-specific extraction methods such as kernel principal component analysis (KPCA), kernel independent component analysis (KICA), and kernel linear discriminant analysis (KLDA) are summarized. The conversion effects on subsequent classifications were tested in conjunction with Gaussian mixture modeling (GMM) learning algorithms; in most cases, computations were found to have a beneficial effect on classification performance. Additionally, the best results were achieved by the Kernel linear discriminant analysis (KLDA) algorithm. The performance of the ASR system is evaluated for clear speech to a wide range of speech quality using ATR Japanese C language corpus and self-recorded iTaukei corpus. The ASR efficiency of KLDA, KICA, and KLDA technique for 6 sec of ATR Japanese C language corpus 99.7%, 99.6%, and 99.1% and equal error rate (EER) are 1.95%, 2.31%, and 3.41% respectively. The EER improvement of the KLDA technique-based ASR system compared with KICA and KPCA is 4.25% and 8.51% respectively.
An advancement in the N×N Multiplier Architecture Realization via the Ancient...VIT-AP University
Multiplication is an crucial unfussy, basic
function in arithmetic procedures and Vedic mathematics is a
endowment prearranged for the paramount of human race,
due to the capability it bestows for quicker intellectual
computation. This paper presents the effectiveness of Urdhva
Triyagbhyam Vedic technique for multiplication which cuffs
a distinction in the authentic actual development of
multiplication itself. It facilitates parallel generation of
partial products and eradicates surplus, preventable
multiplication steps. The anticipated N×N Vedic multiplier is
coded in VHDL (Very High Speed Integrated Circuits
Hardware Description Language), synthesized and simulated
using Xilinx ISE Design Suite 13.1. The projected
architecture is a N×N Vedic multiplier whilst the VHDL
coding is done for 128×128 bit multiplication process. The
result shows the efficiency in terms of area employment and
rapidity
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using ...VIT-AP University
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per this proposed architecture, for two 32-bit numbers; the multiplier and multiplicand, each are grouped as 16-bit numbers so that it decomposes into 16×16 multiplication modules. It is also illustrated that the further hierarchical decomposition of 8×8 modules into 4×4 modules and then 2×2 modules will have a significant VHDL coding of for 32x32 bits multiplication and their used FPGA family Virtex 7 low power implementation by Xilinx Synthesis 16.1 tool done. The synthesis results show that the computation time for calculating the product of 32x32 bits is delay 29.256 ns. (11.499ns logic, 11.994ns route) (48.9% logic, 51.1% route).
LATTICE BASED TOOLS IN CRYPTANALYSIS FOR PUBLIC KEY CRYPTOGRAPHY IJNSA Journal
Lattice reduction is a powerful concept for solving diverse problems involving point lattices. Lattice reduction has been successfully utilizing in Number Theory, Linear algebra and Cryptology. Not only the existence of lattice based cryptosystems of hard in nature, but also has vulnerabilities by lattice reduction techniques. In this survey paper, we are focusing on point lattices and then describing an introduction to
the theoretical and practical aspects of lattice reduction. Finally, we describe the applications of lattice reduction in Number theory, Linear algebra.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
High speed multiplier using vedic mathematicseSAT Journals
Abstract
The digital signal processing in today’s time need high speed computation. The basic building block of signal processing in
Communication, Biomedical signal processing, and Image processing remains Fast Fourier Transform (FFT). FFT computation
involves multiplications and additions. Speed of the DSP processor mainly depends on the speed of the multiplier. Time delay, power
dissipation and the silicon chip area. These are the most important parameters for the fast growing technology. The conventional
multiplication method requires more time and area and hence more power dissipation. In this paper an ancient Vedic multiplication
method called “Urdhva Triyakbhyam” is implemented. It is a method based on 16 sutras of Vedic mathematics. Vedic Mathematics
reduces the number of operations to be carried out compared to the conventional method. The code description is simulated and
synthesized using FPGA device Spartan XC3S400-PQ208.
Keywords— Vedic Multiplication, Urdhva Tiryakbhayam , FFT
Kernal based speaker specific feature extraction and its applications in iTau...TELKOMNIKA JOURNAL
Extraction and classification algorithms based on kernel nonlinear features are popular in the new direction of research in machine learning. This research paper considers their practical application in the iTaukei automatic speaker recognition system (ASR) for cross-language speech recognition. Second, nonlinear speaker-specific extraction methods such as kernel principal component analysis (KPCA), kernel independent component analysis (KICA), and kernel linear discriminant analysis (KLDA) are summarized. The conversion effects on subsequent classifications were tested in conjunction with Gaussian mixture modeling (GMM) learning algorithms; in most cases, computations were found to have a beneficial effect on classification performance. Additionally, the best results were achieved by the Kernel linear discriminant analysis (KLDA) algorithm. The performance of the ASR system is evaluated for clear speech to a wide range of speech quality using ATR Japanese C language corpus and self-recorded iTaukei corpus. The ASR efficiency of KLDA, KICA, and KLDA technique for 6 sec of ATR Japanese C language corpus 99.7%, 99.6%, and 99.1% and equal error rate (EER) are 1.95%, 2.31%, and 3.41% respectively. The EER improvement of the KLDA technique-based ASR system compared with KICA and KPCA is 4.25% and 8.51% respectively.
An advancement in the N×N Multiplier Architecture Realization via the Ancient...VIT-AP University
Multiplication is an crucial unfussy, basic
function in arithmetic procedures and Vedic mathematics is a
endowment prearranged for the paramount of human race,
due to the capability it bestows for quicker intellectual
computation. This paper presents the effectiveness of Urdhva
Triyagbhyam Vedic technique for multiplication which cuffs
a distinction in the authentic actual development of
multiplication itself. It facilitates parallel generation of
partial products and eradicates surplus, preventable
multiplication steps. The anticipated N×N Vedic multiplier is
coded in VHDL (Very High Speed Integrated Circuits
Hardware Description Language), synthesized and simulated
using Xilinx ISE Design Suite 13.1. The projected
architecture is a N×N Vedic multiplier whilst the VHDL
coding is done for 128×128 bit multiplication process. The
result shows the efficiency in terms of area employment and
rapidity
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using ...VIT-AP University
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per this proposed architecture, for two 32-bit numbers; the multiplier and multiplicand, each are grouped as 16-bit numbers so that it decomposes into 16×16 multiplication modules. It is also illustrated that the further hierarchical decomposition of 8×8 modules into 4×4 modules and then 2×2 modules will have a significant VHDL coding of for 32x32 bits multiplication and their used FPGA family Virtex 7 low power implementation by Xilinx Synthesis 16.1 tool done. The synthesis results show that the computation time for calculating the product of 32x32 bits is delay 29.256 ns. (11.499ns logic, 11.994ns route) (48.9% logic, 51.1% route).
LATTICE BASED TOOLS IN CRYPTANALYSIS FOR PUBLIC KEY CRYPTOGRAPHY IJNSA Journal
Lattice reduction is a powerful concept for solving diverse problems involving point lattices. Lattice reduction has been successfully utilizing in Number Theory, Linear algebra and Cryptology. Not only the existence of lattice based cryptosystems of hard in nature, but also has vulnerabilities by lattice reduction techniques. In this survey paper, we are focusing on point lattices and then describing an introduction to
the theoretical and practical aspects of lattice reduction. Finally, we describe the applications of lattice reduction in Number theory, Linear algebra.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Analysis of data is an important task in data managements systems. Many mathematical tools are used in data analysis. A new division of data management has appeared in machine learning, linear algebra, an optimal tool to analyse and manipulate the data. Data science is a multi-disciplinary subject that uses scientific methods to process the structured and unstructured data to extract the knowledge by applying suitable algorithms and systems. The strength of linear algebra is ignored by the researchers due to the poor understanding. It powers major areas of Data Science including the hot fields of Natural Language Processing and Computer Vision. The data science enthusiasts finding the programming languages for data science are easy to analyze the big data rather than using mathematical tools like linear algebra. Linear algebra is a must-know subject in data science. It will open up possibilities of working and manipulating data. In this paper, some applications of Linear Algebra in Data Science are explained.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Quality Prediction in Fingerprint CompressionIJTET Journal
A new algorithm for fingerprint compression based on sparse representation is introduced. At first, dictionary is constructed by sparse combination of set of fingerprint patches. Designing dictionaries can be done by either selecting one from a prespecified set or adapting a dictionary to a set of training signals. In this paper, we use K-SVD algorithm to construct dictionary. After computation of dictionary, the image gets quantized, filtered and encoded. The resultant image obtained may be of three qualities: Good, Bad and Ugly (GBU problem). In this paper, we overcome the GBU problem by prediction the quality of image.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A New Model for Credit Approval Problems a Neuro Genetic System with Quantum ...Anderson Pinho
This paper presents a new model for neuro-evolutionary systems. It is a new quantum-inspired evolutionary algorithm with binary-real representation (QIEA-BR) for evolution of a neural network. The proposed model is an extension of the QIEA-R developed for numerical optimization. The Quantum-Inspired Neuro-Evolutionary Computation model (QINEA-BR) is able to completely configure a feed-forward neural network in terms of selecting the relevant input variables, number of neurons in the hidden layer and all existent synaptic weights. QINEA-BR is evaluated in a benchmark problem of financial credit evaluation. The results obtained demonstrate the effectiveness of this new model in comparison with other machine learning and statistical models, providing good accuracy in separating good from bad customers.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
Novel Methods of Generating Self-Invertible Matrix for Hill Cipher Algorithm.CSCJournals
In this paper, methods of generating self-invertible matrix for Hill Cipher algorithm have been proposed. The inverse of the matrix used for encrypting the plaintext does not always exist. So, if the matrix is not invertible, the encrypted text cannot be decrypted. In the self-invertible matrix generation method, the matrix used for the encryption is itself self-invertible. So, at the time of decryption, we need not to find inverse of the matrix. Moreover, this method eliminates the computational complexity involved in finding inverse of the matrix while decryption.
Implementation of Vedic Multiplier in Image Compression Using Discrete Wavele...IJSRD
Fast Multiplication is one of the most momentous parts in any processor speed which progresses the speed of the manoeuvre like in exceptional application processor like Digital signal processor (DSPs). In this paper Implementation of Vedic Multiplier in Image Compression using DWT Algorithm is being in attendance. The DWT is used to crumble the image into different group of images and the research work in this paper represents the effectiveness of Urdhva Triyagbhyam Vedic Method in Image firmness for burgeoning which smacks a difference in authentic process of multiplication itself.A novelVedic multiplier with less number of half adders and Full Addersis proposed in order to overcome such an error. Simulation is done in Matlab2008a and Modelsim10.0b.Synthesis and Implementation is performed by Xilinx 14.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Single Channel Speech De-noising Using Kernel Independent Component Analysis...theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
A Time-Area-Power Efficient High Speed Vedic Mathematics Multiplier using Com...Kumar Goud
Abstract: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
Keywords—4:2 Compressor, 7:2 Compressor, Booth’s multiplier, high speed multiplier, modified Booth’s multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...iosrjce
This paper anticipated the design of a novel Vedic Multiplier using the techniques of Ancient Indian
Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly
on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in
general processors. Currently the speed of the multipliers is limited by the speed of the adders used for partial
product addition. In this paper, we proposed an 8-bit multiplier using the new methodology of Vedic
Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products. The partial
product addition in Vedic multiplier is realized using carry-skip technique. This paper depicts the design of an
efficient 8×8 binary arithmetic multiplier by using Vedic Mathematics. From various multiplication techniques,
Urdhva-Tiryagbhyam sutra is being implemented because this sutra is applicable to all cases of algorithms for
N×N bit numbers and the minimum delay is obtained. A 4×4 Vedic Multiplier is designed using 9 –full adder
and a special 4-bit adder which is having reduced delay. Then 8-bit multiplier is designed using four 4-bit
multiplier and 3-ripple carry adder. Then 8×8 Vedic Multiplier is coded in VHDL, synthesized and simulated
using Xilinx ISE8.2 Software. Finally the objective of this paper lies in design of an efficient vedic multiplier
using Urdhva–Tiryakbhyam Sutra in VHDL Environment.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Analysis of data is an important task in data managements systems. Many mathematical tools are used in data analysis. A new division of data management has appeared in machine learning, linear algebra, an optimal tool to analyse and manipulate the data. Data science is a multi-disciplinary subject that uses scientific methods to process the structured and unstructured data to extract the knowledge by applying suitable algorithms and systems. The strength of linear algebra is ignored by the researchers due to the poor understanding. It powers major areas of Data Science including the hot fields of Natural Language Processing and Computer Vision. The data science enthusiasts finding the programming languages for data science are easy to analyze the big data rather than using mathematical tools like linear algebra. Linear algebra is a must-know subject in data science. It will open up possibilities of working and manipulating data. In this paper, some applications of Linear Algebra in Data Science are explained.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
Quality Prediction in Fingerprint CompressionIJTET Journal
A new algorithm for fingerprint compression based on sparse representation is introduced. At first, dictionary is constructed by sparse combination of set of fingerprint patches. Designing dictionaries can be done by either selecting one from a prespecified set or adapting a dictionary to a set of training signals. In this paper, we use K-SVD algorithm to construct dictionary. After computation of dictionary, the image gets quantized, filtered and encoded. The resultant image obtained may be of three qualities: Good, Bad and Ugly (GBU problem). In this paper, we overcome the GBU problem by prediction the quality of image.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A New Model for Credit Approval Problems a Neuro Genetic System with Quantum ...Anderson Pinho
This paper presents a new model for neuro-evolutionary systems. It is a new quantum-inspired evolutionary algorithm with binary-real representation (QIEA-BR) for evolution of a neural network. The proposed model is an extension of the QIEA-R developed for numerical optimization. The Quantum-Inspired Neuro-Evolutionary Computation model (QINEA-BR) is able to completely configure a feed-forward neural network in terms of selecting the relevant input variables, number of neurons in the hidden layer and all existent synaptic weights. QINEA-BR is evaluated in a benchmark problem of financial credit evaluation. The results obtained demonstrate the effectiveness of this new model in comparison with other machine learning and statistical models, providing good accuracy in separating good from bad customers.
Dynamic Texture Coding using Modified Haar Wavelet with CUDAIJERA Editor
Texture is an image having repetition of patterns. There are two types, static and dynamic texture. Static texture is an image having repetitions of patterns in the spatial domain. Dynamic texture is number of frames having repetitions in spatial and temporal domain. This paper introduces a novel method for dynamic texture coding to achieve higher compression ratio of dynamic texture using 2D-modified Haar wavelet transform. The dynamic texture video contains high redundant parts in spatial and temporal domain. Redundant parts can be removed to achieve high compression ratios with better visual quality. The modified Haar wavelet is used to exploit spatial and temporal correlations amongst the pixels. The YCbCr color model is used to exploit chromatic components as HVS is less sensitive to chrominance. To decrease the time complexity of algorithm parallel programming is done using CUDA (Compute Unified Device Architecture). GPU contains the number of cores as compared to CPU, which is utilized to reduce the time complexity of algorithms.
Novel Methods of Generating Self-Invertible Matrix for Hill Cipher Algorithm.CSCJournals
In this paper, methods of generating self-invertible matrix for Hill Cipher algorithm have been proposed. The inverse of the matrix used for encrypting the plaintext does not always exist. So, if the matrix is not invertible, the encrypted text cannot be decrypted. In the self-invertible matrix generation method, the matrix used for the encryption is itself self-invertible. So, at the time of decryption, we need not to find inverse of the matrix. Moreover, this method eliminates the computational complexity involved in finding inverse of the matrix while decryption.
Implementation of Vedic Multiplier in Image Compression Using Discrete Wavele...IJSRD
Fast Multiplication is one of the most momentous parts in any processor speed which progresses the speed of the manoeuvre like in exceptional application processor like Digital signal processor (DSPs). In this paper Implementation of Vedic Multiplier in Image Compression using DWT Algorithm is being in attendance. The DWT is used to crumble the image into different group of images and the research work in this paper represents the effectiveness of Urdhva Triyagbhyam Vedic Method in Image firmness for burgeoning which smacks a difference in authentic process of multiplication itself.A novelVedic multiplier with less number of half adders and Full Addersis proposed in order to overcome such an error. Simulation is done in Matlab2008a and Modelsim10.0b.Synthesis and Implementation is performed by Xilinx 14.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Single Channel Speech De-noising Using Kernel Independent Component Analysis...theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
A Time-Area-Power Efficient High Speed Vedic Mathematics Multiplier using Com...Kumar Goud
Abstract: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.
Keywords—4:2 Compressor, 7:2 Compressor, Booth’s multiplier, high speed multiplier, modified Booth’s multiplier, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics.
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...iosrjce
This paper anticipated the design of a novel Vedic Multiplier using the techniques of Ancient Indian
Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly
on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in
general processors. Currently the speed of the multipliers is limited by the speed of the adders used for partial
product addition. In this paper, we proposed an 8-bit multiplier using the new methodology of Vedic
Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products. The partial
product addition in Vedic multiplier is realized using carry-skip technique. This paper depicts the design of an
efficient 8×8 binary arithmetic multiplier by using Vedic Mathematics. From various multiplication techniques,
Urdhva-Tiryagbhyam sutra is being implemented because this sutra is applicable to all cases of algorithms for
N×N bit numbers and the minimum delay is obtained. A 4×4 Vedic Multiplier is designed using 9 –full adder
and a special 4-bit adder which is having reduced delay. Then 8-bit multiplier is designed using four 4-bit
multiplier and 3-ripple carry adder. Then 8×8 Vedic Multiplier is coded in VHDL, synthesized and simulated
using Xilinx ISE8.2 Software. Finally the objective of this paper lies in design of an efficient vedic multiplier
using Urdhva–Tiryakbhyam Sutra in VHDL Environment.
Design of Efficient High Speed Vedic Multiplierijsrd.com
Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large.
ALU Using Area Optimized Vedic MultiplierIJERA Editor
The load on general processor is increasing. For Fast Operations it is an extreme importance in Arithmetic Unit. The performance of Arithmetic Unit depends greatly on it multipliers. So, researchers are continuous searching for new approaches and hardware to implement arithmetic operation in huge efficient way in the terms of speed and area. Vedic Mathematics is the old system of mathematics which has a different technique of calculations based on total 16 Sutras. Proposed work has discussion of the quality of Urdhva Triyakbhyam Vedic approach for multiplication which uses different way than actual process of multiplication itself. It allows parallel generation of elements of products also eliminates undesired multiplication steps with zeros and mapped to higher level of bit using Karatsuba technique with processors, the compatibility to various data types. It is been observed that lot of delay is required by the conventional adders which are needed to have the partial products so in the work it is further optimized the Vedic multiplier type Urdhva Triyakbhyam by replacing the traditional adder with Carry save Adder to have more Delay Optimization. The proposed work shows improvement of speed as compare with the traditional designs. After the proposal discussion of the Vedic multiplier in the paper, It is been used for the implementation of Arithmetic unit using proposed efficient Vedic Multiplier it is not only useful for the improve efficiency the arithmetic module of ALU but also it is useful in the area of digital signal processing. The RTL entry of proposed Arithmetic unit done in VHDL it is synthesized and simulated with Xilinx ISE EDA tool. At the last the proposed Arithmetic Unit is validated on a FPGA device Vertex-IV.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FPGA Implementation of High Speed 8bit Vedic Multiplier using Barrel Shifterdbpublications
In today’s world Vedic mathematics has
proved to be the most robust technique for arithmetic
operations. In contrast, conventional techniques for
multiplication provide significant amount of delay in hardware
implementation of n-bit multiplier. Moreover, the
combinational delay of the design degrades the performance
of the multiplier. Hardware-based multiplication mainly
depends upon architecture selection in FPGA or ASIC.
A barrel shifter is a digital circuit that can shift a data word by
a specified number of bits in one clock cycle. It can be
implemented as a sequence of multiplexers (mux.), and in
such an implementation the output of one mux is connected to
the input of the next mux in a way that depends on the shift
distance.
Compare "Urdhva Tiryakbhyam Multiplier" and "Hierarchical Array of Array Mul...ijsrd.com
Multipliers are extensively used in Microprocessors, DSP and Communication applications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. The need of high speed multiplier is increasing as the need of high speed processors are increasing. In this project, comparative study of different multipliers is done for high speed. The project includes two 4x4 bit Vedic Multiplier (VM) "Urdhva Tiryakbhyam multiplier" and "Hierarchical Array of Array Multiplier" of Ancient Indian Vedic Mathematics which are compared in terms of their speed. Urdhva Tiryakbhyam sutra increases the speed of multiplier by reducing the number of iterations then Hierarchical Array of Array Multiplier.
Design of Efficient 4×4 Quaternary Vedic Multiplier Using Current-Mode Multi-...idescitation
Vedic multiplier is based on ancient Indian Vedic mathematics that offers
simpler and hierarchical structure. Multi-valued logic results in the effective utilization of
interconnections, which reduces the chip size and delay. This paper proposes a new design
of 4×4 Vedic multiplier using quaternary current-mode multi-valued logic, equivalent to
iplier has
very low transistor-count and consumes very low power as compared to other multiplier
designs. Since the performance of a digital signal processor depends mainly on the
multipliers used, the proposed approach can greatly enhance the performance of a digital
signal processing system.
ENHANCING MULTIPLIER SPEED IN FAST FOURIER TRANSFORM BASED ON VEDIC MATHEMATICSVLSICS Design
Vedic mathematics is an ancient system of mathematics which has a unique technique of calculations based
on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam
Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms. These algorithms gives
minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier
is designed and compared using these sutras for various NxN bit multiplications and implemented on the
FFT of the DSP processor. Anurupye sutra on FFT is made efficient than Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras by more reduction in computation time. This gives the method for
hierarchical multiplier design. Logic verification of these designs is verified by simulating the logic circuits
in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL coding.
Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Us...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
VLSI ARCHITECTURE OF AN 8-BIT MULTIPLIER USING VEDIC MATHEMATICS IN 180NM TEC...P singh
A Multiplier is one of the key hardware blocks in most fast processing system which requires less power dissipation. A conventional multiplier consumes more power. This paper presents a low power 8 bit Vedic Multiplier (VM) based on Vertically & Crosswise method of Vedic mathematics, a general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. The implementation is done using cadence Virtuoso tool. The power dissipation of 8x8 bit Vedic multiplier obtained after synthesis is compared with conventional multipliers such as Wallace tree and array multipliers and found that the proposed Vedic multiplier circuit seems to have better performance in terms of power dissipation.
Duplicate and Accumulate (MAC) is one of the central practices utilized absolutely in signal-controlling
and different applications. The multiplier is the major piece of Digital Signal Processors (DSPs). Its cutoff spins around power, LUT use, and surrender pick the presence of a DSP. In like way, there is a need to sort out the drive and give up fit multiplier. In this paper, a 16-digit MAC unit is proposed to utilize an 8-cycle Vedic multiplier and pass on a save snake. A relationship with the current 8-cycle Vedic multiplier utilizing Square-Root (SQR) Carryselect snake (CSLA) is introduced. It is isolated and a standard pack multiplier. The whole technique is done in Verilog HDL. Blend and redirections were finished utilizing Xilinx InDesign Suite 14.5. The proposed game plan
accomplishes fundamental improvement in region and suspension. In like manner, an abatement in power around 9.5% is refined.
Design and Implementation of Parallel FIR Filter Using High Speed Vedic Multi...rahulmonikasharma
The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many signal processing and image processing applications. One of the key arithmetic operations in such applications is multiplication which determines the performance of the entire system. Thus the optimization of the multiplier speed and area is a challenge for many processors. This challenge has been successfully overcome by the use of ancient Vedic multiplier. This paper illustrates design and implementation of parallel Finite Impulse Response (FIR) filters using Vedic mathematics based Urdhva Tiryabhyam algorithm. The system is aiming to reduced propagation delay and area of the filter. The proposed system based on Vedic multiplier is compared with that on conventional multiplier on the basis of resources and time required for processing given data. The comparison shows the 36.29% and 15.70% reduction in propagation delay for two-parallel and three-parallel FIR filter using Vedic multiplier as compared to that of conventional multiplier. The architecture is coded in VHDL and synthesized and simulated by using Xilinx Design Suite 13.1 ISE.
Design and testing of systolic array multiplier using fault injecting schemesCSITiaesprime
Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.
Design and testing of systolic array multiplier using fault injecting schemes
Fk3110791084
1. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084
High Speed ASIC Design of Complex Multiplier Using Vedic
Mathematics
M.Nagaraju1, R.Surya Prakash2, B.Vijay Bhaskar3
1
M.Tech Student, Department of ECE, Avanthi’s St.Theressa Institute of Engg & Tech College, Garividi.
2
Assistant professor, Department of ECE, Avanthi’s St.Theressa Institute of Engg & Tech College, Garividi.
3
HOD,Associate professor.Department of ECE, Avanthi’s St.Theressa Institute of Engg &Tech College,
Garividi
.
ABSTRACT:
The main aim of the project is to improve transformation based implementation[2], bit-serial
the speed of the complex multiplier by using vedic multiplication using offset binary and distributed
mathematics. This 'Vedic Mathematics' is the arithmetic [3], the CORDIC (coordinate rotation
name given to the ancient system of mathematics, digital computer) algorithm [4], the quadratic residue
or, to be precise, a unique technique of number system(QRNS)[5],and recently, the redundant
calculations based on simple rules and principles, complex numbersystem (RCNS) [6]. at the expense of
with which any mathematical problem can done three additions as compared to the direct method
with the help of arithmetic, algebra, geometry or implementation. A left to right array [7] for the fast
trigonometry can be solved. Traditionally complex multiplication has been reported in 2005, and the
multiplier provides less speed only, because it does method is not further extended for complex
not use Vedic Mathematics concept. By using multiplication. But, all the above techniques require
'Vedic Mathematics' concept we can skip carry either large overhead for pre/postprocessing or long
propagation delay. The system is based on 16 latency.
Vedic sutras, in which we are using one kind of In algorithmic and structural levels, a lot of
vedic sutra actually word-formulae describing multiplication techniques had been developed to
natural ways of solving a whole range of enhance the effciency of the multiplier; which
mathematical problems.The main design features encounters the reduction of the partial products and/or
of the proposed system are the reconfigurability the methods for their partial products addition, but the
and flexibility. The proposed system is design principle behind multiplication was same in all cases.
using VHDL or Verilog HDL and is implemented Vedic Mathematics is the ancient system of Indian
through Xilinx ISE 9.1i navigator or modelsim6.0 mathematics which has a unique technique of
softwares. calculations based on 16 Sutras (Formulae). "Urdhva-
tiryakbyham" is a Sanskrit word means vertically and
Kewords: Complex Multiplier, Exponent crosswise formula is used for smaller number
Determinant, High Speed Radix Selection Unit, multiplication. "Nihilam Navatascaramam Dasatah"
Vedic Formulas. also a Sanskrit term indicating "all fom 9 and last fom
10", formula is used for large number multiplication
1. INTRODUCTION and subtraction. All these forulas are adopted fom
Complex multiplication is of immense ancient Indian Vedic Mathematics. In this work we
importance in Digital Signal Processing (DSP) and formulate this mathematics for designing the complex
Image Processing (IP). To implement the hardware multiplier architecture in transistor level wit two clear
module of Discrete Fourier Transformation (DFT), goals in mind such as: i) Simplicity and modularity
Discrete Cosine Transforation (DCT), Discrete Sine multiplications for VLSI implementations and ii) The
Transformation (DST) and modem broadband elimination of carry propagation for rapid additions
communications; large numbers of complex and subtractions.
multipliers are required. Complex number Mehta et al. [9] have been proposed a multiplier
multiplication is performed using four real number design using "Urdhva-tiryakbyham" sutras, which
multiplications and two additions/ subtractions. In was adopted fom the Vedas. The formulation using
real number processing, carry needs to be propagated this sutra is similar to the modem array
fom the least signifcant bit (LSB) to the most multiplication, which also indicating the carry
signifcant bit (MSB) when binary partial products are propagation issues. A multiplier design using
added [1]. Therefore, the addition and subtraction afer "Nikhilam Navatascaramam Dasatah" sutras has been
binary multiplications limit the overall speed. Many reported by Tiwari et. al [10] in 2009, but he has not
alterative method had so far been proposed for implemented the hadware module for multiplication.
complex number multiplication [2-7] like algebraic That
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2. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084
Multiplier implementation in the gate level (FPGA) which involve variations in both the metal and
using Vedic Mathematics has already been reported polysilicon layers.
but to the best of our knowledge till date there is no
report on transistor level (ASIC) implementation of ASIC's are usually classified into one of three
such complex multiplier. By employing the Vedic categories: full-custom, semi-custom, and structured.
mathematics, an N bit complex number multiplication
was transformed into four multiplications for real and 3.VEDIC SUTRAS
imaginary terms of the final product. this sutra is used The gifs of the ancient Indian mathematics in
for the multiplication purpose, with less number of the world history of mathematical science are not well
partial products generation, in comparison with array recognized. The contributions of saint and
based multiplication. When compared with existing mathematician in the feld of number theory, 'Sri
methods such as the direct method or the strength Bharati Krsna Thirthaji Maharaja', in the fon of Vedic
reduction technique, our approach resulted not only in Sutras (formulas) [11] are signifcant for calculations.
simplifed arithmetic operations, but also in a regular He had explored the mathematical potentials from
arraylike structure. The multiplier is fully Vedic primers and showed that the mathematical
parameterized, so any confguration of input and operations can be carried out mentally to produce fast
output word-lengths could be elaborated. Transistor answers using the Sutras. In this paper we are
level implementation for perfonance parameters such concentrating on "Urdhva-tiryakbyham", and
as propagation delay, dynamic leakage power and "Nikhilam Navatascaramam Dasatah" formulas and
dynamic switching power consumption calculation of other formulas are beyond the scope of this paper.
the proposed method was calculated by Model sim
using 90 nm standard CMOS technology and "Urdhva-tiryakbyham " Sutra:The meaning of
compared with the other design like distributed. this sutra is "Vertically and crosswise" and it is
applicable to all the multiplication operations. Fig. 1
2. ASIC represents the general multiplication procedure of the
The term 'ASIC' stands for 'application- 4x4 multiplication. This procedure is simply known
specific integrated circuit'. An ASIC is basically an as array multiplication technique [12]. It is an effcient
integrated circuit designed specifically for a special multiplication technique when the multiplier and
purpose or application. Strictly speaking, this also multiplicand lengths are small, but for the larger
implies that an ASIC is built only for one and only length multiplication this technique is not suitable
one customer. An example of an ASIC is an IC because a large amount of carr propagation delays are
designed for a specific line of cellular phones of a involved in these cases. To overcome this problem we
company, whereby no other products can use it are describing Nikhilam sutra for calculating the
except the cell phones belonging to that product line. multiplication of two larger numbers.The remarkable
The opposite of an ASIC is a standard product or system of Vedic maths was rediscovered from ancient
general purpose IC, such as a logic gate or a general Sanskrit texts early last century. The system is based
purpose microcontroller, both of which can be used in on 16 sutras or aphorisms, such as: "by one more than
any electronic application by anybody of the complex the one before" and "all from nine and the last from
values 10". These describe natural processes in the mind and
side from the nature of its application, an ASIC ways of solving a whole range of mathematical
differs from a standard product in the nature of its problems. For example, if we wished to subtract 564
availability. from 1,000 we simply apply the sutra "all from nine
The intellectual property, design database, and and the last from 10". Each figure in 564 is subtracted
deployment of an ASIC is usually controlled by just a from nine and the last figure is subtracted from 10,
single entity or company, which is generally the end- yielding 436.
user of the ASIC too. Thus, an ASIC is proprietary
by nature and not available to the general public. A
standard product, on the other hand, is produced by
the manufacturer for sale to the general
public. Standard products are therefore readily
available for use by anybody for a wider range of
applications. The first ASIC's, known as uncommitted
logic array or ULA's, utilized gate array
technology. Having up to a few thousand gates, they
were customized by varying the mask for metal
interconnections. Thus, the functionality of such a
device can be varied by modifying which nodes in the
This can easily be extended to solve problems such as
circuit are connected and which are not. Later
3,000 minus 467. We simply reduce the first figure in
versions became more generalized, customization of
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3. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084
3,000 by one and then apply the sutra, to get the For the fast multiplication using Nikhilam sutra the
answer 2,533.We have had a lot of fun with this type bases of the multiplicand and the multiplier would be
of sum, particularly when dealing with money same, (here we have considered different base) thus
examples, such as £10 take away £2. 36. Many of the the equation can be rewritten as hardware
children have described how they have challenged implementation of this mathematics is shown in Fig.
their parents to races at home using many of the 2. The architecture can be decomposed into three
Vedic techniques - and won. This particular method main subsections: (i) Radix Selection Unit (RSU) (ii)
can also be expanded into a general method, dealing Exponent
with any subtraction sum.The sutra "vertically and
crosswise" has many uses. One very useful
application is helping children who are having trouble
with their tables above 5x5. For example 7x8. 7 is 3
below the base of 10, and 8 is 2 below the base of 10.
The Block level architecture of RSU is shown in Fig.
3.RSU consists of three main subsections: (i)
Exponent Determinant (ED), (ii) Mean Determinant
(MD) and (iii) Comparator. 'n' number bit from input
X is fed to the ED block. The maximum power of X
is extracted at the output which is again fed to shifter
and the adder block.
The whole approach of Vedic maths is suitable for The second input to the shifter is the (n+1) bit
slow learners, as it is so simple and easy to use.The representation of decimal '1'.If the maximum power
sutra "vertically and crosswise" is often used in long of X from the ED unit is (n-1) then the output of the
multiplication. Suppose we wish to multiply shifter is 2n-1. The adder unit is needed to increment
32 by 44. We multiply vertically 2x4=8. the value of the maximum power of X by '1'. The
Then we multiply crosswise and add the two results: second shifter is needed to generate the value of
3x4+4x2=20, so put down 0 and carry 2. 2".Here n is the incremented value taken from the
Finally we multiply vertically 3x4=12 and add the adder block. The Mean Determinant unit is required
carried 2 =14. Result: 1,408. We can extend this to compute the mean of (2n-1+2n). The Comparator
method to deal with long multiplication of numbers of compares the actual input with the mean value of (2n-
any size. The great advantage of this system is that 1
+2n). If the input is greater than the mean then 2n is
the answer can be obtained in one line and mentally. selected as the required radix. If the input is less than
By the end of Year 8, I would expect all students to the mean then 2n-1 is selected as the radix. The select
be able to do a "3 by 2" long multiplication in their input to the multiplexer block is taken from the output
heads. This gives enormous confidence to the pupils of the comparator.
who lose their fear of numbers.The mathematical
expression for the proposed algorithm is shown
below. Broadly this algorithm is divided into three
parts. (i) Radix Selection Unit (ii) Exponent
Determinant (iii) Multiplier.Consider two n bit
numbers X and Y. kl and k2 are the exponent of X
and Y respectively. X and Y can be represented as:
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4. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084
decrementing and shifter also stops shifting operation.
The output of the decrementer shows the integer part
(exponent) of the number.
B.Exponent Determinant: The hardware
implementation of the exponent determinant is shown
in Fig. 4.The integer part or exponent of the number
from the binary fixed point number can be obtained 4.COMPLUX MULTIPLIER
by the maximum power of the radix. For the nonzero Complex multiplier design by using parallel
input, shifting operation is executed using parallel in adders and subtractors has been designed by Saha[I].
parallel out (PIPO) shift registers. The number of Fig. 5 shows the direct method for implementation of
select lines (in FigA it is denoted as S1, So) of the the complex multiplier design. In this paper complex
PIPO shifter is chosen as per the binary representation multiplier design is done using Vedic Multipliers and
of the number (N-1)IO. 'Shift' pin is assigned in PIPO Vedic subtractors. Multiplication Algorithm The
shifter to check whether the number is to be shifted or Complex multiplier design and its functionality were
not (to initialize the operation 'Shift' pin is initialized discussed in the previous chapters. Now this chapter
to low). A decrementer [13] has been integrated in deals with the simulation and synthesis results of the
this architecture to follow the maximum power of the Complex multiplier. Here Modelsim tool is used in
radix. A sequential searching procedure has been order to simulate the design and checks the
implemented here to search the first 'I' starting from functionality of the design.
the MSB side by using shifting technique. For an N
bit number, the value (N-I)1O is
Above shows the basic steps involved in
implementation. The initial design entry of may be
VHDL, schematic or Boolean expression. The
fed to the input of decrementer. The decrementer is optimization of the Boolean expression will be
decremented based on a control signal which is carried out by considering area or speed. In
generated by the searched result. If the searched bit is technology mapping, the transformation of optimized
'0' then the control signal becomes low then Boolean expression to FPGA logic blocks, that is said
decrementer start decrementing the input values. The to be as Slices. Here area and delay optimization will
searched bit is used as a controller of the decrementer. be taken place. During placement the algorithms are
When the searched bit is 'I' then the control signal used to place each block in FPGA array. Assigning
becomes high and the decrementer stops further the FPGA wire segments, which are programmable,
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5. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084
to establish connections among FPGA blocks through A comparison between different architecture in terms
routing. The configuration of final chip is made in of propagation delay and dynamic switching power
programming unit. consumption arithmetic, parallel adder based
implementation, and algebraic transformation based
implementation. Once the functional verification is
done, the design will be taken to the Xilinx tool for
Synthesis process and the netlist file generation.
The Appropriate test cases have been identified in
order to test this modelled Complex multiplier design.
Based on the identified values, the simulation results
which describes the operation of the Complex
multiplier design has been achieved. This proves that
the modelled design works properly as per the
process.
Simulations Results:
RTL Schematic: The RTL (Register Transfer Logic) Partial products Generators:
can be viewed as black box after synthesize of design
is made. It shows the inputs and outputs of the
system. By double-clicking on the diagram we can
see gates, flip-flops and MUX.
Figure :Simulation results for Partial product
generator
Booth Encoder:
5. SIMULATION RESULT ANALYSIS
All the algorithm of this paper was simulated
and their functionality was examined by using Spice
Spectre. Performance parameters such as propagation
delay and power consumptions analysis of this paper
using standard 90nm CMOS technology. To evaluate
the performance parameters, we give the values of the
computational effort using array multiplier and Vedic
multiplier. As shown, the application of the Vedic
method for multiplication cuts the amount of the
hardware as well as increases the performance
parameters such as propagation delay, dynamic Figure :Simulation results for Booth Encoder
switching power consumptions, and dynamic leakage
power consumptions. The performance parameters
analysis using array multiplication and Vedic
multiplication is shown in Table I. Input data is taken
as a regular fashion for experimental purpose. We
have kept our main concentration for reducing the
propagation delay, dynamic switching power and
dynamic leakage power consumption and energy
delay product.
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6. M.Nagaraju, R.Surya Prakash, B.Vijay Bhaskar / International Journal of Engineering
Research and Applications (IJERA) ISSN: 2248-9622
www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1079-1084
Simulation results for Complex Multiplier : process, the device utilization in the used device and
package is shown above.
Timing Summary:Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: 28.239ns
Maximum output required time after clock: 4.283ns
Maximum combinational path delay: No path found
7.CONCLUSION
In this paper we report on a novel complex
number multiplier design based on the formulas of the
ancient Indian Vedic Mathematics, highly suitable for
6.SYNTHESIS RESULT high speed complex arithmetic circuits which are
The developed Complex multiplier design is
having wide application in VLSI signal processing.
simulated and verified their functionality. Once the
The implementation was done in Spice spectre and
functional verification is done, the RTL model is
compared with the mostly used architecture like
taken to the synthesis process using the Xilinx ISE
distributed.The developed Complex Multiplier design
tool. In synthesis process, the RTL model will be
is modelled and is simulated using the Modelsim
converted to the gate level netlist mapped to a
tool.The simulation results are discussed by
specific technology library. This Complex multiplier
considering different cases.The RTL model is
design can be synthesized on the family of Spartan
synthesized using the Xilinx tool in Spartan 3E and
3E.Here in this Spartan 3E family, many different
their synthesis results were discussed with the help of
devices were available in the Xilinx ISE tool. In order
generated reports.
to synthesis this design the device named as
“XC3S500E” has been chosen and the package as
8.REFERENCES
“FG320” with the device speed such as “-4”. The
1. P. K. Saha, A. Banerjee, and A. Dandapat,
design of Reversible Watermarking Algorithm is "High Speed Low Power Complex
synthesized and its results were analyzed as follows.
Multiplier Design Using Parallel Adders and
Device utilization summary: Subtractors," International Journal on
Electronic and Electrical Engineering,
(/EEE), vol 07, no. II, pp 38-46, Dec. 2009.
2. R. E. Blahut, Fast Algorithms for Digital
Signal Processing, Reading, MA: Addison-
Wesley, 1987.
3. S. He, and M. Torkelson, "A pipelined bit-
serial complex multiplier using distributed
arithmetic," in proceedings IEEE
International Symposium on Circuits and
Systems, Seattle, WA, April 30-May-03,
1995,pp. 2313-2316.
4. J. E. VoIder, "The CORDIC trigonometric
computing technique," IRE Trans. Electron.
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330-334, Sept. 1959.
5. R. Krishnan, G. A. Jullien, and W. C. Miller,
This device utilization includes the following. "Complex digital
Logic Utilization
Logic Distribution
Total Gate count for the Design
The device utilization summery is shown
above in which its gives the details of number of
devices used from the available devices and also
represented in %. Hence as the result of the synthesis
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