This document describes an FPGA CEP (complex event processing) appliance that can analyze streaming data and events in real-time with ultra-low latency. The appliance provides sub-microsecond latency, high throughput of over 1 million events per second, and low power consumption. It is useful for applications that require fast real-time decision making based on relationships between different data streams, such as high-frequency trading, network monitoring, and sensor data analysis. The appliance achieves its performance through the parallelism and lack of overhead provided by implementing the processing pipeline directly in an FPGA.

1. ULTRA LOW LATENCY
COMPLEX EVENT
PROCESSING
FPGA CEP Appliance
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

2. When may you need CEP?
¨ Different types of related events happening across
systems and these events need to be
¤ captured
¤ analysed online and
¤ decision made (control actions taken) based on the
analysis outcome in real time
¨ Examples of events
¤ Trade and market data
¤ Emergency alarms
¤ Traffic data
¤ Car sensor events etc.
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

3. Application Examples
¨ Finance
¤ HF / LL Trading
¤ Algorithmic Trading
¤ Real Time Indicators (VWAP, PnL, Deltas etc.) and Risk
Management
¨ Networking
¤ Usage Monitoring
¤ Statistics
¨ Telecommunications
¨ Telematics © Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

4. Why is FPGA CEP Appliance useful?
¨ 1-digit usec wire-to-wire latency – real time event
processing and instantaneous decision making
¨ 1 million events/second throughput per appliance
¨ Low power consumption (< 50W)
¨ Small form factor (12 appliances per rack unit)
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

5. Why is it faster than software?
¨ Ethernet packets processed at wire speed
¨ Critical operations are natively parallelized, e.g.
no synchronization locks
¨ No overhead on data transferring through the
processing pipeline
¤ E.g. between different HW components in CPU / GPU
based systems
¤ No interruptions / context switching
¨ Super scalar ALU to evaluate user expressions
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

6. Uncompromising
Performance
¨ Quick time to market for new applications and their
high performance are now both achievable, without
compromise
¨ IDE with a visual editor for model building and data
flow definition
¨ Scale out by cascading appliances
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

7. High Level System Overview
FPGA
CEP Engine
Adapter
(CSV, FIX, FAST,…)
Source
Systems
IDE
(GUI, XML)
Configuration
Data Input
Data
Output Target
Systems
*Other adapters can be implemented in FPGA after feasibility analysis
DDR3
RAM
Ethernet
Ethernet
Ethernet
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

8. Real World Example : Daily VWAP
¨ Schema
¨ Chip : Arria IIGX
¨ Wire-to-wire latency : 1.1 usec
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

9. FPGA CEP Appliance: Key Features
¨ CEP Platform for processing and analyzing data
streams with 1-digit usec wire-to-wire latency
¨ 1 million events/second throughput per appliance
¨ Scale out by cascading appliances
¨ Join, Union, Filter, Aggregate, Event Pattern Matching
operations and user expressions
¨ IDE for the data flow definition and configuring the
appliance
¨ Less than 50W power consumption and compact form
factor © Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

10. Roadmap
¨ .csv and FIX parsing in FPGA
¨ Web GUI to create/manage data flow schema
visually (with support for iOS and Android devices)
¨ Monitoring and error reporting
¨ Hardware upgrade to reduce latency by 1.5 times
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com

11. Sounds interesting?
¨ Contact us at cep.appliance@gmail.com
¨ Visit us at http://www.cepappliance.com
© Dmitry Kapustin & Alexey Savin
http://www.cepappliance.com