Formal verification refers to mathematical techniques for specifying, designing, and verifying software and hardware systems. It involves proving or disproving the correctness of algorithms in a system with respect to a formal specification or property using formal methods of mathematics. Formal verification techniques include manual proofs, semi-automatic theorem proving, and automatic algorithms that take a model and property to determine if the model satisfies the property. Formal verification is commonly used for safety-critical systems like embedded systems to help ensure correctness. Tools like VC formal, VC LP, and Spyglass can be used to formally verify designs early in development without complex test benches or stimulus.

1. Formal verification
Presented To:
Ma'am Maria Latif
Presented By:
Toseef Aslam

2. What is formal Methods
• Formal methods refers to mathematical based
techniques and tools for
1. Specification
2. Design
3. Verification
of software and hardware systems.

3. What is formal verification
• In the context of hardware and software
systems, formal verification is the act of proving
or disproving the correctness of intended
algorithms underlying a system with respect to a
certain formal specification or property, using
formal methods of mathematics.

4. Continue …………
• Formal verification is the act of
proving or disproving the
correctness of a system with
respect to a certain formal
specification or property.

5. Formal Verification Techniques
Techniques
Manual human tries to produce a proof of
correctness
semi-automatic theorem proving
Automatic algorithm takes a model (program)
and a property; decides whether the
model satisfies the property

6. ApplicationDomainsof FormalVerification
• Generally safety-critical systems: a system whose
failure can cause death, injury, or big financial
loses.
• particularly embedded systems
1. often safety critical
2. reasonably small and thus amenable to formal
verification

7. Tools for formal verification
1. VC formal
2. VC LP
3. Spyglass
VC forma, VC LP and Spyglass combine to enable designers
and verification engineers to quickly analyze and check RTL
designs very early in the design flow, with no need for
complex setup, test benches or stimulus.