This paper investigates the effect of process variations on unity gain frequency (ft) in 30 nm gate length FinFET by performing extensive TCAD simulations. Six different geometrical parameters, channel doping, source/drain doping and gate electrode work function are studied for their sensitivity on ft
. It is found that ft is more sensitive to gate length, underlap, gate-oxide thickness, channel and Source/Drain doping and less sensitive to source/drain width and length, and work function variations. Statistical modelling has been performed for ft through design of experiment with respect to sensitive parameters. The model has been validated through a comparison between random set of experimental data simulations and predicted values obtained from the model.
Compact Power Divider Integrated with Coupler and Microstrip Cavity Filter fo...TELKOMNIKA JOURNAL
This document summarizes the design and simulation of an integrated compact power divider module for an X-band surveillance radar system. The module integrates a 2-way power divider, directional coupler, and microstrip cavity bandpass filter into a single compact form to reduce losses from connectors. A 10-pole microstrip cavity filter was designed with a 432.9 MHz bandwidth. A Wilkinson power divider was designed with better than -28 dB return loss. A directional coupler was designed with -34.31 dB coupling and -26.74 dB isolation. Simulation results showed the integrated module had good performance with minimal losses and a compact size suitable for use in the radar system.
This document analyzes and compares two types of MuGFET transistors: BULK and DTMOS. BULK transistors have three gates (FinFETs), while DTMOS transistors are modified BULK transistors where the gate and silicon substrate are short circuited. The study analyzes electrical characterization data from Imec to compare the characteristics, advantages, and disadvantages of BULK versus DTMOS transistors. Results show that DTMOS transistors generally have around 15% higher drain current but are limited to lower gate voltages. Drain current increases with wider channel widths for BULK transistors up to a point, after which wider transistors perform like single-gate planar devices.
Design of Low-Pass Digital Differentiators Based on B-splinesCSCJournals
This paper describes a new method for designing low-pass differentiators that could be widely suitable for low-frequency signals with different sampling rates. The method is based on the differential property of convolution and the derivatives of B-spline bias functions. The first order differentiator is just constructed by the first derivative of the B-spline of degree 5 or 4. A high (>2) order low-pass differentiator is constructed by cascading two low order differentiators, of which the coefficients are obtained from the nth derivative of a B-spline of degree n+2 expanded by factor a. In this paper, the properties of the proposed differentiators were presented. In addition, we gave the examples of designing the first to sixth order differentiators, and several simulations, including the effects of the factor a on the results and the anti-noise capability of the proposed differentiators. These properties analysis and simulations indicate that the proposed differentiator can be applied to a wide range of low-frequency signals, and the trade-off between noise- reduction and signal preservation can be made by selecting the maximum allowable value of a.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Investigation of outdoor path loss models for wireless communication in bhujIAEME Publication
This document discusses and compares several empirical path loss models that can be used for wireless communication, including free space path loss model, Okumura-Hata model, Walfisch-Ikegami model, and ECC-33 model. It presents the equations and parameters for each model. Measurements of path loss were taken in Bhuj, India across various distances and environments and compared to the predicted values from each model. The results showed that the ECC-33 and Okumura-Hata models had the closest predictions to the measured path loss values in Bhuj's diverse terrain.
MINIATURIZATION OF BRANCH-LINE COUPLERS USING OPEN STUBS AND STEPPED IMPEDANC...csijjournal
The document summarizes two proposed structures for compact branch-line couplers (BLCs) using miniaturization techniques. The first structure uses open stubs and meandering transmission lines, reducing the area to 61.8% of a conventional design. The second uses open stub and stepped impedance unit cells, reducing the area to 50.8%. Simulation results show the first structure achieves return losses and isolation of -27.8 dB and -27.9 dB respectively with a 312 MHz bandwidth. The second structure achieves comparable performance to previously published measured results. Both miniaturized designs achieve good size reduction while maintaining BLC performance compared to a conventional design.
Adaptive transmit diversity selection (atds) based on stbc and sfbc fir 2 x1 ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document summarizes a research paper that evaluates the performance of different MIMO techniques for MIMO-OFDM systems. It describes spatial multiplexing (SM), space time block coding (STBC), and a hybrid model combining SM and STBC. A simulation model of a 4x4 antenna hybrid MIMO-OFDM system is developed. Results show the hybrid system provides lower bit error rates than SM or STBC systems alone, improving both data rate and link reliability for wireless communication.
Compact Power Divider Integrated with Coupler and Microstrip Cavity Filter fo...TELKOMNIKA JOURNAL
This document summarizes the design and simulation of an integrated compact power divider module for an X-band surveillance radar system. The module integrates a 2-way power divider, directional coupler, and microstrip cavity bandpass filter into a single compact form to reduce losses from connectors. A 10-pole microstrip cavity filter was designed with a 432.9 MHz bandwidth. A Wilkinson power divider was designed with better than -28 dB return loss. A directional coupler was designed with -34.31 dB coupling and -26.74 dB isolation. Simulation results showed the integrated module had good performance with minimal losses and a compact size suitable for use in the radar system.
This document analyzes and compares two types of MuGFET transistors: BULK and DTMOS. BULK transistors have three gates (FinFETs), while DTMOS transistors are modified BULK transistors where the gate and silicon substrate are short circuited. The study analyzes electrical characterization data from Imec to compare the characteristics, advantages, and disadvantages of BULK versus DTMOS transistors. Results show that DTMOS transistors generally have around 15% higher drain current but are limited to lower gate voltages. Drain current increases with wider channel widths for BULK transistors up to a point, after which wider transistors perform like single-gate planar devices.
Design of Low-Pass Digital Differentiators Based on B-splinesCSCJournals
This paper describes a new method for designing low-pass differentiators that could be widely suitable for low-frequency signals with different sampling rates. The method is based on the differential property of convolution and the derivatives of B-spline bias functions. The first order differentiator is just constructed by the first derivative of the B-spline of degree 5 or 4. A high (>2) order low-pass differentiator is constructed by cascading two low order differentiators, of which the coefficients are obtained from the nth derivative of a B-spline of degree n+2 expanded by factor a. In this paper, the properties of the proposed differentiators were presented. In addition, we gave the examples of designing the first to sixth order differentiators, and several simulations, including the effects of the factor a on the results and the anti-noise capability of the proposed differentiators. These properties analysis and simulations indicate that the proposed differentiator can be applied to a wide range of low-frequency signals, and the trade-off between noise- reduction and signal preservation can be made by selecting the maximum allowable value of a.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Investigation of outdoor path loss models for wireless communication in bhujIAEME Publication
This document discusses and compares several empirical path loss models that can be used for wireless communication, including free space path loss model, Okumura-Hata model, Walfisch-Ikegami model, and ECC-33 model. It presents the equations and parameters for each model. Measurements of path loss were taken in Bhuj, India across various distances and environments and compared to the predicted values from each model. The results showed that the ECC-33 and Okumura-Hata models had the closest predictions to the measured path loss values in Bhuj's diverse terrain.
MINIATURIZATION OF BRANCH-LINE COUPLERS USING OPEN STUBS AND STEPPED IMPEDANC...csijjournal
The document summarizes two proposed structures for compact branch-line couplers (BLCs) using miniaturization techniques. The first structure uses open stubs and meandering transmission lines, reducing the area to 61.8% of a conventional design. The second uses open stub and stepped impedance unit cells, reducing the area to 50.8%. Simulation results show the first structure achieves return losses and isolation of -27.8 dB and -27.9 dB respectively with a 312 MHz bandwidth. The second structure achieves comparable performance to previously published measured results. Both miniaturized designs achieve good size reduction while maintaining BLC performance compared to a conventional design.
Adaptive transmit diversity selection (atds) based on stbc and sfbc fir 2 x1 ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document summarizes a research paper that evaluates the performance of different MIMO techniques for MIMO-OFDM systems. It describes spatial multiplexing (SM), space time block coding (STBC), and a hybrid model combining SM and STBC. A simulation model of a 4x4 antenna hybrid MIMO-OFDM system is developed. Results show the hybrid system provides lower bit error rates than SM or STBC systems alone, improving both data rate and link reliability for wireless communication.
In metallurgy, cladding refers to the bonding together of dissimilar metals, normally achieved by extruding two or more metals through a die or pressing sheets together under high pressure. Timely detection of delamination that occurs occasionally during the cladding processes is very important for the industry. This paper presents an EMAT system based on ultrasonic guided wave techniques. The analysis of a three-layer, brass/copper/brass product is also presented including dispersion curves, and interaction of ultrasonic guided wave with delamination defects. The authors observed a cyclic behavior of guided wave propagation with the increase of defect size. An explanation is introduced and proved with finite element analysis. The results presented in this paper will have a very significant impact on understanding of delamination detection in multilayered composite structures including adhesive bonded structures.
This document compares several propagation path loss models - Okumura, Hata, ECC 33, Cost-231, and SUI - by estimating path losses and signal strengths at 950 MHz in urban, suburban, and rural areas. Path losses are estimated using each model and compared to measured practical data from those environments. The results show that the Hata model most closely matches the practical data across all three environments. Therefore, the Hata model is concluded to be the most suitable for predicting signal strength in urban, suburban, and rural areas.
This document discusses full dimension MIMO (FD-MIMO) technology for LTE-Advanced and 5G networks. It provides an overview of 3GPP activities related to FD-MIMO, including the recently completed 3D channel model, ongoing studies of FD-MIMO scenarios and antenna architectures. FD-MIMO uses a base station with a 2D active antenna array to support multi-user beamforming in both the elevation and azimuth dimensions, resulting in significantly higher cell capacity compared to conventional systems. The document also discusses challenges of reducing channel state information feedback overhead for large FD-MIMO systems.
Multi carrier equalization by restoration of redundanc y (merry) for adaptive...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The
performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed
DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated
and less complexity also involved by the simulation of the DST-DMT system.
Austenitic welds are extensively used in nuclear, petrochemical and process industries. Due to the strong material anisotropy and coarse grain size in the dendritic weld zone, they are difficult to inspect with ultrasound. In this regard, the shear horizontal (SH) wave mode is far superior to the more conventional shear vertical (SV) and longitudinal wave modes. In this paper, an electromagnetic acoustic transducer (EMAT) is designed and used for the inspection of two austenitic weld samples. Despite the low efficiency of EMAT generation due to low conductivity of austenitic stainless steel material and strong attenuation in the weld zone, good signal to noise ratio is achieved with optimized EMAT probes and state-of-the-art instrumentation. The angle beam EMAT probe successfully detected all defects in the samples with good signal to noise ratio including a 2% defect.
The capability of detection a defect across a 2’’ inch thick and 2’’ wide austenitic weld zone is also demonstrated in the paper.
AN ANALYTICAL ANALYSIS OF PATH LOSS MODELS FOR MOBILE CELLULAR WIRELESS COMMU...IJCI JOURNAL
The paper deals with the study based on the comparative analysis of radio propagation models for mobile cellular wireless communication of global system for mobile at frequencies 0.9 GHz and 1.8 GHz, respectively. The path loss propagation models are vital tool for planning the wireless network as well as
designed to predict path loss in a meticulous environment. Various propagation models: Free-space model, CCIR (ITU-R) model, Hata model, Ericson model, and Stanford University Interim (SUI) model have been studied and examined through analytically from the base station (BS) to mobile station (MS)
and vice versa followed by respective simulation performance evaluation by using Matlab simulator. The observed data is collected at the operating frequency of 0.9 GHz from various environments (high density region and low density region) using the spectrum analyzer and path loss comparison is shown for
different model.
Path loss modeling of mobile radio communication in urban areasNguyen Minh Thu
This document presents a numerical path loss model for mobile radio communication in urban areas using the Uniform Theory of Diffraction (UTD). The model considers various propagation paths around buildings and compares computed results at 2.154GHz and 835MHz to existing models, finding excellent agreement. Computed losses are shown to decrease with lower frequency and increase with distance from the base station, while changing in complex ways with mobile position due to multipath effects. The model provides a simple and reliable way to predict path losses in both line-of-sight and non-line-of-sight environments.
Fpga implementation of low complexity linear periodically time varying filterIAEME Publication
This document summarizes a research paper that proposes a low complexity architecture for implementing linear periodically time-varying (LPTV) filters using field programmable gate arrays (FPGAs). The architecture is based on representing an LPTV filter as a multi-input multi-output (MIMO) system of linear time-invariant (LTI) filters. It divides the input signal into blocks and processes them in parallel using LTI filters, reducing the effective input sampling rate. A single multiplier can be shared among the LTI filters. Each LTI filter is realized using multiplier-less multiplication structures based on binary common bit patterns to reduce complexity. The proposed architecture is simulated, synthesized and implemented on an FPGA to
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
This document summarizes a simulation study on the physical scaling limits of FinFET structures. It analyzes the scaling limits of double gate underlap and triple gate overlap FinFET structures using 2D and 3D computer simulations. Key findings include:
1) For double gate FinFETs, DIBL and SS increase abruptly when the ratio of gate length to fin thickness (L/Tfin) goes below 1.5, limiting scaling.
2) For triple gate FinFETs, both fin thickness and height can control short channel effects, but fin thickness is found to be a more dominant parameter. DIBL and SS increase as the ratio of effective gate length to fin thickness (Leff/Tfin) decreases
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However,
as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
IMPACT OF DEVICE PARAMETERS OF TRIPLE GATE SOI-FINFET ON THE PERFORMANCE OF C...VLSICS Design
This document summarizes a simulation-based study of the impact of device parameters on the performance of 22nm triple gate SOI FinFETs. Device parameters like fin width, fin height, and gate oxide thickness were varied and their effects on short channel effects, on-current, off-current, and gate leakage current were analyzed. It was found that increasing fin width and height improved on-current but also increased off-current and short channel effects. Reducing fin thickness lowered off-current, while reducing fin height decreased gate leakage. The performance and static power of a CMOS inverter built using the FinFETs was also evaluated.
Simulation of DIBL effect in junctionless SOI MOSFETs with extended gateMahkam Xalilloyev
Short channel effects such as DIBL are compared for trigate SOI Junctionless MOSFET with extended and nonextended
lateral part of the gate.
A trigate SOI JLMOSFET with gate length Lgate, a silicon body width Wtin and thickness of 10 nm are simulated. In order to calculate the
DIBL, the transfer characteristics of JLMOSFETs was simulated at a donor concentration of 5 1019 cm 3 in the silicon body. The equivalent
oxide thicknesses of the HfO2 gate insulator used in simulation was 0.55 nm. Simulation result showed the DIBL for the trigate JLMOSFET
depended on the length of the lateral part of the gate Lext. DIBL is high for devices with gates having extended lateral parts. This is a result
of parasitic source (drain)gate
capacitance coupling which is higher for longer Lext.
Multiple gate field effect transistors foreSAT Journals
This document provides a review of multiple gate field-effect transistors (MuGFETs), also known as FinFETs, as promising candidates to enable continued CMOS scaling. It discusses the motivation for multigate transistors due to short channel effects. It then summarizes the evolution of FinFET technologies, including variants like omega-gate and pi-gate FinFETs. Fabrication techniques like resist-defined fin and spacer-defined fin patterning are briefly outlined. Performance metrics like mobility, saturation velocity, transconductance and voltage gain are compared between FinFETs and planar MOSFETs based on measurements. FinFETs show lower resistance but higher voltage gain due to lower output conductance.
Effects of downscaling channel dimensions on electrical characteristics of In...IJECEIAES
In this paper, we present the impact of downscaling of nano-channel dimensions of Indium Arsenide Fin Feld Effect Transistor (InAs- FinFET) on electrical characteristics of the transistor, in particular; (i) ION/IOFF ratio, (ii) Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to simulate and compare the considered characteristics based on variable channel dimensions: length, width and oxide thickness. The results demonstrate that the best performance of InAs- FinFET was achieved with channel length = 25 nm, width= 5 nm, and oxide thickness between 1.5 to 2.5 nm according to the selected scaling factor (K = 0.125).
Wideband Branch Line Coupler with Open Circuit Coupled Lines IJECEIAES
This paper focuses on the design of a Wideband Branch Line Coupler by using open circuits coupled lines technique. The design is implemented by adding four open circuits coupled lines to the structure of the Conventional Branch Line Coupler. The proposed design of Wideband Branch Line C 3 z -3 orts. The prototype is fabricated and measured to validate the simulated results. A similar Wide Bandwidth is observed on simulation and measurement. The structure achieved a fractional bandwidth of 42.63%, and return loss of 21 dB compared to the Conventional Branch Line Coupler (BLC).
A Survey on Architectural Modifications for Improving Performances of Devices...IRJET Journal
This document summarizes research on improving the performance of FinFET devices through architectural modifications. FinFETs are promising replacements for bulk CMOS beyond the 22nm node due to their ability to better control short channel effects. Various techniques are discussed to enhance FinFET performance in terms of power, speed, and area. These include optimizing the fin geometry, gate work functions, strain engineering, and reducing parasitic capacitance. FinFETs also show improvements in noise reduction, scalability, and applications such as SRAM cells compared to planar CMOS devices. Overall, the document reviews how FinFET design modifications can help address challenges in continued device scaling for low power applications.
Electrical characterization of si nanowire GAA-TFET based on dimensions downs...IJECEIAES
This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (V T ). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.
Review of Fin FET Technology and Circuit Design Challengesrbl87
1. FinFET technology uses a fin-like gate structure to improve gate control and reduce leakage compared to planar CMOS. It allows continued transistor scaling beyond limits of planar devices.
2. There are manufacturing challenges for FinFETs including fin patterning and variability, doping, stress application, and parasitic capacitance. Circuit design challenges include adapting SRAM cells and EDA tools to the 3D FinFET structure.
3. FinFETs are now used for high performance logic but new materials and design approaches are still being explored to further improve FinFET technology and address remaining challenges in manufacturing and circuit design.
Review of Fin FET Technology and Circuit Design ChallengesIJERA Editor
Considering the difficulties in planar CMOS transistor scaling to secure an acceptable gate to channel control
FinFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the
existing technology. The desirability of FinFET that it’s operation principle is same as CMOS process. This
permits to lengthening the gate scaling beyond the planar transistor limits, sustaining a steep subthreshold slope,
better performance with bias voltage scaling and good matching due to low doping concentration in the channel.
There are, still, several challenges and limitations that FinFET technology has to face to be competitive with
other technology options: Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as
device parasitic, performance and patterning approaches will be discussed.
This document summarizes the numerical study of a triangular coplanar circulator using a ferrite film for application at X-band frequency. Simulation results showed an insertion loss of -0.46 dB and isolation of -29.88 dB was achieved at an operating frequency of 10.6 GHz after optimizing the structure dimensions. The triangular structure with a ground plane provided non-reciprocal transmission between ports. Parameters like the signal line width and spacing, ground plane radius, and ferrite linewidth were analyzed to understand their impact on circulator performance. Compared to prior work, the proposed triangular design demonstrated lower losses and better isolation.
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
Segmentation of Overlapped and Touching Human Chromosome imagesIOSR Journals
This document describes the design and analysis of a 4-bit Johnson counter using 16nm FinFET technology. It first discusses the advantages of FinFET over conventional CMOS for reducing short channel effects at small scales. It then presents the structure and manufacturing process of FinFET. A single-edge triggered D flip-flop using 9 FinFET transistors is proposed for use in the Johnson counter. The 4-bit Johnson counter is implemented by connecting 4 of these D flip-flops in a ring configuration. Simulation results show the waveforms of the D flip-flop and Johnson counter operating at 500MHz with 0.85V power supply. Compared to a conventional flip-flop-based counter, the proposed FinFET Johnson
In metallurgy, cladding refers to the bonding together of dissimilar metals, normally achieved by extruding two or more metals through a die or pressing sheets together under high pressure. Timely detection of delamination that occurs occasionally during the cladding processes is very important for the industry. This paper presents an EMAT system based on ultrasonic guided wave techniques. The analysis of a three-layer, brass/copper/brass product is also presented including dispersion curves, and interaction of ultrasonic guided wave with delamination defects. The authors observed a cyclic behavior of guided wave propagation with the increase of defect size. An explanation is introduced and proved with finite element analysis. The results presented in this paper will have a very significant impact on understanding of delamination detection in multilayered composite structures including adhesive bonded structures.
This document compares several propagation path loss models - Okumura, Hata, ECC 33, Cost-231, and SUI - by estimating path losses and signal strengths at 950 MHz in urban, suburban, and rural areas. Path losses are estimated using each model and compared to measured practical data from those environments. The results show that the Hata model most closely matches the practical data across all three environments. Therefore, the Hata model is concluded to be the most suitable for predicting signal strength in urban, suburban, and rural areas.
This document discusses full dimension MIMO (FD-MIMO) technology for LTE-Advanced and 5G networks. It provides an overview of 3GPP activities related to FD-MIMO, including the recently completed 3D channel model, ongoing studies of FD-MIMO scenarios and antenna architectures. FD-MIMO uses a base station with a 2D active antenna array to support multi-user beamforming in both the elevation and azimuth dimensions, resulting in significantly higher cell capacity compared to conventional systems. The document also discusses challenges of reducing channel state information feedback overhead for large FD-MIMO systems.
Multi carrier equalization by restoration of redundanc y (merry) for adaptive...IJNSA Journal
This paper proposes a new blind adaptive channel shortening approach for multi-carrier systems. The
performance of the discrete Fourier transform-DMT (DFT-DMT) system is investigated with the proposed
DST-DMT system over the standard carrier serving area (CSA) loop1. Enhanced bit rates demonstrated
and less complexity also involved by the simulation of the DST-DMT system.
Austenitic welds are extensively used in nuclear, petrochemical and process industries. Due to the strong material anisotropy and coarse grain size in the dendritic weld zone, they are difficult to inspect with ultrasound. In this regard, the shear horizontal (SH) wave mode is far superior to the more conventional shear vertical (SV) and longitudinal wave modes. In this paper, an electromagnetic acoustic transducer (EMAT) is designed and used for the inspection of two austenitic weld samples. Despite the low efficiency of EMAT generation due to low conductivity of austenitic stainless steel material and strong attenuation in the weld zone, good signal to noise ratio is achieved with optimized EMAT probes and state-of-the-art instrumentation. The angle beam EMAT probe successfully detected all defects in the samples with good signal to noise ratio including a 2% defect.
The capability of detection a defect across a 2’’ inch thick and 2’’ wide austenitic weld zone is also demonstrated in the paper.
AN ANALYTICAL ANALYSIS OF PATH LOSS MODELS FOR MOBILE CELLULAR WIRELESS COMMU...IJCI JOURNAL
The paper deals with the study based on the comparative analysis of radio propagation models for mobile cellular wireless communication of global system for mobile at frequencies 0.9 GHz and 1.8 GHz, respectively. The path loss propagation models are vital tool for planning the wireless network as well as
designed to predict path loss in a meticulous environment. Various propagation models: Free-space model, CCIR (ITU-R) model, Hata model, Ericson model, and Stanford University Interim (SUI) model have been studied and examined through analytically from the base station (BS) to mobile station (MS)
and vice versa followed by respective simulation performance evaluation by using Matlab simulator. The observed data is collected at the operating frequency of 0.9 GHz from various environments (high density region and low density region) using the spectrum analyzer and path loss comparison is shown for
different model.
Path loss modeling of mobile radio communication in urban areasNguyen Minh Thu
This document presents a numerical path loss model for mobile radio communication in urban areas using the Uniform Theory of Diffraction (UTD). The model considers various propagation paths around buildings and compares computed results at 2.154GHz and 835MHz to existing models, finding excellent agreement. Computed losses are shown to decrease with lower frequency and increase with distance from the base station, while changing in complex ways with mobile position due to multipath effects. The model provides a simple and reliable way to predict path losses in both line-of-sight and non-line-of-sight environments.
Fpga implementation of low complexity linear periodically time varying filterIAEME Publication
This document summarizes a research paper that proposes a low complexity architecture for implementing linear periodically time-varying (LPTV) filters using field programmable gate arrays (FPGAs). The architecture is based on representing an LPTV filter as a multi-input multi-output (MIMO) system of linear time-invariant (LTI) filters. It divides the input signal into blocks and processes them in parallel using LTI filters, reducing the effective input sampling rate. A single multiplier can be shared among the LTI filters. Each LTI filter is realized using multiplier-less multiplication structures based on binary common bit patterns to reduce complexity. The proposed architecture is simulated, synthesized and implemented on an FPGA to
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
This document summarizes a simulation study on the physical scaling limits of FinFET structures. It analyzes the scaling limits of double gate underlap and triple gate overlap FinFET structures using 2D and 3D computer simulations. Key findings include:
1) For double gate FinFETs, DIBL and SS increase abruptly when the ratio of gate length to fin thickness (L/Tfin) goes below 1.5, limiting scaling.
2) For triple gate FinFETs, both fin thickness and height can control short channel effects, but fin thickness is found to be a more dominant parameter. DIBL and SS increase as the ratio of effective gate length to fin thickness (Leff/Tfin) decreases
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However,
as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
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Statistical Modelling of ft to Process Parameters in 30 NM Gate Length Finfets
1. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
DOI : 10.5121/vlsic.2010.1304 36
STATISTICAL MODELLING OF ft TO PROCESS
PARAMETERS IN
30 NM GATE LENGTH FINFETS
B. Lakshmi and R. Srinivasan
Department of Information Technology
SSN College of Engineering, Kalavakkam – 603 110, Chennai, India
laxmi.balu@yahoo.com
srinivasanr@ssn.edu.in
ABSTRACT
This paper investigates the effect of process variations on unity gain frequency (ft) in 30 nm gate length
FinFET by performing extensive TCAD simulations. Six different geometrical parameters, channel
doping, source/drain doping and gate electrode work function are studied for their sensitivity on ft. It is
found that ft is more sensitive to gate length, underlap, gate-oxide thickness, channel and Source/Drain
doping and less sensitive to source/drain width and length, and work function variations. Statistical
modelling has been performed for ft through design of experiment with respect to sensitive parameters.
The model has been validated through a comparison between random set of experimental data simulations
and predicted values obtained from the model.
KEYWORDS
ft , FinFET, process variations, Statistical modelling, Design of Experiments
1. INTRODUCTION
The progress in CMOS technology has made it well suited for RF and microwave operations at
high level of integration [1], and the continuous improvement of the device performance has
made it a contender for low-power and, eventually, low-cost radio front end. In the area of multi-
gate transistors, double-gate FinFETs are considered a serious contender for channel scaling [2],
[3] because of their quasi-planar structure and the compatibility with CMOS. Several authors
have already studied the low field mobility in fins of various widths [4]-[6]. RF performance of
FinFETs is reported in [7], [8].
Unity gain frequency (ft) is one of the important metric in RF applications. ft is defined as the
frequency at which the current gain of the device becomes unity. ft is calculated by
)
1
(
C
2
g
f
gg
m
t
π
=
where Cgg is the combination of Cgs, Cgd, overlap capacitance and any other fringing capacitance.
In this article, nine different geometrical parameters related to FinFET are varied to capture their
sensitivity on ft.
This paper analyzes double-gate FinFETs as a downscaling option for CMOS technology from
an RF perspective. The effect of various structural and doping parameters (9 parameters in total)
on ft is studied and the five most sensitive parameters are identified. Using these sensitive
parameters a 5 point DOE (design of experiments) is designed and the simulations are done. i.e.
this work is based on design and simulation of the nominal device, design of experiment and
running of the experiment, extraction of results, fitting the response surfaces (models) and
testing of the models. We have modelled ft in terms of the most sensitive parameters like gate
2. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
37
length, underlap, gate oxide thickness, channel and source/drain doping. The model that describe
these quantities have an approximated form [9] as,
)
2
(
x
x
b
x
x
b
x
x
b
x
x
b
x
x
b
x
x
b
x
x
b
x
x
b
x
x
b
x
x
b
x
b
x
b
x
b
x
b
x
b
x
b
x
b
x
b
x
b
x
b
b
y
5
4
45
5
3
35
4
3
34
5
2
25
4
2
24
3
2
23
5
1
15
4
1
14
3
1
13
2
1
12
2
5
55
2
4
44
2
3
33
2
2
22
2
1
11
5
5
4
4
3
3
2
2
1
1
0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
=
where x1 is the gate length, x2 is the underlap, x3 is the gate oxide thickness, x4 is the channel
doping and x5 is the Source/Drain doping, y is the unity gain frequency, b’s are the fitting
parameters determined by the data obtained from the experiment. Next section deals with the
simulation methodology followed in this paper. Section III discusses the simulation results and
statistical modelling. Finally section IV provides conclusions.
2. SIMULATION METHODOOGY
Sentaurus TCAD simulator from Synopsys [10] is used to perform all the simulations. This
simulator has many modules and the following are used in this study.
• Sentaurus structure editor (SDE): To create the device structure, to define doping, to
define contacts, and to generate mesh for device simulation
• Sentaurus device simulator (SDEVICE): To perform all DC and AC simulations
• Inspect and Tecplot: To view the results.
The physics section of SDEVICE includes the appropriate models for band to band tunnelling,
quantization of inversion layer charge, doping dependency of mobility, effect of high and normal
electric fields on mobility, and velocity saturation. The structure generated from SDE is shown
in Fig 1. Doping and mesh information can also be observed in Fig. 1. Figure 2 shows the
schematic diagram of the device. Totally nine different parameters are considered in this study.
Out of them, six are geometrical parameters - gate length (Lg), underlap (Lun), fin width (W),
source/drain width (SW), source/drain length (SL), and Tox and these are shown in Fig. 2. Other
three parameters are channel doping (Nch), source/drain doping (NSD) and gate electrode work
function (WF). The various process parameters considered in this study and their range are given
in Table. 1. Table 1 also gives the dimensions of the nominal device. Standard AC simulations
are done in SDEVICE and ft is extracted from these results. ft is the frequency at which
|Y21/Y11| equals one, and it strongly depends on the gate bias. At various gate biases ft is
calculated and the maximum of them is taken as ft. Supply voltage (Vdd) used in this study is 0.8
V.
Figure 1. Structure of the Dual-Gate FinFET
3. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
38
Figure 2. Schematic view of Dual-Gate FinFET
Table 1. Characteristics of the device
Process parameter Nominal value Range
Gate length (Lg) 30 nm 20 nm to 40 nm
Underlap (Lun) 3 nm 1 nm to 8 nm
Fin Width (W) 4 nm 2 nm to 7 nm
Source Length (SL) 15 nm 10 nm to 20 nm
Source Width (SW) 8 nm 4 nm to 16 nm
Channel Doping (Nch) 1x1016
/cm3
1x1015
/cm3
to
1x1019
/cm3
Source Drain Doping
(NSD)
1x1020
/cm3
1x1018
/cm3
to
2x20
/cm3
Oxide Thickness (Tox) 1 nm 0.5 nm to 2 nm
Gate Work Function
(WF)
4.337 eV 4.13 eV to 4.9 eV
4. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
39
3. RESULTS AND DISCUSSION
3.1 Sensitivity Analysis of Process Parameters
The nine different process parameters are varied one at a time, according to the range
given in Table 1 and their sensitivity to ft is analysed in this section.
3.1.1 Variation in Gate Length
Figure 3 shows the variation of ft against Lg. It can be observed from Fig. 3 that ft initially
increases and then decreases. As per (1), ft is decided by both gm and Cgg. While gm degrades
with Lg, Cgg shows a different behaviour i.e. initially decreases with Lg and then increases (Fig
4).The initial decrease of Cgg can be attributed to the reduction of Cgd [11]. At some point, Cgs
starts dominating and calls for the increase in Cgg. The combined behaviour of gm and Cgg
contributes to the variation of ft w.r.t. Lg.
Figure 3. Variation of ft with respect to Lg
Figure 4. Variation of Cgs with respect to Lg
5. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
40
3.1.2. Variation in Underlap
Figure 5 depicts the plot between ft and Lun. It can be seen from Fig 5 that ft initially increases
and then decreases w.r.t. Lun. Increasing Lun reduces the fringing capacitance, and thereby
decreases Cgg [12], [13].The Cgg in DGMOS can be expressed as
( ) )
3
(
fringing
ov
si
ox
gg C
||
C
||
C
,
C
Series
C =
where Cox is the oxide capacitance, Csi is the silicon body capacitance, Cov is the gate to
source/drain overlap capacitance and Cfringing is the fringing capacitance and is given by
)
4
(
e
T
L
W
ln
WK
C ox
T
un
L
ox
T
un
L
2
ox
2
un
di
fringing
+
−
−
+
π
π
∈
=
When Lun increases current degrades and thereby gm monotonically decreases. The combined
behavior of gm and Cgg is responsible for the ft trend seen in Fig. 5.
Figure 5.Variation of ft with respect to Lun
3.1.3 .Variation in Fin Width
When W is varied we may either face volume inversion or may not, depending upon the channel
doping levels. When the channel doping is 1x1016
/cm3
volume inversion is not seen [14].
Therefore, the increase in W increases current and thereby gm and ft. Figure 6 shows this kind of
behaviour between ft and W. For the channel doping around 1.5x1018
/cm3
, volume inversion
effect is seen which causes ft to decrease initially and then to increase w.r.t W. This is depicted
in Fig. 7.
6. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
41
Figure 6. Variation of ft w.r.t W without volume inversion
Figure 7. Variation of ft w.r.t W with volume inversion
3.1.4. Variation in Source Length
Figure 8 shows the ft versus source length plot. Increasing source length increases the parasitic
resistance associated with the channel and degrades gm which in turn decreases ft.
Figure 8. Variation of ft with respect to SL
7. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
42
3.1.5 .Variation in Source Width
Figure 9 shows ft as a function of source width. It can be noticed from Fig. 9 that ft is almost
independent of SW.
Figure 9. Variation of ft with respect to SW
3.1.6 .Variation in Oxide Thickness
Figure 10 shows the variation of ft with Tox. ft increases initially w.r..t Tox. Both gm and Cgg
together control ft. Cgg always decreases when Tox increases whereas gm may go down or high
depending on whether we are driven by short channel effects or not. The combined effect of gm
and Cgg decides ft behaviour with respect to Tox.
Figure 10. Variation of ft with respect to Tox
3.1.7 .Variation in Channel Doping
Figure 11 shows the variation of ft against Nch. Threshold voltage of DGFET/FinFET is
insensitive up to 1x1017
/cm3
[15]. From which it can be reasoned out that ft is also insensitive at
lower channel doping levels. The same is seen in Fig. 11. At higher doping levels, ft decreases
due to gm degradation.
8. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
43
Figure 11. Variation of ft with respect to Nch.
3.1.8 .Variation in Source/drain Doping
Figure 12 shows the variation of ft with source/drain doping. When NSD increases Ion and gm
increase due to the lowered parasitic series resistance values, and thereby ft increases. This is
reflected in Fig.12
Figure 12. Variation of ft with respect to NSD
3.1.9 .Variation in Work Function
High frequency characteristics are less sensitive to work function variation [16]. Therefore, ft is
expected to be indifferent to gate electrode work function. Figure 13 shows ft versus gate work
function plot and it can be noticed that ft exhibits a flat behaviour w.r.t work function.
9. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
44
Figure 13. Variation of ft with respect to WF
3.2 Statistical modelling:
The sensitive parameters are chosen as Lg, Lun, Tox, Nch and NSD. These sensitive parameters are
made to undergo a variability study with the help of design of experiments. The range of these
sensitive parameters for the variability study is given in Table 2 which results in 2500
simulations. The model that has been obtained by the regression technique is generated with the
help of SPSS [17].The regression coefficients for the second order polynomial of the process
parameters are shown in Table 3.
Table 2 .Range of Sensitive Parameters
Process parameters Range Points in the range
Gate length (Lg) 20 nm to 40 nm 20, 25, 30, 35 and 40 (nm)
Underlap (Lun) 1nm to 9 nm 1,3, 5,7 and 9 (nm)
Oxide Thickness (Tox) 0.5 nm to 2.2 nm 0.5, 1,1.2,2 and 2.2 (nm)
Channel Doping (Nch) 1X1016
/cm3
to 1X1019
/cm3
1X1016
, 1X1017
, 1X1018
and
1X1019
(/cm3
)
Source Drain Doping (NSD) 5X1018
/cm3
to 2X1020
/cm3
5X1018
, 5X1019
, 9.5X1019
,
1.1X1020
and 2X1020
(/cm3
)
10. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.3, September 2010
45
Table 3. Process parameters along with their corresponding
regression coefficients
Factor Coefficient Factor values
Constant bo 2.765E12
Lg b1 -1.103E20
Lun b2 -3.964E19
Tox b3 4.007E19
Nch b4 -.052
NSD b5 .009
Lg
2
b11 1.164E27
Lun
2
b22 -4.210E27
Tox
2
b33 -3.564E28
Nch
2
b44 9.698E-16
NSD
2
b55 -1.489E-17
LgLun b12 1.874E27
LgTox b13 1.639E27
LgNch b14 1266894.540
LgNSD b15 -100967.539
LunTox b23 7.137E27
LunNch b24 -3105744.884
LunNSD b25 -124191.069
ToxNch b34 -1672454.265
ToxNSD b35 23534.568
NchNSD b45 -4.254E-17
In order to study the statistical nature of the device output with respect to sensitive parameters,
we have generated 35
(=243) uniformly distributed pseudo-random numbers for each of these
sensitive parameters and ft values are predicted from the generated model. For the same set of
random numbers generated, TCAD simulations are carried out and the ft values are extracted. To
have a correlation plot TCAD values are plotted against model values and the same is depicted
in Fig. 14. The correlation coefficient is found out as r=0.992.
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46
Fig. 14: Correlation plot between TCAD simulated data and model
predicted data for ft. Correlation coefficient r is depicted here
4. CONCLUSION
Six geometrical parameters (Lg, Lun, W, SW, SL, and Tox), and three non-geometrical parameters
(Nch, NSD, and WF) have been varied over a range and their effect on ft have been studied
through TCAD simulations. It was found that Lg, Lun, Tox, Nch and NSD are more sensitive
parameters whereas gate electrode work function, source/drain length and width are less
sensitive parameters. By running DOE using the sensitive parameters in TCAD, statistical
modelling has been performed. Correlation coefficient around 0.992 was got while running the
simulations with random set of values for sensitive parameters.
ACKNOWLEDGEMENT
This work is supported by Department of Science & Technology, Government of India under
SERC scheme
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