Exercises, Quizzes on workshop on Advances in Verification methodologies conducted at BMS College of Engineering

1. Language constructs ­ Data types, Arrays and Queues
1) What is difference between a logic and bit data type? What will following code display?
logic abc;
bit ​def​;
abc ​=​ ​'​x;
​def​ ​=​ abc;
$display​("​abc​=%​h ​def​=%​h​",​ abc​,​ ​def​);
2) Write a subroutine that can read data from an SRAM for a given address ?
a) Assume s synchronous SRAM. Drive read enable and read address on a clock
edge and sample the data once cycle later. (Assume SRAM read return data
with a one cycle latency).
b) Will you use a task or function ?
c) What arguments will you need ?
3) Is it legal to call a function from inside a task?
task task1​()​ ;
endtask
​function​ f1​();
task1​();
endfunction
4) What will be the value of a and c in following enumerated type?
​enum​ ​{​a​,​ b​=​7​,​ c​}​ alphabet;
5) What will following code print ? Concept: Understanding difference between == and ===
operators
logic​[​2​:​0​]​ abc​,​ ​def;
logic eq2​,​ eq3;
abc​=​ ​3​'​b01x;
​def​=​ ​3​'​b01x​;
eq2 ​=​ ​(​abc​==​def​);
eq3 ​=​ ​(​abc​===​def​);
$display​("​eq2​=%​b eq1​=%​b​",​ eq2​,​ eq1​);
6) What is wrong in following code ?
​int​ A​[​9​:​0​];
​int​ B​[​21​:​0​];
A ​=​ B​;

2. 7) Which of following are true with respect to arrays?
a) Dynamic arrays are useful for contiguous collection of variables whose number
keeps varying
b) Associative arrays can be used when size of an array is not known as it can be built
as key/value pairs
c) Dynamic arrays can be resized after size is allocated once
d) All of above
8) Which of the following implementation using a systemverilog queue will give you a FIFO
implementation?
a) Use push_front() to put an entry in queue and use pop_front() to get entry from
queue
b) Use push_back() to put an entry in queue and use pop_front() to get entry from
queue
c) Use push_back() to put an entry in queue and use pop_back() to get entry from
queue
9) Identify which of following are packed and which are unpacked arrays?
a) logic status[31:0]
b) reg[31:0] registers[128];
c) Integer data [8][32]
10) Write SystemVerilog code for following operations
a) Create a dynamic array of integers
b) Initialize the array to 10 integers with value 0 to 9
c) Use array methods to randomize the order of array
d) Print the array contents
e) Now use array methods to sort in ascending order
f) Print the array contents

3. Threads and Interprocess communication
1) In following code ­ what happens to threads A() and B() if C() finishes first ?
fork
A​();
B​();
C​();
join_any
2) Analyze following code and answer following:
a) How many concurrent process will this code spawn?
b) If task4() finishes first, how many child processes will be disabled by the
“disable fork” ?
fork
task1​();
​begin
task2​();
task3​();
​end
​begin
task4​();
​end
join_any
disable fork;
3) How many concurrent processes will be generated by code?
fork
for​ ​(​int​ i​=​0​;​ i ​<​ ​10​;​ i​++​ ​)​ ​begin
ABC​();
end
join
4) Which of the following are true with respect to comparing a queue and a mailbox?
a) A mailbox is just a queue with no real difference
b) A queue supports adding, removing or modifying any entry in the queue at any
given time while a mailbox can only be accessed at head of it
c) A mailbox size can be bounded while a queue has no limits in size
5) What is difference between get() and peek() methods in mailbox?
6) What is an event data type and what are its uses ?

4.
SystemVerilog classes
1) What is the difference between a local, protected and public data member of a
SystemVerilog class?
2) Does following code illustrate class inheritance of composition ?
​class​ A;
endclass
​class​ B;
A a1;
​function​ ​new​();
a1 ​=​ ​new​();
endfunction
endclass
3) Which of the following is True ?
a) A base class pointer can be used to reference an object of derived class type.
b) A derived class pointer can be used to reference an object of base class type.
4) What is a virtual method in SystemVerilog class and what is the use?
5) What is the need of “super” keyword in SystemVerilog class and when it will be used?
Randomization and Constraints
1) How can we change the constraint behavior defined in a base class using class
inheritance?
2)

5.
Lab Exercises:
1) Simulate a few examples to understand concepts of ​associative arrays and queues
a) Create a simple associative array of integers indexed with a string
b) Add 3 entries to the associative array
c) Print the full associative array contents using assoc array methods
2) Simulate a few examples to understand concepts of ​class definition, objects
a) Create a simple packet class with following data members ­ a 32 bit source and
destination address, a dynamic array of data bytes and a 32 bit CRC field
b) Create some sample methods to print the class contents, set the data bytes to a
random size with random values
c) Create a test module and create 10 instances of above packet and call the print
method to display contents of packet
3) Simulate a few examples to understand concept of ​class inheritance
a) Continue from above exercise
b) Derive an error packet class from packet class defined in previous exercise with
a new data member as “bit error”
​Class ErrPacket;
c) In the test module, create an instance of derived packet
d) Declare a base class pointer and assign the derived class object to base class
pointer
e) What happens when you try to access the data member “error” using base class
pointer ?
4) Simulate an example to understand concept of ​virtual methods
a) Use a reference code where a base class and a derived class has a virtual
method and a non­virtual method
b) Simulate and understand which of the methods gets called when referencing
each object using different pointers
5) Simulate a few examples to understand constraints and randomization
[TBD]
6) Fork.. join / join_any / join_none example

6.
References:
1) Download a copy of Language Reference Manual (LRM) ­
http://standards.ieee.org/getieee/1800/download/1800­2012.pdf
2) A useful online Quick reference guide ­ Easily indexable
​http://svref.renerta.com/
3) Online courses ­ ​http://verificationexcellence.in/online­courses/
4) Books ­ Good reference
a) SystemVerilog for Verification ­ Chris Spear
b) Verilog and SystemVerilog Gotchas ­ Stuart Sutherland
5) Interview focussed book ­ ​Cracking Digital VLSI Verification Interviews: Interview
Success
a) Available on amazon ​http://www.amazon.in/gp/product/B01CZ0Z08E
6) Reference SystemVerilog examples available on GitHub
​https://github.com/VerificationExcellence/SystemVerilogReference
7) Several other papers, tutorials etc available
a) See list here ​http://verificationexcellence.in/course­resources/general/

7.
Day 1 ­ Morning ( 9 ­ 11)
1) Introduction to SV ­ 10 mins
2) Building blocks ­ 30 mins
modules, programs, subroutines, package, interface)
Show with example code
3) Language constructs ­ Data types, Arrays ­ 50 mins
Net/variables, 2 vs 4 valued, integer, user defined types
operators
Loop and flow controls
packed vs unpacked arrays
Dynamic and Assoc arrays
Queues and Lists
4) Exercise/Quiz/Q&A ­ 30 mins
Day 1 ­ Morning (11.15 to 12.30)
1) Threads and Inter process communication
Sequential vs concurrent blocks, fork..join ,
Mailboxes, Semaphores and events ­ 60 mins
2) Exercise / Quiz/ Q&A ­ 15 mins
Day 1 ­ After noon (2­4)
1) System Verilog Classes (90 mins)
Inheritance, Composition, Polymorphism
Class definition , Objects, virtual methods
Abstract class , Parameterized class
typedef class/forward declaration
Example usages of Classes
2) Exercise / Q&A / ­ 30 mins
Day 2 ­ Morning (9 ­ 11)
1) Interfaces and Virtual Interfaces ­ 15 mins
2) Randomization and Constraints ­ 60 minutes
urandom, rand vs randc
constraint operators, implication, loop/array constraints
dist constraints, Inline constraints
Enable/disable/overriding constraints
Examples

8.
3) Exercise on constraints ­ 30 minutes
Day 2 ­ Morning (11.15 to 12.30)
1) Building Test bench components
2) Layered Test bench and concepts
3) Exercise / Q &A
Day 2 ­ Afternoon (2­4)
1) Lab
1) Exercise to demonstrate and understand some concepts on assoc arrays, queues
2) Exercise to demonstrate and understand concepts on class inheritance, virtual methods
3) Exercise to demonstrate some class randomization and constraints