miol

1. E D G E T R I G G E R E D R S F L I P F L O P
SEQUENTIAL LOGIC

2. EDGE TRIGGERED RS FLIP FLOP
• In the case of Flip flops (RS) that we already had discussed, the o/p Q
changes immediately when there is a change in the i/p (R, S).
• Gated or clocked FFs, o/p changes when the clock is enabled(EN) or
High(1).
• All the digital systems operates in synchronous mode also.
• If any of these FFs, are used in the Synchronous system, care must be
taken to ensure that all FF i/p change state in synchronism with the clock
(C).
• These lead to the development of edge triggered flip

3. POSITIVE EDGE TRIGGERED RS FLIP FLOP
• In the positive edge triggered FF, Clock
(C) is applied to a positive pulse forming
circuit.
• Then these positive pulses (positive
trigger, PT) are applied to a gated RS FF.
• The small triangle in the symbol indicates
that Q can change state only with
PT(positive trigger) of the clock.
• Each PT of the clock is very narrow (25
ns) and is applied to the AND gates.
• The AND gates are active only while PT
is high and thus Q can change state only
during this short period, ie; Q is in
synchronism with the PTs of the clock.

4. POSITIVE EDGE TRIGGERED RS FLIP FLOP
CLK R S Qn+1 Action
↑ 0 0 Qn No change
↑ 0 1 1 SET
↑ 1 0 0 RESET
↑ 1 1 ? Forbidden
TRUTH TABLE

5. +VE EDGE TRIGGERED RS FLIP FLOP-O/P WAVE FORMS
• At time t0 S=0
R=0 no change in Q
(Q remains 0)
• At time t1 S=1 R=0
Q changes to 1 from 0
• At time t2 S=0 R=1
Q resets to 0
• At time t3 S=1 R=0
Q sets to 1
• At time t4 S=0 R=0
No changes in Q (remains 1)
(previous o/p)

6. NEGATIVE EDGE TRIGGERED RS FLIP FLOP
• Here Q changes state according
to R & S inputs but only
during NTs of the clock.
• Symbol has a small bubble.
• The FF behaves exactly same as
that of PT RS FF except that
changes in o/p Q are
synchronised with NTs &
clock(c).
CLK R S Qn+1 Action
↓ 0 0 Qn No change
↓ 0 1 1 SET
↓ 1 0 0 RESET
↓ 1 1 ? Forbidden
TRUTH TABLE

7. -VE EDGE TRIGGERED RS FLIP FLOP-O/P WAVE FORMS
• At time t0 S=0 R=0
Q=0 (No change)
• t1 S=1 R=0
Q changes from 0 to 1
• t2 S=0 R=1
Q resets to 0
• t3 S=1 R=0
Q sets to 1
• t4 S=0 R=0
Q remains at 1