This document proposes four 4:2 compressors that can dynamically switch between exact and approximate modes for use in configurable multipliers. The approximate mode provides higher speeds and lower power at the cost of lower accuracy. Each compressor has a different accuracy level and power/delay in exact and approximate modes. Using these compressors in parallel multipliers allows the accuracy, power, and speed to be dynamically changed at runtime. The compressors were evaluated in a 45nm Dadda multiplier, showing average 46% lower delay and 68% lower power in approximate mode compared to state-of-the-art approximate multipliers. The proposed architecture was also analyzed for logic size, area, and power consumption using Xilinx and Modelsim software.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Parallel Processing Technique for Time Efficient Matrix MultiplicationIJERA Editor
In this paper, we have proposed one designs for parallel-parallel input and single output (PPI-SO) matrix-matrix multiplication. In this design differs by high speed area efficient, throughput rate and user defined input format to match application needs. We have compared the proposed designs with the existing similar design and found that, the proposed designs offer higher throughput rate, reduce area at relatively lower hardware cost. We have synthesized the proposed design and the existing design using Xilinx software. Synthesis results shows that proposed design on average consumes nearly 30% less energy than the existing design and involves nearly 70% less area-delay-product than other. Interestingly, the proposed parallel-parallel input and single output (PPI-SO) structure consumes 40% less energy than the existing structure.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Parallel Processing Technique for Time Efficient Matrix MultiplicationIJERA Editor
In this paper, we have proposed one designs for parallel-parallel input and single output (PPI-SO) matrix-matrix multiplication. In this design differs by high speed area efficient, throughput rate and user defined input format to match application needs. We have compared the proposed designs with the existing similar design and found that, the proposed designs offer higher throughput rate, reduce area at relatively lower hardware cost. We have synthesized the proposed design and the existing design using Xilinx software. Synthesis results shows that proposed design on average consumes nearly 30% less energy than the existing design and involves nearly 70% less area-delay-product than other. Interestingly, the proposed parallel-parallel input and single output (PPI-SO) structure consumes 40% less energy than the existing structure.
ANALYSIS OF TRANSFER LINE WITH BUFFER STORAGEManoj Gowda K
An automated transfer line is consisted of several workstations which are linked together by a material handling system where parts are transferred from one station to the next.
Low cost high-performance vlsi architecture for montgomery modular multiplica...LogicMindtech Nologies
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
Design and simulation of single phase five-level symmetrical cascaded h-bridg...Asoka Technologies
Multilevel inverter is an effective and practical solution for increasing power demand and reducing harmonics of ac waveforms. Such inverters synthesize a desired output voltage from several levels of dc voltages as inputs. This paper analyzes the performance of five level cascaded H-bridge multilevel inverter with reduce number of power switches. Further by reducing switches and increasing level will reduce filter cost & harmonic content. 5- Level cascaded H-bridge asymmetrical multilevel inverter topology requires 8 switches but in this new multilevel inverter it requires 6 switches in which same multilevel is obtained. Invariably switching losses and cost also reduced. In this paper only multilevel inverter circuitry will be studied. The performance has been analyzed by the MATLAB/Simulink.
Design and Implementation of a Programmable Truncated Multiplierijsrd.com
Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. However, this result in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction trade off against signal degradation which can be modified at run time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analysed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation also shown to be effective when deploying truncated multipliers in a system.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
Distributed arithmetic (DA) calculation is generally utilized for FIR channel execution. In the starting, DA was proposed as successive DA (SDA), and at that point was stretched out to parallel DA (PDA) for higher throughput. This paper introduces a novel PDA FIR channel design in view of 4:2 compressors which can be mapped on Xilinx FPGAs effectively. Overall, our proposed FIR models accomplish 17.5% decrease in asset use and 20.7% change in execution contrasted with the cutting edge PDA FIR channel. Additionally, overall, there is 57.9% decrease in asset utilization and 23.0% change in execution contrasted with PDA FIR. Another 4:2 compressor design in light of changing some inward conditions are proposed. Furthermore, utilizing an efficient full-snake (FA) square is considered to have a fast blower. Three 4:2 compressors are considered for examination. The proposed engineering is contrasted and the best existing plans exhibited in the best in class writing regarding force, deferral and territory. The paper presents compressors that are broadly utilized as building squares of multipliers.
A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. To implement power efficient and high performance analog-to-digital converters the designers are urged to design an optimized dual tail comparator. In this paper, It is shown that in the proposed dual tail comparator both the power and delay time is significantly reduced.
On the fragility of fractional-order PID controllers for FOPDT processesISA Interchange
This paper analyzes the fragility issue of fractional-order proportional-integral-derivative controllers applied to integer first-order plus-dead-time processes. In particular, the effects of the variations of the controller parameters on the achieved control system robustness and performance are investigated. Results show that this kind of controllers is more fragile with respect to the standard proportional-integral-derivative controllers and therefore a significant attention should be paid by the user in their tuning.
PaperLoad following in a deregulated power system with Thyristor Controlled S...rajeshja
Load following is considered to be an ancillary service in a deregulated power system. This paper investigates
the effect of a Thyristor Controlled Series Compensator (TCSC) for load following in a deregulated
two area interconnected thermal system with two GENCOs and two DISCOs in either areas. Optimal
gain settings of the integral controllers in the control areas are obtained using Genetic Algorithm by
minimizing a quadratic performance index. Simulation studies carried out in MATLAB validates that a
Thyristor Controlled Series Compensator in series with tie-line can effectively improve the load following
performance of the power system in a deregulated environment.
Design optimization of an axial flow compressor for industrial gas turbineeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
ANALYSIS OF TRANSFER LINE WITH BUFFER STORAGEManoj Gowda K
An automated transfer line is consisted of several workstations which are linked together by a material handling system where parts are transferred from one station to the next.
Low cost high-performance vlsi architecture for montgomery modular multiplica...LogicMindtech Nologies
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
Design and simulation of single phase five-level symmetrical cascaded h-bridg...Asoka Technologies
Multilevel inverter is an effective and practical solution for increasing power demand and reducing harmonics of ac waveforms. Such inverters synthesize a desired output voltage from several levels of dc voltages as inputs. This paper analyzes the performance of five level cascaded H-bridge multilevel inverter with reduce number of power switches. Further by reducing switches and increasing level will reduce filter cost & harmonic content. 5- Level cascaded H-bridge asymmetrical multilevel inverter topology requires 8 switches but in this new multilevel inverter it requires 6 switches in which same multilevel is obtained. Invariably switching losses and cost also reduced. In this paper only multilevel inverter circuitry will be studied. The performance has been analyzed by the MATLAB/Simulink.
Design and Implementation of a Programmable Truncated Multiplierijsrd.com
Truncated multiplication reduces part of the power required by multipliers by only computing the most-significant bits of the product. The most common approach to truncation includes physical reduction of the partial product matrix and a compensation for the reduced bits via different hardware compensation sub circuits. However, this result in fixed systems optimized for a given application at design time. A novel approach to truncation is proposed, where a full precision multiplier is implemented, but the active section of the partial product matrix is selected dynamically at run-time. This allows a power reduction trade off against signal degradation which can be modified at run time. Such architecture brings together the power reduction benefits from truncated multipliers and the flexibility of reconfigurable and general purpose devices. Efficient implementation of such a multiplier is presented in a custom digital signal processor where the concept of software compensation is introduced and analysed for different applications. Experimental results and power measurements are studied, including power measurements from both post-synthesis simulations and a fabricated IC implementation. This is the first system-level DSP core using a fine-grain truncated multiplier. Results demonstrate the effectiveness of the programmable truncated MAC (PTMAC) in achieving power reduction, with minimum impact on functionality for a number of applications. Software compensation also shown to be effective when deploying truncated multipliers in a system.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
Distributed arithmetic (DA) calculation is generally utilized for FIR channel execution. In the starting, DA was proposed as successive DA (SDA), and at that point was stretched out to parallel DA (PDA) for higher throughput. This paper introduces a novel PDA FIR channel design in view of 4:2 compressors which can be mapped on Xilinx FPGAs effectively. Overall, our proposed FIR models accomplish 17.5% decrease in asset use and 20.7% change in execution contrasted with the cutting edge PDA FIR channel. Additionally, overall, there is 57.9% decrease in asset utilization and 23.0% change in execution contrasted with PDA FIR. Another 4:2 compressor design in light of changing some inward conditions are proposed. Furthermore, utilizing an efficient full-snake (FA) square is considered to have a fast blower. Three 4:2 compressors are considered for examination. The proposed engineering is contrasted and the best existing plans exhibited in the best in class writing regarding force, deferral and territory. The paper presents compressors that are broadly utilized as building squares of multipliers.
A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. To implement power efficient and high performance analog-to-digital converters the designers are urged to design an optimized dual tail comparator. In this paper, It is shown that in the proposed dual tail comparator both the power and delay time is significantly reduced.
On the fragility of fractional-order PID controllers for FOPDT processesISA Interchange
This paper analyzes the fragility issue of fractional-order proportional-integral-derivative controllers applied to integer first-order plus-dead-time processes. In particular, the effects of the variations of the controller parameters on the achieved control system robustness and performance are investigated. Results show that this kind of controllers is more fragile with respect to the standard proportional-integral-derivative controllers and therefore a significant attention should be paid by the user in their tuning.
PaperLoad following in a deregulated power system with Thyristor Controlled S...rajeshja
Load following is considered to be an ancillary service in a deregulated power system. This paper investigates
the effect of a Thyristor Controlled Series Compensator (TCSC) for load following in a deregulated
two area interconnected thermal system with two GENCOs and two DISCOs in either areas. Optimal
gain settings of the integral controllers in the control areas are obtained using Genetic Algorithm by
minimizing a quadratic performance index. Simulation studies carried out in MATLAB validates that a
Thyristor Controlled Series Compensator in series with tie-line can effectively improve the load following
performance of the power system in a deregulated environment.
Design optimization of an axial flow compressor for industrial gas turbineeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Analysis of Harmonics and Ripple Current in Multi-Module Converters with Incr...IAES-IJPEDS
Controlled rectifiers are considered as the most important hardware part in
the field of HVDC systems in transmission lines and can be used for a
number of power electronics based system operation, control and utility
applications. In this paper, a brief design of a 12-pulse, 24-pulse, 36-pulse
and a 48-pulse converter connected to the grid is presented along with the
harmonic and ripple current analysis with its comparison statistics and thus
providing a justification for the suitable ones. The performance of the
12, 24, 36 and 48-pulse converters are compared for their effectiveness in
both quantitatively as well as qualitatively. Further, comparison of the
48-pulse converter on its THD and current ripple which is connected towards
the grid with simple pulse width modulation technique is also proposed. It
combines all features of the low switching concepts and DC current reinjection
techniques. Some basic topological explanation of the controlled
rectifiers and simulation results using MATLAB are also presented in this
paper in order to justify the harmonic analysis. The simulation results along
with the quantitative results shows the effectiveness of the proposed scheme
for the cancelation or the elimination of the harmonics result in maximum
harmonic mitigation, for high power utility applications, the 48-pulse
converter is most fitting to improve the conversion efficiency, low di/dt
and dv/dt and active and reactive power controllability.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
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Fuzzy logic Technique Based Speed Control of a Permanent Magnet Brushless DC...IJMER
This paper presents an analysis by which the dynamic performances of a permanent magnet
brushless dc (PMBLDC) motor drive with different speed controllers can be successfully predicted. The
control structure of the proposed drive system is described. The dynamics of the drive system with a
classical proportional-integral-derivative (PID) and Fuzzy-Logic (FL) speed controllers are presented.
The simulation results for different parameters and operation modes of the drive system are investigated
and compared. The results with FL speed controller show improvement in transient response of the
PMBLDC drive over conventional PID controller. Moreover, useful conclusions stemmed from such a
study which is thought of good use and valuable for users of these controllers
Multi-Objective Optimization Based Design of High Efficiency DC-DC Switching ...IJPEDS-IAES
In this paper we explore the feasibility of applying multi objective stochastic
optimization algorithms to the optimal design of switching DC-DC
converters, in this way allowing the direct determination of the Pareto
optimal front of the problem. This approach provides the designer, at
affordable computational cost, a complete optimal set of choices, and a more
general insight in the objectives and parameters space, as compared to other
design procedures. As simple but significant study case we consider a low
power DC-DC hybrid control buck converter. Its optimal design is fully
analyzed basing on a Matlab public domain implementations for the
considered algorithms, the GODLIKE package implementing Genetic
Algorithm (GA), Particle Swarm Optimization (PSO) and Simulated
Annealing (SA). In this way, in a unique optimization environment, three
different optimization approaches are easily implemented and compared.
Basic assumptions for the Matlab model of the converter are briefly
discussed, and the optimal design choice is validated “a-posteriori” with
SPICE simulations.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to
around the operands to the closest exponent of 2. This way the machine intensive a part of the
multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is
evaluated by comparing its performance with those of some approximate and correct multipliers using
different design parameters. In this proposed approach combined the conventional RoBA multiplier with
Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA
multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved
the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the
DSP.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.
Similar to Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers (20)
Java Web Application Project Titles 2023-2024.
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E-Authentication System using QR Code and OTP
Student Attendance System Using QR-Code
Hall Ticket Generation System with Integrated QR Code
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QR Code-based Smart Vehicle Parking Management System
Employee Attendance System using QR Code
QR Code based Secure Online Voting System
QR Code Based Smart Online Student Attendance System
Cyber Security Projects
Detecting Malicious Facebook Applications
Detection of Bullying Messages in Social Media
Enhanced Secure Login System using Captcha as Graphical Passwords
Filtering Unwanted Messages in Online Social Networking User walls
Secure Online Transaction System with Cryptography
Detecting Mobile Malicious Webpages in Real Time
Credit Card Fraud Detection in Online Shopping System
Enhanced Data Security with Onion Encryption and Key Rotation
Detection of Offensive Messages in Social Media to Protect Online Safety
Healthcare Projects
Diabetes Prediction using Data Mining in Healthcare Management System
Online Hospital Management System
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Enhanced Hospital Admission System to Mitigate Crowding
Online Parking Booking System
E-Pass Management System | Curfew e-pass management system
Online Tender Management System
Online Toll Gate Management System
Online Election System
Panchayat Union Automation System
Smart City Project - A Complete City Guide Using Database
Visa Processing Management System
Cricket Win Predictor using Machine Learning
College Management System
Online college Counselling system
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Online Student Mentoring System
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Bike Store Management System
Computer Inventory System
Distilled Water Management System
Donation Tracking System | Online Charity Management System
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Online Content Based Image Retrieval System with Ranking Model
Online Crime File Management System
Online Courier Management System
Online Blood Bank Management System
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Connecting Social Media to E-Commerce
Twitter Based Tweet Summarization
Mental Disorders Detection via Online Social Media Mining
Detecting Stress Based on Social Interactions in Social Networks
Knowledge Sharing Based Online Social Network with Question and Answering System
Predicting Suicide Intuition in Online Social Network
Predicting Emotions of User in Online Social Network
Employee Payroll Management System
Human Resource Management System
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College Admission Predictor
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Personalized Movie Recommendation System
Product Recommendation System in Online Social Network
Mining Online Product Evaluation System based on Ratings and Review Comments
Online Book Buying and Selling
MATLAB IEEE Projects 2023 – 2024.
Brain Tumor Detection and Classification Using Artificial Intelligence
Classification of Potholes using Convolutional Neural Network Model
Deep Learning Based Parkinson's Disease Progression Analysis Using DaTscan Images
Artificial Intelligence based Facial Emotions Analysis for Depression Detection
Grading Of Diabetic Retinopathy Using Deep Learning
Identification of Plant Disease from Leaf Images Based on Convolutional Neural Network
Knee Osteoarthritis Detection and Classification Using X-Rays
Weeds and Crop Image Classification using Deep Learning Technique
URL Based Phishing Website Detection using Machine Learning Models
AI-based Gender Identification using Facial Features
Skin Disease Classification using Deep Learning
Driver Drowsiness Detection System Using Image Processing
Classification of Leukemia White Blood Cell Cancer using Image Processing and Machine Learning
Age Prediction through Facial Images using Deep Learning
Brain Stroke Classification Through Image Processing and SVM
Video-Based Driver Drowsiness Detection System
Enhanced Fog Detection and Visibility Measurement in Adverse Weather Conditions
Flower Species Detection using Machine Learning Technique
Face Recognition and Expression Detection for the Visually Impaired
Night Time Vehicle Detection Using Image Processing and Linear SVM
Human Action Recognition using Image Processing and Nearest Mean Classifier
Traffic Light Controller System and Road Congestion Detection based on Counting of Vehicles
Secure Authentication System Using Visual Cryptography
Effective Detection of Copy Move Forgery using HOG and Machine Learning
Traffic Sign Detection and Classification using HOG and SVM
Python IEEE Papers / Projects 2023 – 2024.
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🌐Website: https://www.jpinfotech.org
📞MOBILE: (+91)9952649690.
DEEP LEARNING IEEE PROJECTS 2023
Blood Cancer Identification using Hybrid Ensemble Deep Learning Technique
Breast Cancer Classification using CNN with Transfer Learning Models
Calorie Estimation of Food and Beverages using Deep Learning
Detection and Identification of Pills using Machine Learning Models
Detection of Cardiovascular Diseases in ECG Images Using Machine Learning and Deep Learning Methods
Development of Hybrid Image Caption Generation Method using Deep Learning
Dog Breed Classification using Inception-ResNet-V2
Forest Fire Detection using Convolutional Neural Networks (CNN)
Digital Image Forgery Detection Using Deep Learning
Image-Based Bird Species Identification Using Machine Learning
Kidney Cancer Detection using Deep Learning Models
Medicinal Herbs Identification
Monkeypox Diagnosis with Interpretable Deep Learning
Music Genre Classification Using Convolutional Neural Network
Pancreatic Cancer Classification using Deep Learning
Prediction of Lung Cancer using Convolution Neural Networks
Signature Fraud Detection using Deep Learning
Skin Cancer Prediction Using Deep Learning Techniques
Traffic Sign Classification using Deep Learning
Disease Classification in Wheat from Images Using CNN
Detection of Lungs Cancer through Computed Tomographic Images using Deep Learning
MACHINE LEARNING IEEE PROJECTS 2023
A Machine Learning Framework for Early-Stage Detection of Autism Spectrum Disorders
A Machine Learning Model to Predict a Diagnosis of Brain Stroke
CO2 Emission Rating by Vehicles Using Data Science
Cyber Hacking Breaches Prediction and Detection Using Machine Learning
Fake Profile Detection on Social Networking Websites using Machine Learning
Crime Prediction Using Machine Learning and Deep Learning
Drug Recommendation System in Medical Emergencies using Machine Learning
Efficient Machine Learning Algorithm for Future Gold Price Prediction
Heart Disease Prediction With Machine Learning
House Price Prediction using Machine Learning Algorithm
Human Stress Detection Based on Sleeping Habits Using Machine Learning Algorithms
Sentiment Classification using N-gram IDF and Automated Machine LearningJAYAPRAKASH JPINFOTECH
Sentiment Classification using N-gram IDF and Automated Machine Learning
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Privacy-Preserving Social Media DataPublishing for Personalized Ranking-Based...JAYAPRAKASH JPINFOTECH
Privacy-Preserving Social Media Data Publishing for Personalized Ranking-Based Recommendation
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FunkR-pDAE: Personalized Project Recommendation Using Deep LearningJAYAPRAKASH JPINFOTECH
FunkR-pDAE: Personalized Project Recommendation Using Deep Learning
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Discovering the Type 2 Diabetes in Electronic Health Records using the Sparse...JAYAPRAKASH JPINFOTECH
Discovering the Type 2 Diabetes in Electronic Health Records using the Sparse Balanced Support Vector Machine
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Crop Yield Prediction and Efficient use of Fertilizers
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Collaborative Filtering-based Electricity Plan Recommender System
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Achieving Data Truthfulness and Privacy Preservation in Data MarketsJAYAPRAKASH JPINFOTECH
Achieving Data Truthfulness and Privacy Preservation in Data Markets
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V2V Routing in a VANET Based on the Auto regressive Integrated Moving Average...JAYAPRAKASH JPINFOTECH
V2V Routing in a VANET Based on the Auto regressive Integrated Moving Average Model
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Towards Fast and Reliable Multi-hop Routing in VANETs
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Selective Authentication Based Geographic Opportunistic Routing in Wireless S...JAYAPRAKASH JPINFOTECH
Selective Authentication Based Geographic Opportunistic Routing in Wireless Sensor Networks for Internet of Things Against DoS Attacks
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Robust Defense Scheme Against Selective DropAttack in Wireless Ad Hoc NetworksJAYAPRAKASH JPINFOTECH
Robust Defense Scheme Against Selective DropAttack in Wireless Ad Hoc Networks
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Privacy-Preserving Cloud-based Road Condition Monitoring with Source Authenti...JAYAPRAKASH JPINFOTECH
Privacy-Preserving Cloud-based Road Condition Monitoring with Source Authentication in VANETs
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Novel Intrusion Detection and Prevention for Mobile Ad Hoc NetworksJAYAPRAKASH JPINFOTECH
Novel Intrusion Detection and Prevention for Mobile Ad Hoc Networks
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Node-Level Trust Evaluation in Wireless Sensor Networks
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Model Attribute Check Company Auto PropertyCeline George
In Odoo, the multi-company feature allows you to manage multiple companies within a single Odoo database instance. Each company can have its own configurations while still sharing common resources such as products, customers, and suppliers.
Biological screening of herbal drugs: Introduction and Need for
Phyto-Pharmacological Screening, New Strategies for evaluating
Natural Products, In vitro evaluation techniques for Antioxidants, Antimicrobial and Anticancer drugs. In vivo evaluation techniques
for Anti-inflammatory, Antiulcer, Anticancer, Wound healing, Antidiabetic, Hepatoprotective, Cardio protective, Diuretics and
Antifertility, Toxicity studies as per OECD guidelines
Read| The latest issue of The Challenger is here! We are thrilled to announce that our school paper has qualified for the NATIONAL SCHOOLS PRESS CONFERENCE (NSPC) 2024. Thank you for your unwavering support and trust. Dive into the stories that made us stand out!
Francesca Gottschalk - How can education support child empowerment.pptxEduSkills OECD
Francesca Gottschalk from the OECD’s Centre for Educational Research and Innovation presents at the Ask an Expert Webinar: How can education support child empowerment?
Instructions for Submissions thorugh G- Classroom.pptxJheel Barad
This presentation provides a briefing on how to upload submissions and documents in Google Classroom. It was prepared as part of an orientation for new Sainik School in-service teacher trainees. As a training officer, my goal is to ensure that you are comfortable and proficient with this essential tool for managing assignments and fostering student engagement.
Palestine last event orientationfvgnh .pptxRaedMohamed3
An EFL lesson about the current events in Palestine. It is intended to be for intermediate students who wish to increase their listening skills through a short lesson in power point.
How to Make a Field invisible in Odoo 17Celine George
It is possible to hide or invisible some fields in odoo. Commonly using “invisible” attribute in the field definition to invisible the fields. This slide will show how to make a field invisible in odoo 17.
Synthetic Fiber Construction in lab .pptxPavel ( NSTU)
Synthetic fiber production is a fascinating and complex field that blends chemistry, engineering, and environmental science. By understanding these aspects, students can gain a comprehensive view of synthetic fiber production, its impact on society and the environment, and the potential for future innovations. Synthetic fibers play a crucial role in modern society, impacting various aspects of daily life, industry, and the environment. ynthetic fibers are integral to modern life, offering a range of benefits from cost-effectiveness and versatility to innovative applications and performance characteristics. While they pose environmental challenges, ongoing research and development aim to create more sustainable and eco-friendly alternatives. Understanding the importance of synthetic fibers helps in appreciating their role in the economy, industry, and daily life, while also emphasizing the need for sustainable practices and innovation.
Embracing GenAI - A Strategic ImperativePeter Windle
Artificial Intelligence (AI) technologies such as Generative AI, Image Generators and Large Language Models have had a dramatic impact on teaching, learning and assessment over the past 18 months. The most immediate threat AI posed was to Academic Integrity with Higher Education Institutes (HEIs) focusing their efforts on combating the use of GenAI in assessment. Guidelines were developed for staff and students, policies put in place too. Innovative educators have forged paths in the use of Generative AI for teaching, learning and assessments leading to pockets of transformation springing up across HEIs, often with little or no top-down guidance, support or direction.
This Gasta posits a strategic approach to integrating AI into HEIs to prepare staff, students and the curriculum for an evolving world and workplace. We will highlight the advantages of working with these technologies beyond the realm of teaching, learning and assessment by considering prompt engineering skills, industry impact, curriculum changes, and the need for staff upskilling. In contrast, not engaging strategically with Generative AI poses risks, including falling behind peers, missed opportunities and failing to ensure our graduates remain employable. The rapid evolution of AI technologies necessitates a proactive and strategic approach if we are to remain relevant.
Unit 8 - Information and Communication Technology (Paper I).pdfThiyagu K
This slides describes the basic concepts of ICT, basics of Email, Emerging Technology and Digital Initiatives in Education. This presentations aligns with the UGC Paper I syllabus.
"Protectable subject matters, Protection in biotechnology, Protection of othe...
Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
1. Dual-Quality 4:2 Compressors for Utilizing in Dynamic
Accuracy Configurable Multipliers
ABSTRACT:
In this paper, we propose four 4:2 compressors, which have the flexibility of
switching between the exact and approximate operating modes. In the approximate
mode, these dual-quality compressors provide higher speeds and lower power
consumptions at the costof lower accuracy. Each of these compressors has its own
level of accuracy in the approximate mode as well as different delays and power
dissipations in the approximate and exact modes. Using these compressors in the
structures of parallel multipliers provides configurable multipliers whose
accuracies (as well as their powers and speeds) may change dynamically during the
runtime. The efficiencies of these compressors in a 32-bit Dadda multiplier are
evaluated in a 45-nm standard CMOS technology by comparing their parameters
with those of the state-of-the-art approximate multipliers. The results of
comparison indicate, on average, 46% and 68% lower delay and power
consumption in the approximate mode. Also, the effectiveness of these
compressors is assessed in some image processing applications. The proposed
architecture of this paper analysis the logic size, area and power consumption using
Xilinx 14.2.