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The document discusses the design and analysis of approximate 4-2 compressors for use in multipliers, focusing on inexact computing for digital processing at nanometric scales. It presents four schemes for utilizing these compressors in a dadda multiplier, demonstrating reductions in power, delay, and transistor count compared to exact designs, along with application in image processing. The paper emphasizes the performance of the proposed designs in terms of error rates and signal-to-noise ratios, alongside necessary software and hardware requirements.

