The document discusses optimization techniques used in an auto-tuning framework for parallel multicore stencil computations. It describes loop unrolling, cache blocking, and arithmetic simplification implemented as AST transformations. Cache blocking exposes temporal locality and increases cache reuse by organizing data into blocks that fit in cache. The framework applies these serial optimizations and additional parallelization strategies by modifying the AST to reflect the chosen parallelization before code generation.

1. Stencil Computation
Research Project
Jishnu P | Reshmi Mitra
Presentation #1 | Date: 11-Jul-2017

2. The Agenda
Discuss 2 or 3 Optimization
techniques from
An Auto-Tuning
Framework for Parallel
Multicore Stencil
Computations

3. Optimizations
Techniques used in the auto
tuning framework.
Several common optimizations have
been implemented in the framework
as AST transformations, including
● Loop Unrolling
● Cache Blocking
● Arithmetic Simplification

4. Loop Unrolling

12. Cache Blocking
To expose temporal locality and increase cache reuse

13. Cache Blocking
● An important class of algorithmic changes involves blocking data structures to
fit in cache.
● By organizing data memory accesses, one can load the cache with a small
subset of a much larger data set.
● The idea is then to work on this block of data in cache.
● By using/reusing this data in cache we reduce the need to go to memory
(reduce memory bandwidth pressure).

14. An example.

15. Example contd...

16. Arithmetic simplification

25. AST - Abstract Syntax Tree
● Abstract syntax trees are data structures widely used in compilers,
due to their property of representing the structure of program code.
● An AST is usually the result of the syntax analysis phase of a
compiler.
● It often serves as an intermediate representation of the program
through several stages that the compiler requires, and has a strong
impact on the final output of the compiler.

26. AST example

27. These were some of the serial optimizations.
● Although the current set of optimizations may seem identical to existing
compiler optimizations, future strategies such as memory structure
transformations will be beyond the scope of compilers, since such
optimizations are specific to stencil-based computations.
● Additionally, the fact that the framework’s transformations yield code that
outperforms compiler-only optimized versions shows compiler algorithms
cannot always prove that these (safe) optimizations are allowed.
● Thus, a domain-specific code generator run by the user has the freedom to
implement transformations that a compiler may not.

28. Parallelization optimization

29. Parellel Optimization
● The shared-memory parallel code generators leverage the serial code
generation routines to produce the version run by each individual
thread.
● Since the parallelization strategy influences code structure, the AST —
which represents code run on each individual thread — must be
modified to reflect the chosen parallelization strategy.
● The parallel code generators make the necessary modifications to the
AST before passing it to the serial code generator.

30. Stencil auto-tuning framework flow

31. References
● http://people.csail.mit.edu/cycha
n/papers/ipdps10.pdf
● https://en.wikipedia.org/wiki/Abs
tract_syntax_tree
● https://www.youtube.com/watch
?v=SfV8aRX0YY0
● https://software.intel.com/en-us/
articles/cache-blocking-techniqu
es

32. Sometimes it is good to revisit our learnings. It helps to be a
good competitor and also to be prepared for grabbing
opportunities.
Thank you