This document contains questions from previous year university examination papers on the topic of digital system design. It covers 5 units: Unit 1 includes questions on binary codes, Boolean algebra identities, prime implicants, minterms, maxterms, SOP, POS, simplifying Boolean functions, and Karnaugh maps. Unit 2 includes questions on decoders, multiplexers, adders, encoders, priority encoders, magnitude comparators, and parallel adders. Unit 3 includes questions on edge triggered flip flops, ring counters, clocked sequential circuits, synchronous counters, asynchronous counters, and shift registers. Unit 4 includes questions on programmable logic arrays, RAM, PAL, memory

1. DIGITAL SYSTEM DESIGN PREVIOUS YEAR UNIVERSITY QUESTIONS
UNIT – 1
1. Explain in detail about Binary codes
2. Demonstrate the validity of the following identities by means of truth table :
(a) DeMorgan’s Theorem for three variables :
(x+y+z) = x’y’z’ and (xyz)’=x’+y’+z’
(b) The distributive law : X + YZ = (x+y)(x+z)
3. Determine the prime – implicants of the function.
F(W,X,Y,Z) = ∑(1,4,6,7,8,9,10,11,15)
4. Write a short notes on Minterms, Maxterms, SOP and POS.
5. Simplify the Boolean function
F(A,B,C,D,E) = ∑(0,2,4,6,9,11,13,15,17,21,25,27,29,31)
6. Decimal 225 to binary, octal and hexadecimal
7. Binary 11010111 to decimal, octal and hexadecimal
8. simplify the following expression using K- map
(a) F(X,Y,Z) = ∑(1,2,3,6,7)
(b) F(X.Y,Z) = ∑(0,1,5,7)
(c) F(W,X,Y,Z) = ∑(2,3,12,13,14,15)
9. Implement BCD to Excess-3 code
10. Explain the basic Boolean algebra operations and theorems with suitable example
11. Explain karnaugh maps in detail.
UNIT – 2
1. With a proper truth table and a logic diagram, explain three-to-eight decoder.
2. Explain the Multiplexer and De-multiplexer with its logic diagram.
3. Write in detail about adders and subtractors
4. Explain in detail about Encoder and Decoder with neat diagram
5. Explain in detail about Priority encoder.
6. Discuss the design and implementation of Magnitude comparator.
7. Explain in detail about 4 bit binary parallel adder.
8. Explain in detail about 4 bit parallel adder.
UNIT – 3
1. Explain the edge triggered flip flops with neat logic diagram.
2. With a neat sketch, describe the working principles of Ring counter
3. Describe about clocked sequential circuit.
4. Explain about synchronous counter
5. Explain about asynchronous counter.
6. Discuss about sequential cirucuits
7. Explain about shift registers.
8. Discuss and design of 3 bit counter
9. Discuss on various counters in detail.
UNIT – 4
1. Describe the Programmable Logic Array in detail with a proper diagram.
2. Elaborate Ram with its operations.
3. Explain the neat diagram with PAL.
4. Explain in detail about Memory organization and Memory organization.
5. Explain in detail about coincident decoding.
6. When is an RTOS necessary and when is it not necessary in the embedded systems?
7. Explain mail boxes and virtual sockets.
UNIT – 5
1. Give the HDL design module of Multiplexer and Adder
2. Elaborate various levels of Design Description in Verilog.
3. Discuss in detail about the operators in Verilog
4. Discuss in detail about always statement and conditional statement.
5. Give the design description of 2 to 4 line decoder circuit.
6. Explain the HDL sequential circuits.
7. Discuss on the registers and counters in detail
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