The document discusses Direct Memory Access (DMA) which allows input/output (I/O) devices to access main memory directly without intervention from the Central Processing Unit (CPU). It describes how the DMA controller takes control of the address bus, data bus, read and write lines to facilitate direct transfer between I/O devices and memory while the CPU is temporarily disabled. It also explains the different signals and lines used by the DMA controller to communicate with devices and memory as well as the two common modes of DMA transfer: burst and cycle stealing.

1. Roll No 12001006 Paper Code ii061 NA Page No9.
Ans: Dire.ctMemors Access (DMA):
The Direct memoryAccess(DMA)iSan T/otechnique thatbravideS
direct AGcess to the mainmemory_while CPuistemborarilu
Ldisable.d,to sheed uh the memoru 0berations-
Ihis bracess is_managed bhs a chib knoun aS DMA Controller
LCDMAG.
I6devicesare Connecked to SystemBusvia a Shecial InterHace
Circuit called"DMA Controller"
InDMA,both CPU and DMA Controller have acc.ess to hemain
memoru via Shared System bushaving data, Address_and
Control lines.
DMA allows Tlo Devices to transter datadirectlu to or
ftom the main_memory with.out CPU intervention CorSimblu
by aSSing the CPU trom thebath
Conhol Sionals
From To to
DMAController
for it'S Access
ABUS
Add ress BUS- AR
DBUS
Data BUS
DS
DMASelect
Register Select
weR
RS DMA
RD
Read Controller R
WR
write DMARequest
BR
BusReguest
BUs Groant
Interrubt
BG
Lnterrust DMA Acknouwle9-
-ment
Control lineS fig:DMA Controller
DMAController takesover tht ContralofBuses toallouw the
tranSfer direcHy iom main_Me.mory to or from Ilodevices
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2. Roll No 12001006 Paper Code 11061/N1 Page No10.
DMA lorking:
ohen Ilo wans to transfer data with main Memory
Ilo device Sends DMA Reguest to DMA Controller(DMAC).
DMACSends BR(Bus Request)Siqnal to CPU for requesting
he conhrolot Buses
DMA waits untilLCPU SendS BG Bus G1rant) Signal to DMA
CPU neleaSe the antroloBuses and place Address BUS
LARUS),DatoBus(DBUS),Read(RD)and lwrite(WR) lines
into High-Tmbedenc.e State
CPU activates the BG (LeBusGrant)Stanaland becomesim
Idle Stote (disabled).
DMA Contmller takes Conhnl of Buses to Conduct direct
memory transfer withdut CPU InteryentHon
when DMA tanster terminates,it dis.a.blesHhe BRG.e
Bus Request)line.
The CPU disables the BGCBUS Gant).
After that CPu toakesthe Contral ofBuSES and returnto
S normal oheotion.
BRRus Reauest
DMA BGRLS Girant+
I/o Acknowlegment
DMA
Requestt ABUS
High
Tmbedence
Cdisobled)
BR
DMA
Controller
DBUS
C.P.U RD
BG wR hen BG-1
Enabled
CPU Signal to DMA Conttoller
that Buseaare inHigh-Imbedence
Main
Memory
(RAM)
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3. Roll No 2001006 Paper Code 1io61/NJ Page No 11
DMATransfer:
he DMA Controller Communjcates withthe CPUvia data bus_
and Controlline.S.
Ihe Connection between the DMA Contraller and ofher Combanen-
ESina Combuter Suskemtor DMA Tansfer is as fallnwsi
Interrupt
BG
BR
Randam-Access
CPU Memory (RAM)
RD wR AddressData. RD WR Address Data |
RD
wR
Data BUS
Address
Select
Address BUS
RD WRR Address Data
DS DMA
RS DMA
Reques+
Periphera
BR Controller
DMA Device
BG
Tnterrupt
Acknouslege
Frg: DMA Iranster
The DMA request lineis used torequest a DMA Tmnster
TheRegistersin DMA are selectedbu the CPU through
he Address BuS byenabling DS(DMA Select) and
Register Seleck
Read (RD) and wuriteLwR linesare Bidirectional
Luhen BG (Busarant) inbutiS0 (i:e BG=0) the CPUCa
1Communicate ith DMA Registers, hrough he Dato BUSto
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4. Roll No 12001006 PaperCode11o61 NJ Page No12.
read from orwrite to the DMA Registers.
hen BG:1, the CPu has to release the Busts andthe
DMACan CommuniG.ate directu with fhe main emor-
byShecifuing an address in he AddressBus and
a.ctivating Rnand uwR Contral.
DMACo.mmumicate with the externalTlo devices through
Tne_request and ackmowlegment lines by he HandShalsiue
rocedue
he DMA Acknoulegment 1line is set when the Sysienm iS
readyto initiate data tmnsfer
he data lous is uSed to transter_clata hetween T/odevice
and memoru
Lwhenthe last word odata in theDMA hransferis
ransfer red,he dma Controller informs the fermmation
ohransferto CPU bå meanso Inierrukt lines
Modes of DMA Transter: 4-bute burst
Burst Transfer
Mode
) |Burst Transter:
Tn DMA,Burst Transfer,Li.ea black_Seqvence_Consistingo
numberomemary wordsto ransterre.d in Gonlinuous
burst while the DMA ismast+er o memory BUSES
This mode isneeded or fastdevices Suchaamagnelicdisk
where thedata ransfer Can' be Slouwed.
Breakbotnt_
it Cacle Stealing
Caycle Sealing,allouwsDMACanhmllertotran8ferone dataword
ata ime, after uhich it must rehurn Cantrol tn CPU_
The CPU_merely_delays it'SOheratinn for one memory Cycleto
alloln the direct transfer m Ilot_memory_to 'steal) one
memary Cycle 18ed bu Sloo devices Suchas keybnard
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