The document provides information on logic minimization techniques including Karnaugh maps (K-maps) for two, three, four and more variables, prime implicant charts, don't care conditions, NAND and NOR gate implementations, and the Quine-McCluskey (Q-M) tabulation method. Examples are given for each topic to demonstrate how to use the techniques to minimize logic functions and implement them using basic gates.
4. MAP FO R : x’yz+xy’z’+xyz+xyz’=yz+xz’
yz
x
00 01 11 10
0
1 1
1
1
1
z
y
A
BC
A
00 01 11 10
0
1
C
BC B
1
1 1
11
1
MAP FOR : A’C+A’B+AB’C+BC=C+A’B
yz
x
00 01 11 10
0
1
y
x
F(x,y,z)=Σ(0,2,4,5,6)=z’+xy’
1
1
1 1
1
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5. m0 m1 m3 m2
m6
m14
m10m11m9m8m8
m12 m13 m15
m7m5m4
(a)
y
z
w
00
01
11
10
00 01 11 10wx
yz
x
w’x’y’z’
w’xy’z’
wxy’z’
wx’y’z’
w’x’y’z w’x’yzw’x’yz w’x’yz’
w’xyz’
wxyz’
wx’yz’wx’yzwx’y’z
wxy’z wxyz
w’xyzw’xy’z
FOUR VARIBALE MAP
1 square represents a term of 4 literals.
2 adjacent squares represent a term of 3 literals.
4 adjacent squares represent a term of 2 literals.
8 adjacent squares represent a term of 1 literal.
16 adjacent squares represent the function equal to 1
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6. MAP FOR : F(w,x,y,z)=Σ(0,1,2,4,5,6,8,9,12,13,14)=y’+w’z’+xz’
y
yz
z
00
01
11
10
10110100
wx
x
w
1
1
1
1 1
1
1
1
1
1
1
C
CD
D
00
01
11
10
10110100
AB
B
A
1 1 1
1
1
MAP FOR : A’B’C’+B’CD’+A’BCD’+AB’C’=B’D’+B’C’+A’CD’
1 1
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7. A
C
AB
00
01
11
10
000 001 011 010 110 111 101 100
CDE
B
D
E
E
FIVE -VARIABLE MAP
0 1 3 2 6 77 5 4
8 9 11 10 15 13 12
282931
==
30
14
26272524
16 17 19 18 22 23 21 20
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10. 11
1111
1111
11
1 1
CDE
000 001 011 010 110 111 101 100
C
B
AB
00
01
11
10
E D E
A
F=BE+AD’E+A’B’E’
F(A,B,C,D,E)=Σ
(0,2,4,6,9,11,13,15,17,21,25,27,29,31)
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11. Example
F(A , B, C, D) =∑(0,1,2,5,8,9,10)
(ii) Simplify it in:
(iii) Sum of products
(iv) Product of sums
AB
(i) Sum of products
F=B’D’+B’C’+A’C’D
F’ =AB+CD+BD’
(ii) F=(A’+B’)(C’+D’)(B’+D)
00
01
11
10
A
11
CD
00 01 10
1011
0000
0010
1011
C
D
B
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13. GATE IMPLEMENTATION
X Y Z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
7 0 1 0
1 1 0 1
1 1 1 0
TRUTH TABLE OF
FUNCTION F
F(x,y,z)= Σ(1,3,4,6)
F(x,y,z)= Σ(1,3,4,6)
F(x,y,z) = ∏ (0,2,5,7)
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14. 1001
0110
0
1
00 01 11 10
z
yzx
x
y
Sum of products
F=x’z+xz’)
Product of sums
F’=xz+x’z’
F=(x’+z’)(x+z)
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15. NAND and NOR implementation
x
y
z
F=(xyz)’
AND invert
x
y
z
F=(x’+y’+z’)=(xyz)’
Invert-OR
F=(x+y+z)’
OR-invert
(a) TWO GRAPHIC SYMBOLS FOR NAND GATE
x
y
z F=x’y’z’=(x+y+z)’
Invert-AND
(b) TWO GRAPHIC SYMBOLS FOR NOR GATE
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16. x’x x x’
Buffer-invert AND-invert
x x’
OR-invert
THREE GRAPHIC SYMBOLS FOR INVERTORFaaDoOEngineers.com
23. Example
F(n, y, z) = {(0, 6)
F = x’y’z’ + xyz’
F’ = x’y + xy’ + z
x
y’
x’
y
z’
F
(a) F = (x + y’) (x’ + y)z’
x
y
z
x’
y’
z
F
F’
(b) F’ = (x + y + z) (x’ + y’ + z)
IMPLEMENTATION WITH NOR GATES
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27. PRIME-IMPLICANTS
Decimal Binary
w x y z
Term
1,9 (8)
4,6 (2)
6,7 (1)
7,15 (8)
11,15 (4)
8,9,10,11 (1,2)
- 0 0 1
0 1 - 0
0 1 1 -
- 1 1 1
1 - 1 1
1 0 - -
X’ y’ z
W’ x z’
w’ x y
X y z
w y z
W x’
F=x’y’z+w’xz’+w’xy+xyz+wyz+wx’
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28. (i) Selection of
PRIME-IMPLICANTS
1 4 6 7 8 9 10 11 15
x’y’z 1,9 X X
w’xz’ 4,6 X X
w’xy 6,7 X X
xyz 7,15 X X
wyz 11,15 X X
wx’ 8,9,10,11 X X X X
F=x’y’z+w’xz’+wx’+xyz
Essential Prime-implicants
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29. 1111
1
111
1
01
11
10
YZ
00 01 11 10
w
x
z
wx
00
F(w,x,y,z)=∑(1,4,6,7,8,9,10,11,15)
y
MAP FOR THE FUNCTION OF
F = x’y’z+w’xz’+xyz+wx’
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31. (i) Selection of
PRIME-IMPLICANTS
0 1 2 8 10 11 14 15
w’x’y’ 0,1 X X
x;z’ 0,2,8,10 X X X X
wy 10,11,14,15 X X X X
Essential Prime-implicants : F=w’x’y’+x’z’+wy
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32. 111
11
11 1
00 01 11 10
Y
10
11
01
00
wx
yz
W
X
F= w’x’y’ + x’z’+wy
MAP FOR THE FUNCTION
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33. RULES FOR NAND and NOR IMPLEMENTATION
Case
Function
to
Simplify
Standrad
From to
Use
How to
drive
Implement
with
Number
of Levels
to F
(a)
(b)
(c)
(d)
F
F
F
F
Sum of
Products
Sum of
Products
Product
of Sums
Product
of Sums
Combine 1,s
in map
Combine 0, s
In map
Complement
F in (b)
Complement
F in (a)
NAND
NAND
NOR
NOR
2
3
2
3
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34. A
B
C
D
F
F = (AB + CD)’
F = (A B)’ . (C D)’
(a) Wired – AND in open Collector TTL NAND
gates
C
A
B
D
F
F = [(A + B ) ( C + D)]’
F = (A + B)’ + (C + D)’
(b) Wired – OR in ECL gates
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35. A
B
C
D
E
A
B
C
D
E
F F
(AND – OR - INVERT) OR – AND - INVERT
WIRED LOGIC
A
B
C
D
E
F
(a) AND - NOR (b) AND - NOR
(c) NAND - AND
AND – OR – INVERT CIRCUITS F = (AB + CD + E)’
(Non degenerate form)
AND - - NOR & NAND – AND are equivalent forms
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36. NONDEGENERATE FORMS
COMMON GATE : AND, OR, NAND, NOR
IF AT LEVEL 1 : ONE TYPE OF GATE
AT LEVEL 2 : ONE TYPE OF GATE
* POSSIBLE COMBINATIONS = 16
8 OF THESE COMBINATIONS ARE SAID TO BE DEGENERATE FORMS
BECAUSE THEY DEGENERATE TO A SINGLE OPERATION.
FOR EXAMPLE :
NAND – OR AND – AND OPERATION
NAND – NOR OR – OR OPERATION
NOR – AND AND – NAND OPERATION
NOR – NAND OR – NOR OPERATION
8 OF THESE COMBINATION S ARE SAID TO BE NON – DEGENERATE
FORMS BECAUSE THEY PRODUCE AN IMPLEMENTATION IN SUM OF PRODUCTS OR
PRODUCT OF SUMS.
FOR EXAMPLE :
AND – OR OR – AND
NAND – NAND NOR – NOR
NOR – OR NAND – AND
OR – NAND AND - NOR
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38. A
B
C
D
E
F
(C) NOR - OR
OR – AND – INVERT F = [(A + B ) (C + D ) E]’
(Non – degenerate form)
OR – NAND & NOR – OR ARE EQUIVALENT FORMSFaaDoOEngineers.com
39. X’
y
X
y’
z
F
X’
y
X
y’
z
F
Example
AND - NOR NAND - AND
F = x’ y + x y’ + z
(a) F = (x’ y + x y’ + z)’
1 0 0 0
0 0 0 1
0
1
00 01 11 10
F’ = x’ y + x y’ + z
F = x’ y z’ + x y z’
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40. x
y
z
z
x’
y’
F
x
y
z
z
x’
y’
F
OR - NAND NAND - OR
F = x’ y’ z’ + x y z’
F = (x + y + z) (x’ + y’ +z)
(b) F = [(x + y + z) (x’ + y’ + z)]’
TWO – LEVEL IMPLEMENTATION
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