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- 1. DIGITAL ELECTRONICS LABEx. No:1 STUDY OF LOGIC GATESDate:AIM: To study about logic gates and verify their truth tables.APPARATUS REQUIRED: SL No. COMPONENT SPECIFICATION QTY 1. AND GATE IC 7408 1 2. OR GATE IC 7432 1 3. NOT GATE IC 7404 1 4. NAND GATE 2 I/P IC 7400 1 5. NOR GATE IC 7402 1 6. X-OR GATE IC 7486 1 7. NAND GATE 3 I/P IC 7410 1 8. IC TRAINER KIT - 1 9. PATCH CORD - 14THEORY: Circuit that takes the logical decision and the process are called logic gates.Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known asuniversal gates. Basic gates form these gates.AND GATE: Page No: 4
- 2. DIGITAL ELECTRONICS LAB The AND gate performs a logical multiplication commonly known as ANDfunction. The output is high when both the inputs are high. The output is low levelwhen any one of the inputs is low.OR GATE: The OR gate performs a logical addition commonly known as OR function.The output is high when any one of the inputs is high. The output is low level whenboth the inputs are low.NOT GATE: The NOT gate is called an inverter. The output is high when the input islow. The output is low when the input is high.NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when bothinputs are low and any one of the input is low .The output is low level when bothinputs are high.NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when bothinputs are low. The output is low when one or both inputs are high.X-OR GATE: The output is high when any one of the inputs is high. The output is low whenboth the inputs are low and both the inputs are high. Page No: 5
- 3. DIGITAL ELECTRONICS LABPROCEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.AND GATE:SYMBOL: PIN DIAGRAM:OR GATE: Page No: 6
- 4. DIGITAL ELECTRONICS LABNOT GATE:SYMBOL: PIN DIAGRAM:X-OR GATE :SYMBOL : PIN DIAGRAM : Page No: 7
- 5. DIGITAL ELECTRONICS LAB2-INPUT NAND GATE:SYMBOL: PIN DIAGRAM:3-INPUT NAND GATE : Page No: 8
- 6. DIGITAL ELECTRONICS LABNOR GATE: Page No: 9
- 7. DIGITAL ELECTRONICS LABRESULT: Thus the logic gates are studied and their truth tables are verified.Ex. No: 2 DESIGN OF ADDER AND SUBTRACTORDate:AIM: To design and construct half adder, full adder, half subtractor and fullsubtractor circuits and verify the truth table using logic gates.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. AND GATE IC 7408 1 2. X-OR GATE IC 7486 1 3. NOT GATE IC 7404 1 4. OR GATE IC 7432 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - 23THEORY: Page No: 10
- 8. DIGITAL ELECTRONICS LABHALF ADDER: A half adder has two inputs for the two bits to be added and two outputs onefrom the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Abovecircuit is called as a carry signal from the addition of the less significant bits sumfrom the X-OR Gate the carry out from the AND gate.FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of input; itconsists of three inputs and two outputs. A full adder is useful to add three bits at atime but a half adder cannot do so. In full adder sum output will be taken from X-ORGate, carry output will be taken from OR Gate.HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The halfsubtractor has two input and two outputs. The outputs are difference and borrow. Thedifference can be applied using X-OR Gate, borrow output can be implemented usingan AND Gate and an inverter.FULL SUBTRACTOR: The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a fullsubtractor the logic circuit should have three inputs and two outputs. The two halfsubtractor put together gives a full subtractor .The first half subtractor will be C andA B. The output will be difference output of full subtractor. The expression ABassembles the borrow output of the half subtractor and the second term is the inverteddifference output of first X-OR.LOGIC DIAGRAM:HALF ADDER Page No: 11
- 9. DIGITAL ELECTRONICS LABTRUTH TABLE: A B CARRY SUM 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0K-Map for SUM: K-Map for CARRY: SUM = A’B + AB’ CARRY = ABLOGIC DIAGRAM:FULL ADDER USING TWO HALF ADDER Page No: 12
- 10. DIGITAL ELECTRONICS LABTRUTH TABLE: A B C CARRY SUM 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1K-Map for SUM: K-Map for CARRY:SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + ACLOGIC DIAGRAM:HALF SUBTRACTOR Page No: 13
- 11. DIGITAL ELECTRONICS LABTRUTH TABLE: A B BORROW DIFFERENCE 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0K-Map for DIFFERENCE: K-Map for BORROW: DIFFERENCE = A’B + AB’ BORROW = A’BFULL SUBTRACTOR Page No: 14
- 12. DIGITAL ELECTRONICS LABFULL SUBTRACTOR USING TWO HALF SUBTRACTOR:TRUTH TABLE: A B C BORROW DIFFERENCE 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 Page No: 15
- 13. DIGITAL ELECTRONICS LABK-Map for Difference: K-Map for Borrow:Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’CPROCEEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.RESULT: Thus the half adder, full adder, half subtractor and full subtractor circuitsare designed and the truth tables are verified. Page No: 16
- 14. DIGITAL ELECTRONICS LABEx. No: 3 DESIGN AND IMPLEMENTATION OF CODE CONVERTORDate:AIM: To design and implement 4-bit (i) Binary to gray code converter (ii) Gray to binary code converter (iii) BCD to excess-3 code converter (iv) Excess-3 to BCD code converterAPPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. X-OR GATE IC 7486 1 2. AND GATE IC 7408 1 3. OR GATE IC 7432 1 4. NOT GATE IC 7404 1 5. IC TRAINER KIT - 1 6. PATCH CORDS - 35THEORY: The availability of large variety of codes for the same discrete elements ofinformation results in the use of different codes by different systems. A conversioncircuit must be inserted between the two systems if each uses different codes forsame information. Thus, code converter is a circuit that makes the two systemscompatible even though each uses different binary code. A code converter is a circuit that makes the two systems compatible eventhough each uses a different binary code. To convert from binary code to Excess-3code, the input lines must supply the bit combination of elements as specified bycode and the output lines generate the corresponding bit combination of code. Eachone of the four maps represents one of the four outputs of the circuit as a function ofthe four input variables. Page No: 17
- 15. DIGITAL ELECTRONICS LAB A two-level logic diagram may be obtained directly from the Booleanexpressions derived by the maps. These are various other possibilities for a logicdiagram that implements this circuit.LOGIC DIAGRAM:BINARY TO GRAY CODE CONVERTORK-Map for G3: K-Map for G2: G3 = B3K-Map for G1: K-Map for G0: Page No: 18
- 16. DIGITAL ELECTRONICS LABTRUTH TABLE:| Binary input | Gray code output | B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0LOGIC DIAGRAM:GRAY CODE TO BINARY CONVERTOR Page No: 19
- 17. DIGITAL ELECTRONICS LABTRUTH TABLE:| Gray Code | Binary Code | G3 G2 G1 G0 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1K-Map for B3: K-Map for B2: B3 = G3 Page No: 20
- 18. DIGITAL ELECTRONICS LABK-Map for B1: K-Map for B0:LOGIC DIAGRAM:BCD TO EXCESS-3 CONVERTORK-Map for E3: K-Map for E2:E3 = B3 + B2 (B0 + B1) Page No: 21
- 19. DIGITAL ELECTRONICS LABK-Map for E1: K-Map for E0:TRUTH TABLE:| BCD input | Excess – 3 output | B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 x x x x 1 0 1 1 x x x x 1 1 0 0 x x x x 1 1 0 1 x x x x 1 1 1 0 x x x x 1 1 1 1 x x x x Page No: 22
- 20. DIGITAL ELECTRONICS LABEXCESS-3 TO BCD CONVERTOR:K-Map for A: K-Map for B:A = X1 X2 + X3 X4 X1K-Map for C: K-Map for D: Page No: 23
- 21. DIGITAL ELECTRONICS LABTRUTH TABLE:| Excess – 3 Input | BCD Output | B3 B2 B1 B0 G3 G2 G1 G0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1PROCEDURE: (i) Connections were given as per circuit diagram. (ii) Logical inputs were given as per truth table (iii) Observe the logical output and verify with the truth tables.RESULT: Thus the code converters are designed and verified using truth table. Page No: 24
- 22. DIGITAL ELECTRONICS LABEx. No: 4 DESIGN OF 4-BIT ADDER AND SUBTRACTORDate:AIM: To design and implement 4-bit adder and subtractor using IC 7483.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. IC IC 7483 1 2. EX-OR GATE IC 7486 1 3. NOT GATE IC 7404 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - 40THEORY:4 BIT BINARY ADDER: A binary adder is a digital circuit that produces the arithmetic sum of twobinary numbers. It can be constructed with full adders connected in cascade, with theoutput carry from each full adder connected to the input carry of next full adder inchain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscriptnumbers from right to left, with subscript 0 denoting the least significant bits. Thecarries are connected in chain through the full adder. The input carry to the adder isC0 and it ripples through the full adder to the output carry C4.4 BIT BINARY SUBTRACTOR: The circuit for subtracting A-B consists of an adder with inverters, placedbetween each data input ‘B’ and the corresponding input of full adder. The inputcarry C0 must be equal to 1 when performing subtraction. Page No: 25
- 23. DIGITAL ELECTRONICS LAB4 BIT BINARY ADDER/SUBTRACTOR: The addition and subtraction operation can be combined into one circuit withone common binary adder. The mode input M controls the operation. When M=0, thecircuit is adder circuit. When M=1, it becomes subtractor.4 BIT BCD ADDER: Consider the arithmetic addition of two decimal digits in BCD, together withan input carry from a previous stage. Since each input digit does not exceed 9, theoutput sum cannot be greater than 19, the 1 in the sum being an input carry. Theoutput of two decimal digits must be represented in BCD and should appear in theform listed in the columns. ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2decimal digits, together with the input carry, are first added in the top 4 bit adder toproduce the binary sum.PIN DIAGRAM FOR IC 7483: Page No: 26
- 24. DIGITAL ELECTRONICS LABLOGIC DIAGRAM:4-BIT BINARY ADDERLOGIC DIAGRAM:4-BIT BINARY SUBTRACTOR Page No: 27
- 25. DIGITAL ELECTRONICS LABLOGIC DIAGRAM:4-BIT BINARY ADDER/SUBTRACTOR Page No: 28
- 26. DIGITAL ELECTRONICS LABTRUTH TABLE:LOGIC DIAGRAM:BCD ADDER Input Data A Input Data B Addition Subtraction A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1 1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 Page No: 29
- 27. DIGITAL ELECTRONICS LABK MAP Y = S4 (S3 + S2)TRUTH TABLE: Page No: 30
- 28. DIGITAL ELECTRONICS LAB BCD SUM CARRY S4 S3 S2 S1 C 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1PROCEDURE: (i) Connections were given as per circuit diagram. (ii) Logical inputs were given as per truth table (iii) Observe the logical output and verify with the truth tables.RESULT: Thus the 4-bit adder and subtractor circuits are implemented using IC 7483.Ex. No: 5 Page No: 31
- 29. DIGITAL ELECTRONICS LABDate: DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATORAIM: To design and implement (i) 2 – Bit magnitude comparator using basic gates. (ii) 8 – Bit magnitude comparator using IC 7485.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. AND GATE IC 7408 2 2. X-OR GATE IC 7486 1 3. OR GATE IC 7432 1 4. NOT GATE IC 7404 1 5. 4-BIT MAGNITUDE IC 7485 2 COMPARATOR 6. IC TRAINER KIT - 1 7. PATCH CORDS - 30THEORY: The comparison of two numbers is an operator that determine one number isgreater than, less than (or) equal to the other number. A magnitude comparator is acombinational circuit that compares two numbers A and B and determine theirrelative magnitude. The outcome of the comparator is specified by three binaryvariables that indicate whether A>B, A=B (or) A<B. A = A3 A2 A1 A0 B = B3 B2 B1 B0 The equality of the two numbers and B is displayed in a combinational circuitdesignated by the symbol (A=B). This indicates A greater than B, then inspect the relative magnitude of pairs ofsignificant digits starting from most significant position. A is 0 and that of B is 0. We have A<B, the sequential comparison can be expanded as Page No: 32
- 30. DIGITAL ELECTRONICS LAB A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01 A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0 The same circuit can be used to compare the relative magnitude of two BCDdigits. Where, A = B is expanded as, A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0) x3 x2 x1 x0LOGIC DIAGRAM:2 BIT MAGNITUDE COMPARATORK MAP Page No: 33
- 31. DIGITAL ELECTRONICS LABTRUTH TABLE A1 A0 B1 B0 A>B A=B A<B 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0PIN DIAGRAM FOR IC 7485: Page No: 34
- 32. DIGITAL ELECTRONICS LABLOGIC DIAGRAM:8 BIT MAGNITUDE COMPARATORTRUTH TABLE: A B A>B A=B A<B0000 0000 0000 0000 0 1 00001 0001 0000 0000 1 0 00000 0000 0001 0001 0 0 1PROCEDURE: Page No: 35
- 33. DIGITAL ELECTRONICS LAB (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.RESULT: Thus the 2-bit and 8-bit magnitude comparator circuits are implemented usinglogic gates and IC 7485. Page No: 36
- 34. DIGITAL ELECTRONICS LABEx. No: 6 16 BIT ODD/EVEN PARITY CHECKER /GENERATORDate:AIM: To design and implement 16 bit odd/even parity checker and generator usingIC 74180.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. NOT GATE IC 7404 1 1. PARITY IC IC 74180 2 2. IC TRAINER KIT - 1 3. PATCH CORDS - 30THEORY: A parity bit is used for detecting errors during transmission of binaryinformation. A parity bit is an extra bit included with a binary message to make thenumber is either even or odd. The message including the parity bit is transmitted andthen checked at the receiver ends for errors. An error is detected if the checked paritybit doesn’t correspond to the one transmitted. The circuit that generates the parity bitin the transmitter is called a ‘parity generator’ and the circuit that checks the parity inthe receiver is called a ‘parity checker’. In even parity, the added parity bit will make the total number is even amount.In odd parity, the added parity bit will make the total number is odd amount. Theparity checker circuit checks for possible errors in the transmission. If the informationis passed in even parity, then the bits required must have an even number of 1’s. Anerror occur during transmission, if the received bits have an odd number of 1’sindicating that one bit has changed in value during transmission.PIN DIAGRAM FOR IC 74180: Page No: 37
- 35. DIGITAL ELECTRONICS LABFUNCTION TABLE: INPUTS OUTPUTS Number of High Data PE PO ∑E ∑O Inputs (I0 – I7) EVEN 1 0 1 0 ODD 1 0 0 1 EVEN 0 1 0 1 ODD 0 1 1 0 X 1 1 0 0 X 0 0 1 1LOGIC DIAGRAM:16 BIT ODD/EVEN PARITY CHECKERTRUTH TABLE: Page No: 38
- 36. DIGITAL ELECTRONICS LABI7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 00 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 00 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1LOGIC DIAGRAM:16 BIT ODD/EVEN PARITY GENERATORTRUTH TABLE:I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 01 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 11 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0PROCEDURE: Page No: 39
- 37. DIGITAL ELECTRONICS LAB (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.RESULT: Thus the 16 bit odd/even parity checker and generator circuit designed andimplemented using IC 74180.Ex. No: 7 Page No: 40
- 38. DIGITAL ELECTRONICS LABDate: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXERAIM: To design and implement multiplexer and demultiplexer using logic gates andstudy of IC 74150 and IC 74154.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. 3 I/P AND GATE IC 7411 2 2. OR GATE IC 7432 1 3. NOT GATE IC 7404 1 2. IC TRAINER KIT - 1 3. PATCH CORDS - 32THEORY:MULTIPLEXER: Multiplexer means transmitting a large number of information units over asmaller number of channels or lines. A digital multiplexer is a combinational circuitthat selects binary information from one of many input lines and directs it to a singleoutput line. The selection of a particular input line is controlled by a set of selectionlines. Normally there are 2n input line and n selection lines whose bit combinationdetermine which input is selected.DEMULTIPLEXER: The function of Demultiplexer is in contrast to multiplexer function. It takesinformation from one line and distributes it to a given number of output lines. For thisreason, the demultiplexer is also known as a data distributor. Decoder can also beused as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to allof the AND gates. The data select lines enable only one gate at a time and the data onthe data input line will pass through the selected gate to the associated data outputline. Page No: 41
- 39. DIGITAL ELECTRONICS LABBLOCK DIAGRAM FOR 4:1 MULTIPLEXER:FUNCTION TABLE: S1 S0 INPUTS Y 0 0 D0 → D0 S1’ S0’ 0 1 D1 → D1 S1’ S0 1 0 D2 → D2 S1 S0’ 1 1 D3 → D3 S1 S0 Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0CIRCUIT DIAGRAM FOR MULTIPLEXER:TRUTH TABLE: S1 S0 Y = OUTPUT 0 0 D0 0 1 D1 1 0 D2 1 1 D3 Page No: 42
- 40. DIGITAL ELECTRONICS LABBLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:FUNCTION TABLE: S1 S0 INPUT 0 0 X → D0 = X S1’ S0’ 0 1 X → D1 = X S1’ S0 1 0 X → D2 = X S1 S0’ 1 1 X → D3 = X S1 S0 Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0TRUTH TABLE: INPUT OUTPUT S1 S0 I/P D0 D1 D2 D3 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 Page No: 43
- 41. DIGITAL ELECTRONICS LABLOGIC DIAGRAM FOR DEMULTIPLEXER:TRUTH TABLE: INPUT OUTPUT S1 S0 I/P D0 D1 D2 D3 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1PIN DIAGRAM FOR IC 74150: Page No: 44
- 42. DIGITAL ELECTRONICS LABPIN DIAGRAM FOR IC 74154:PROCEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table. Page No: 45
- 43. DIGITAL ELECTRONICS LABRESULT: Thus the multiplexer and demultiplexer circuits are designed and implementedusing logic gates, IC 74150 and IC 74154.Ex. No: 8 DESIGN AND IMPLEMENTATION OF ENCODER ANDDate: DECODERAIM: To design and implement encoder and decoder using logic gates and study ofIC 7445 and IC 74147.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. 3 I/P NAND GATE IC 7410 2 2. OR GATE IC 7432 3 3. NOT GATE IC 7404 1 2. IC TRAINER KIT - 1 3. PATCH CORDS - 27THEORY:ENCODER: An encoder is a digital circuit that perform inverse operation of a decoder. Anencoder has 2n input lines and n output lines. In encoder the output lines generates thebinary code corresponding to the input value. In octal to binary encoder it has eightinputs, one for each octal digit and three output that generate the correspondingbinary code. In encoder it is assumed that only one input has a value of one at anygiven time otherwise the circuit is meaningless. It has an ambiguila that when all Page No: 46
- 44. DIGITAL ELECTRONICS LABinputs are zero the outputs are zero. The zero outputs can also be generated when D0= 1.DECODER: A decoder is a multiple input multiple output logic circuit which convertscoded input into coded output where input and output codes are different. The inputcode generally has fewer bits than the output code. Each input code word produces adifferent output code word i.e there is one to one mapping can be expressed in truthtable. In the block diagram of decoder circuit the encoded information is present as ninput producing 2n possible outputs. 2n output values are from 0 through out 2n – 1.PIN DIAGRAM FOR IC 7445:BCD TO DECIMAL DECODER:PIN DIAGRAM FOR IC 74147: Page No: 47
- 45. DIGITAL ELECTRONICS LABLOGIC DIAGRAM FOR ENCODER: Page No: 48
- 46. DIGITAL ELECTRONICS LABTRUTH TABLE: INPUT OUTPUTY1 Y2 Y3 Y4 Y5 Y6 Y7 A B C1 0 0 0 0 0 0 0 0 10 1 0 0 0 0 0 0 1 00 0 1 0 0 0 0 0 1 10 0 0 1 0 0 0 1 0 00 0 0 0 1 0 0 1 0 10 0 0 0 0 1 0 1 1 00 0 0 0 0 0 1 1 1 1LOGIC DIAGRAM FOR DECODER:TRUTH TABLE: Page No: 49
- 47. DIGITAL ELECTRONICS LAB INPUT OUTPUT E A B D0 D1 D2 D3 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0PROCEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table. Page No: 50
- 48. DIGITAL ELECTRONICS LABRESULT: Thus the encoder and decoder circuits were designed and implemented usinglogic gates, IC 7445 and IC 74147.Ex. No: 9 CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLEDate: COUNTER AND MOD 10/MOD 12 RIPPLE COUNTERAIM: To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. JK FLIP FLOP IC 7476 2 2. NAND GATE IC 7400 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - 30THEORY: A counter is a register capable of counting number of clock pulse arriving at itsclock input. Counter represents the number of clock pulses arrived. A specifiedsequence of states appears as counter output. This is the main difference between aregister and a counter. In synchronous common clock is given to all flip flop and inasynchronous first flip flop is clocked by external pulse and then each successive flipflop is clocked by Q or Q output of previous stage. Because of inherent propagationdelay time all flip flops are not activated at same time which results in asynchronousoperation.PIN DIAGRAM FOR IC 7476: Page No: 51
- 49. DIGITAL ELECTRONICS LABLOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:TRUTH TABLE: CLK QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0 1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1 Page No: 52
- 50. DIGITAL ELECTRONICS LAB 10 0 1 0 1 11 1 1 0 1 12 0 0 1 1 13 1 0 1 1 14 0 1 1 1 15 1 1 1 1LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:TRUTH TABLE: CLK QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0 1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 Page No: 53
- 51. DIGITAL ELECTRONICS LAB 9 1 0 0 1 10 0 0 0 0LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:TRUTH TABLE: CLK QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 1 0 0 4 0 0 1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 0 0 1 10 0 1 0 1 11 1 1 0 1 12 0 0 0 0 Page No: 54
- 52. DIGITAL ELECTRONICS LABPROCEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.RESULT: Thus the 4 bit ripple counter mod 10/ mod 12 ripple counter circuits weredesigned and verified successfully. Page No: 55
- 53. DIGITAL ELECTRONICS LABEx. No: 10 DESIGN AND IMPLEMENTATION OF 3 BITDate: SYNCHRONOUS UP/DOWN COUNTERAIM: To design and implement 3 bit synchronous up/down counter.APPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. JK FLIP FLOP IC 7476 2 2. 3 I/P AND GATE IC 7411 1 3. OR GATE IC 7432 1 4. XOR GATE IC 7486 1 5. NOT GATE IC 7404 1 6. IC TRAINER KIT - 1 7. PATCH CORDS - 35THEORY: A counter is a register capable of counting number of clock pulse arriving at itsclock input. Counter represents the number of clock pulses arrived. An up/downcounter is one that is capable of progressing in increasing order or decreasing orderthrough a certain sequence. An up/down counter is also called bidirectional counter.Usually up/down operation of the counter is controlled by up/down signal. When thissignal is high counter goes through up sequence and when up/down signal is lowcounter follows reverse sequence.K MAP: Page No: 56
- 54. DIGITAL ELECTRONICS LABSTATE DIAGRAM:CHARACTERISTICS TABLE: Q Qt+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0LOGIC DIAGRAM: Page No: 57
- 55. DIGITAL ELECTRONICS LABTRUTH TABLE: Input Present State Next State A B C Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC 0 0 0 0 1 1 1 1 X 1 X 1 X 0 1 1 1 1 1 0 X 0 X 0 X 1 0 1 1 0 1 0 1 X 0 X 1 1 X 0 1 0 1 1 0 0 X 0 0 X X 1 0 1 0 0 0 1 1 X 1 1 X 1 X 0 0 1 1 0 1 0 0 X X 0 X 1 0 0 1 0 0 0 1 0 X X 1 1 X 0 0 0 1 0 0 0 0 X 0 X X 1 1 0 0 0 0 0 1 0 X 0 X 1 X 1 0 0 1 0 1 0 0 X 1 X X 1 1 0 1 0 0 1 1 0 X X 0 1 X 1 0 1 1 1 0 0 1 X X 1 X 1 1 1 0 0 1 0 1 X 0 0 X 1 X 1 1 0 1 1 1 0 X 0 1 X X 1 1 1 1 0 1 1 1 X 0 X 0 1 X 1 1 1 1 0 0 0 X 1 X 1 X 1PROCEDURE: (i) Connections are given as per circuit diagram. Page No: 58
- 56. DIGITAL ELECTRONICS LAB (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.RESULT: Thus the 3 bit synchronous up/down counter was designed and implementedusing the IC7476.Ex. No: 11 DESIGN AND IMPLEMENTATION OF SHIFT REGISTERDate: Page No: 59
- 57. DIGITAL ELECTRONICS LABAIM: To design and implement (i) Serial in serial out (ii) Serial in parallel out (iii) Parallel in serial out (iv) Parallel in parallel outAPPARATUS REQUIRED: Sl.No. COMPONENT SPECIFICATION QTY. 1. D FLIP FLOP IC 7474 2 2. OR GATE IC 7432 1 3. IC TRAINER KIT - 1 4. PATCH CORDS - 35THEORY: A register is capable of shifting its binary information in one or both directionsis known as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop.All flip flops receive common clock pulses which causes the shift in the output of theflip flop. The simplest possible shift register is one that uses only flip flop.PIN DIAGRAM:LOGIC DIAGRAM:SERIAL IN SERIAL OUT: Page No: 60
- 58. DIGITAL ELECTRONICS LABTRUTH TABLE: Serial in Serial out CLK 1 1 0 2 0 0 3 0 0 4 1 1 5 X 0 6 X 0 7 X 1LOGIC DIAGRAM:SERIAL IN PARALLEL OUT:TRUTH TABLE: OUTPUT Page No: 61
- 59. DIGITAL ELECTRONICS LAB CLK DATA QA QB QC QD 1 1 1 0 0 0 2 0 0 1 0 0 3 0 0 0 1 1 4 1 1 0 0 1LOGIC DIAGRAM:PARALLEL IN SERIAL OUT:TRUTH TABLE: CLK Q3 Q2 Q1 Q0 O/P 0 1 0 0 1 1 1 0 0 0 0 0 2 0 0 0 0 0 3 0 0 0 0 1LOGIC DIAGRAM:PARALLEL IN PARALLEL OUT: Page No: 62
- 60. DIGITAL ELECTRONICS LABTRUTH TABLE: DATA INPUT OUTPUT DA DB DC DD QA QB QC QDCLK 1 1 0 0 1 1 0 0 1 2 1 0 1 0 1 0 1 0PROCEDURE: (i) Connections are given as per circuit diagram. (ii) Logical inputs are given as per circuit diagram. (iii) Observe the output and verify the truth table.RESULT: Thus the shift registers were designed and implemented using IC7474 andverified successfully.Ex. No: 12 SIMULATION OF ADDER AND SUBTRACTOR USINGDate: VERILOG HDL Page No: 63
- 61. DIGITAL ELECTRONICS LABAIM: To write the Verilog HDL program for adder and subtractor circuit andsimulate it using ISE simulator.HARDWARE& SOFTWARE REQUIRED: XILINK 9.1i Simulator PC WITH WINDOWS-XPTHEORY:HALF ADDER: From the verbal explanation of a half adder, we find that this circuit needs twobinary inputs and two binary outputs. The input variables designate the augends andaddend bits; the output variables produce the sum and carry. We assign symbol ‘a’and ‘b’ to the inputs and S (for sum) and C (for carry) to the outputs. The truth tablefor the half adder is listed in table. The C output is 1 only when both inputs are 1.The S output represents the least significant bit of the sum.The simplified Boolean functions for the two outputs can be obtained directly fromthe truth table. The simplified sums of products expressions are S= a’b + ab’ C= abThe logic diagram of the half adder implemented in sum of products is shown infigure. It can be also implemented with an exclusive-OR and an AND gate as shownin figure. This from is used to show that two half adders can be used to construct afull adder.FULL ADDER:A full adder is a combinational circuit that forms the arithmetic sum of three bits. Itconsists of three inputs and two outputs. Two of the input variables, denoted by ‘a’and ‘b’, represent the two significant bits to be added. The third input ‘c’ representsthe carry from the previous lower significant position. Two outputs are necessarybecause the arithmetic sum of three binary digits ranges in value from 0 to 3, andbinary 2 or 3 needs two digits. The two outputs are designated by the symbols S forsum and D for carry. The binary variable S gives the value of the least significant bitof the sum. The binary variable D gives the output carry. The truth table of the fulladder is listed in table. The eight rows under the input variables designate allpossible combinations of the variables. The output variables are determined from thearithmetic sum of the input bits. When all input bits are 0, the output is 0. The S Page No: 64
- 62. DIGITAL ELECTRONICS LABoutput is equal to 1 when only one input is equal to 1 or when all three inputs areequal to 1. The D output has a carry of 1 if two or three inputs are equal to 1.The input and output bits of the combinational circuit different interpretations atvarious stages of the problem. Physically, the binary signals of the inputs areconsidered binary digits to be added arithmetically to form a two-digit sum at theoutput. On the other hand, the same binary values are considered as variables ofBoolean functions when expressed in the truth table or when the circuit isimplemented with logic gates. The maps for the output of the full adder are shown inbelow.HALF ADDER:LOGIC DIAGRAM:TRUTH TABLE: A B CARRY SUM 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0PROGRAM FOR HALF ADDER:module halfadder (sum,carry,a,b); input a,b; Page No: 65
- 63. DIGITAL ELECTRONICS LAB output sum,carry; xor(sum,a,b); and(carry,a,b);endmoduleOUTPUT:FULL ADDER:LOGIC DIAGRAM: Page No: 66
- 64. DIGITAL ELECTRONICS LABTRUTH TABLE: A B C CARRY SUM 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1PROGRAM FOR FULL ADDER:module fulladder(s,cout, a,b,cin); input a,b,cin; output s,cout; wire p,q,r; xor(s,a,b,cin); and(p,a,b); and(q, b,cin); and(r,a,cin); or(cout,p,q,r);endmoduleOUTPUT: Page No: 67
- 65. DIGITAL ELECTRONICS LABHALF SUBTRACTOR:LOGIC DIAGRAM:TRUTH TABLE: A B BORROW DIFFERENCE 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0PROGRAM FOR HALF SUBTRACTOR:module halfsubtractor(diff,borrow, a,b); Page No: 68
- 66. DIGITAL ELECTRONICS LAB input a,b; output diff,borrow; xor(diff,a,b); not(a1,a) and(borrow,a1,b);endmoduleOUTPUT:FULL SUBTRACTOR:LOGIC DIAGRAM:TRUTH TABLE: Page No: 69
- 67. DIGITAL ELECTRONICS LAB A B C BORROW DIFFERENCE 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1PROGRAM FOR FULL SUBTRACTOR:module fullsubtractor(diff,bout, a,b,cin); input a,b,cin; output diff,bout; wire p,q,r; xor(s,a,b,cin); not (a1,a) and(p,a1,b); and(q,b,cin); and(r,a,cin); or(cout,p,q,r);endmoduleOUTPUT:PROCEDURE: Page No: 70
- 68. DIGITAL ELECTRONICS LAB Open project navigator. Go to the file and click the new project Type the project name The “property wizard” is open to check all properties such as product, categories, family, device etc. then click next Create new source wizard appears then click next Project summary is displayed then click next Go to the project and click “new source” Then type the module name as well as select verilog module then click next “Define module window” here we assign the input and output of half adder, clicks next and click finish Type the program and save it Make sure that the source is in “BEHAVIOURAL SIMULATION” Then click the ISE simulator and view the signal window Force the input data corresponding circuit Simulate the program using ISE simulatorRESULT: Thus the Verilog HDL program for adder and subtractor are written andsimulated using ISE simulator. Page No: 71
- 69. DIGITAL ELECTRONICS LABEx. No: 13 SIMULATION OF MULTIPLEXER AND DE-MULTIPLEXERDate: USING VERILOG HDLAIM: To write the Verilog HDL program for multiplexer and de-multiplexer circuitand simulate it using ISE simulator.HARDWARE& SOFTWARE REQUIRED: XILINK 9.1i Simulator PC WITH WINDOWS-XPTHEORY:MULTIPLEXER: A digital multiplexer is a combinational circuit that selects binary informationfrom one of many input lines and directs it to a single output line. The selection of aparticular input line is controlled by a set of selection lines. Normally, there are 2^ninputs lines and n selection lines whose bit combinations determine which input isselected. In a 4 to 1 line multiplexer, the four input lines, I0 to I3 is applied to one inputof an AND gate. Selection lines S1 and S0 are decoded to select a particular ANDgate. A multiplexer is also called a data selector, since it selects one of many inputsand steers the binary information to the output line.DEMULTIPLEXER: The demultiplexer does the reverse operation of a multiplexer. It can be usedto separate the multiplexed signal into individual signals, The select input codedetermines to which output the data input will be transmitted. The number of outputlines is n and the number of select lines is m, where n=2^m. The input data istransmitted to one of the output di by means of select signals a,b. The 4-bit adderadds the input a & b and produces the 4-bit sum as the output. Page No: 72
- 70. DIGITAL ELECTRONICS LABLOGIC DIAGRAM FOR MULTIPLEXER:TRUTH TABLE: S1 S0 Y = OUTPUT 0 0 D0 0 1 D1 1 0 D2 1 1 D3PROGRAM FOR MULTIPLEXER: Page No: 73
- 71. DIGITAL ELECTRONICS LABmodule mux(f,d0,d1,d2,d3,s0,s1); input d0,d1,d2,d3,s0,s1; output f; wire ns1,ns0,p,q,r,s; not (ns1,s1); not(ns0,s0); and(p,ns0,ns1,i0); and(q,s0,ns1,i1); and(r,ns0, s1,i2); and(s,s0, s1,i3); or(f,p,q,r,s);endmoduleOUTPUT:LOGIC DIAGRAM FOR DEMULTIPLEXER: Page No: 74
- 72. DIGITAL ELECTRONICS LABTRUTH TABLE: INPUT OUTPUT S1 S0 I/P D0 D1 D2 D3 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1PROGRAM FOR DE-MULTIPLEXER:module demux(do,d1,d2,d3, a,b,s); input a,b,s; Page No: 75
- 73. DIGITAL ELECTRONICS LAB output d0,d1,d2,d3; wire a1,b1; not (a1,a); not(b1,b); and(d0,b1,a1,s); and(d1,b,a1,s); and(d2,b1,a,s); and(d3,b,a,s);endmoduleOUTPUT:PROCEDURE: Open project navigator. Go to the file and click the new project Page No: 76
- 74. DIGITAL ELECTRONICS LAB Type the project name The “property wizard” is open to check all properties such as product, categories, family, device etc. then click next Create new source wizard appears then click next Project summary is displayed then click next Go to the project and click “new source” Then type the module name as well as select verilog module then click next “Define module window” here we assign the input and output of half adder, clicks next and click finish Type the program and save it Make sure that the source is in “BEHAVIOURAL SIMULATION” Then click the ISE simulator and view the signal window Force the input data corresponding circuit Simulate the program using ISE simulatorRESULT: Thus the Verilog HDL program for multiplexer and de-multiplexer are writtenand simulated using ISE simulator. Page No: 77

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