134 138


Published on

Published in: Technology, Business
  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

134 138

  1. 1. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering (IJARCSEE) Volume 1, Issue 6, August 2012 Design Of High Speed Gray To Binary Code Converter Using A Novel Two Transistor XOR Gate 1 2 3 Pakkiraiah chakali Naveen Kumar T Serinth MAbstract—In modern era, Ultra low power so these are not suitable for small and lowdesign has an Active research topic due to price systems. The power consumptionits various Applications. In this paper we techniques are CMOS complementary logic,introduce a novel low power and Area Pseudo NMOS[3], Dynamic CMOS[7],efficient Gray to Binary code converter is Clocked CMOS logic (C2MOS), CMOSimplemented by using two transistor Domino logic, Cascade voltage switch logicXOR gate. This two Transistor XOR gate (CVSL)[9], Modified Domino logic, Passis designed by using two PMOS Transistor Logic (PTL)[8].The most usefultransistors. Both two transistor and Gray low power consumption technique isto Binary code converter is designed and PTL.The PTL advantages are,implemented by using Mentor Graphics 1) High speed, due to small nodeTool. So we were obtained the power capacitances.dissipation of Gray to Binary code 2) Low power dissipation [4], as a result ofconverter which is very small and area reduced number of transistors.required to this Gray to Binary code 3) Lower interconnection effect, due toconverter is also very small. smaller area. There are two main drawbacksKeywords—Low Power, OR, Binary in PTL,code, Gray code, Area. 1) The threshold voltage across the single channel pass transistors results in reduced I INTRODUCTION drive and hence slower operation at reduced voltages.The design of code converters[12] which 2) The high input voltage level is not VDDforms the basic building blocks of all digital the PMOS device in inverter is not fullyVLSI circuits has been undergoing a turned off.considerable improvement, being motivated In order to overcome these drawbacks weby basic design goals, viz. minimizing the use Transmission Gate (TG) logic.transistor count, minimizing the power The main advantage of the TG logic isconsumption[5].The XOR gates form the complex logic functions are implemented byfundamental building block of code using small number of transistors. Anotherconverters. Enhancing the performance of advantage is logic level swing can bethe XOR gates can significantly improve the reduced by using PTL.The combination ofperformance of the code converters. NMOS PT with CMOS output inverters is called Complementary pass transistor logicDifferent types of XOR [2] gates that have (CPL).It suffers from the static power andbeen realized over the years. The code low swing at gates of the output inverters.converters [13],[16] are more complex and To reduce the static power dissipation andpower consuming circuits in digital design. full swing operation we use the Double passTo reduce the power dissipation several transistor logic (DPL). Double passcode converters are designed but they are transistor logic (DPL) has more area due tonot suitable for operation in the sub presence of PMOS transistor.threshold region. These designs requiremore transistors leads to area is increasing, . 134 All Rights Reserved © 2012 IJARCSEE
  2. 2. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering (IJARCSEE) Volume 1, Issue 6, August 2012 II. IMPLEMENTATION OF EX-OR code tables in octal, decimal or hexadecimalThe basic building gate of Gray to Binary notation.code converter is EX-OR[1].Theimplementation of EX-OR gate using two The reflected binary code, also known asPMOS transistors is shown in figure2.The Gray code [17].It is a binary numeral systemdesign and implementation of EX-OR gate where two successive values differ in onlyusing two PMOS transistors is dissipates one bit. It is a non-weighted code. Theless power and it requires less are. reflected binary code was originally designed to prevent spurious output from electromechanical switches. Today, Gray codes [18] are widely used to facilitate error correction in digital communications such as digital terrestrial television and some cable TV systems. Patent applications give "Gray code" as an alternative name for the "reflected binary code". One of those also lists "minimum error code" and "cyclic permutation code" among the names. The problem with natural binary codes is that, with real (mechanical) switches, it is very unlikely that switches will change states exactly in synchrony. In the transition Fig 2. XOR cell with the two PMOS between the two states shown above, all transistors three switches change state. In the brief period while all are changing, the switchesIII. IMPLEMENTATION OF GRAY TO will read some spurious position. Even BINARY CODE without key bounce, the transition might look like 011 — 001 — 101 — 100. WhenA binary code [14] is a way of representing the switches appear to be in position 001,text or computer processor instructions by the observer cannot tell if that is the "real"the use of the binary number systems two- position 001, or a transitional state betweenbinary digits 0 and 1. This is accomplished two other positions. If the output feeds into aby assigning a bit string to each particular sequential system (possibly viasymbol or instruction. For example, a binary combinational logic) then the sequentialstring of eight binary digits (bits) can system may store a false value. The reflectedrepresent any of 256 possible values and can binary code solves this problem by changingtherefore correspond to a variety of different only one switch at a time, so there is neversymbols, letters or instructions. In any ambiguity of position.computing and telecommunication, binarycodes[15] are used for any of a variety of Decimal Gray Binarymethods of encoding data, such as character number code number 0 000 000strings, into bit strings. Those methods may 1 001 001be fixed-width or variable-width. In a fixed- 2 011 010width binary code, each letter, digit, or other 3 010 011character, is represented by a bit string of 4 110 100the same length; that bit string, interpreted 5 111 101as a binary number, is usually displayed in 6 101 110 7 100 111 135 All Rights Reserved © 2012 IJARCSEE
  3. 3. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering (IJARCSEE) Volume 1, Issue 6, August 2012More formally, a Gray code is a code converter are designed. After that we wereassigning to each of a contiguous set of simulated these designs. By using simulationintegers, or to each member of a circular list, results we got the values of rise time, falla word of symbols such that each two time, delay, power dissipation and we wereadjacent code words differ by one symbol. taken the input and output simulatedThese codes are also known as single- waveforms. The simulated waveforms aredistance codes, reflecting the Hamming shown in figure4-5.The power dissipationdistance of 1 between adjacent codes. There and transistor count is shown in table2.can be more than one Gray code[18] for agiven word length, but the term was firstapplied to a particular binary code for thenon- negative integers, the binary-reflectedGray code, or BRGC, the three-bit versionof which is shown above. Fig.4.waveforms at 5v and 66MHZ of XOR Fig.5.waveforms at 5v and 66MHZ of Gray to Binary Code . Table.2 comparison of Code Converters (Power, Number of Transistors). Circuit No Power Transistors (w) Binary to 6 195.8P Fig. 3. Design of Gray to Binary Code two Gray PMOS transistors EX-OR 2 63.31P IV. RESULTS AND SIMULATIONThe Gray to Binary code converter operatesin 66 MHz range. In Mentor Graphics Toolboth EX-OR and Gray to Binary code 136 All Rights Reserved © 2012 IJARCSEE
  4. 4. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering (IJARCSEE) Volume 1, Issue 6, August 2012 V. CONCLUSION [6] H. P. Alstead and S. Aunet, "Seven sub threshold flip-flops cells," in Proc. IEEEA new technique, two PMOS transistors Nor CHIP 2007, Nov. 2007, pp. 1-4.technique has been adopted for reducing the [7] N. Weste and K. Eshraghian Principlestransistor count with full swing. The two of CMOS digital design.PMOS transistors have been implemented in [8] W. Al-Assadi, A. P. Jayasumana, and Y.Code Converters and the comparison results K. Malaiya, ―Pass-transistor logic design,‖have been shown. The performance metrics Int. J. Electron., vol. 70, pp. 739–749, 1991.like area, power, delay and transistor count [9] I. S. Abu-Khater, A. Bellaouar, and M. I.are compared with the previous CMOS logic Elmastry, ―Circuit techniques for CMOSdesign families. The implementation of Gray low-power high-performance multipliers,‖to Binary Code Converter has been IEEE J. Solid-State Circuits, vol. 31, pp.presented in two PMOS transistors are three 1535–1546, Oct. 1996.and can be extended to other codes. The [10] A. Morgenshtein, A. Fish, I.A. Wagner,future research activities may include ―Gate-Diffusion Input (GDI) – A Powerintegration of the proposed Gray to Binary Efficient Method for Digital CombinationalCode in complex digital systems, digital Circuits,‖ IEEE Trans. VLSI, vol.10, no.5communication systems and pp.566-581, October 2002.telecommunications. [11] A. Morgenstein, A. Fish, I. Wagner, ―An Efficient Implementation of D-Flip- Flop Using the GDI Technique,‖ ISCAS REFERENCES ‟04, pp. 673-676, May 2004. [12] M. Morris Mano and Michael D.Ciletti,[1] Pakkiraiah Chakali,Design of High ―Digital Design‖.Speed Six Transistor Full Adder using a [13] Table of general binary codes. AnNovel Two Transistor XOR Gates, updated version of the tables of bounds forIJARCSEE ISSN: 2277 – 9043. small general binary codes given in M.R.[2] Pakkiraiah Chakali, A Novel Low power Best, A.E. Brouwer, F.J. MacWilliams,and Area efficient Carry Look Ahead Adder A.M. Odlyzko & N.J.A. Sloane (1978),Using GDI Technique, IJRCET "Bounds for Binary Codes of Length Less[3] Jan M. Rabaey, Anantha Chandrakasan than 25", IEEE Trans. Inf. Th. 24: 81–93.and Borivoje Nikolic, ―Digital IntegratedCircuits- A Design Perspective‖,2 nd ed., [14] Table of Nonlinear Binary Codes.Prentice Hall of India Pvt Ltd, New Maintained by Simon Litsyn, E. M. Rains,Delhi,2006. and N. J. A. Sloane.[4] A. P. Chandrakasan, S. Sheng, and R. W.Brodersen, ―Low-power CMOS digital [15]Glaser, Anton (1971). "Chapter VIIdesign‖. IEEE J. Solid-State Circuits, vol. Applications to Computers". History of27, pp. 473-484, Apr. 1992.W.-K. Chen, Binary and other Nondecimal Numeration.Linear Networks and Systems (Book style). Tomash. ISBN 0-938228-00-5. Cites someBelmont, CA: Wadsworth, 1993, pp. 123– pre-ENIAC milestones.135.[5] A. P. Chandrakasan and R.W.Brodersen, ―Minimizing power consumption [16] Black, Paul E. Gray code. 25 Februaryin digital CMOS circuits‖. Proc. IEEE, vol. 2004. NIST.83, pp. 498–523, Apr. 1995. 137 All Rights Reserved © 2012 IJARCSEE
  5. 5. ISSN: 2277 – 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering (IJARCSEE) Volume 1, Issue 6, August 2012[17] Press, WH; Teukolsky, SA; Vetterling, Engineering College, Tirupati, AndhraWT; Flannery, BP (2007). "Section 22.3. Pradesh, India. His interest includes DigitalGray Codes". Numerical Recipes: The Art Design, FPGA Design.of Scientific Computing (3rd ed.). NewYork: Cambridge University Press.ISBN 978-0-521-88068-8.[18] Savage, Carla (1997). "A Survey ofCombinatorial Gray Codes". SIAM Rev. 39(4):605629doi:10.1137/S0036144595295272. JSTOR 2132693. M Serinth completed his B.Tech in Electronics and Communication Engineering from Narayana Engineering college, Gudur, Nellore, Andhra Pradesh, India in 2010. he is now pursuing his Master of Technology (M.Tech) in VLSI at Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, India. His interest C.Pakkiraiah completed his includes Digital Design, Verilog Coding.B.Tech in Electronics and CommunicationEngineering from Sreenivasa Institute ofTechnology and management studies,Chittoor, Andhra Pradesh, India in 2009. Heis now pursuing his Master of Technology(M.Tech) in VLSI at Sree VidyanikethanEngineering College , Tirupati, AndhraPradesh, India. His interest includes DigitalDesign, ASIC Design, VLSI Testing. T Naveen Kumarcompleted his B.Tech in Electronics andCommunication Engineering fromVisvesvaraya Technological University,Belguan, Karnataka, India in 2010. He isnow pursuing his Master of Technology(M.Tech) in VLSI at Sree Vidyanikethan 138 All Rights Reserved © 2012 IJARCSEE