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Digital computer architecture issues in IO

The document discusses digital computer architecture, focusing on input/output systems, buses, and their various types, including processor-memory and I/O buses. It highlights the advantages and disadvantages of bus systems, describes bus transaction dynamics, and addresses bus arbitration schemes. Additionally, it touches on modern integration concepts like the system-on-a-chip and the open core protocol for efficient communication in complex systems.

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1 204521 Digital Computer Architecture Lecture 10b I/O Introduction: Storage Devices, Metrics, & Productivity Pradondet Nilagupta Original note from Professor David A. Patterson Spring 2001
2 204521 Digital Computer Architecture Storage System Issues • Historical Context of Storage I/O • Secondary and Tertiary Storage Devices • Storage I/O Performance Measures • Processor Interface Issues • A Little Queuing Theory • Redundant Arrarys of Inexpensive Disks (RAID) • I/O Buses
3 204521 Digital Computer Architecture A Communication-Centric World • Computation is getting distributed … – Internet, WAN, LAN, BodyLAN, Home Networks, Microprocessor Peripherals, Processor-Memory Interface, System-on-a-Chip • Efficient Networking and Communication is Crucial • The System-on-a-Chip implies the Network- on-a-Chip • In Next Set of Lectures: – Busses and Networks – But more importantly, the impact of integration
4 204521 Digital Computer Architecture A Bus Is: • shared communication link • single set of wires used to connect multiple subsystems • A Bus is also a fundamental tool for composing large, complex systems – systematic means of abstraction Control Datapath Memory Processor Input Output What is a bus?
5 204521 Digital Computer Architecture Busses
6 204521 Digital Computer Architecture • Versatility: – New devices can be added easily – Peripherals can be moved between computer systems that use the same bus standard • Low Cost: – A single set of wires is shared in multiple ways Memory Processe r I/O Device I/O Device I/O Device Advantages of Buses
7 204521 Digital Computer Architecture • It creates a communication bottleneck – The bandwidth of that bus can limit the maximum I/O throughput • The maximum bus speed is largely limited by: – The length of the bus – The number of devices on the bus – The need to support a range of devices with: • Widely varying latencies • Widely varying data transfer rates Memor y Processo r I/O Device I/O Device I/O Device Disadvantage of Buses
8 204521 Digital Computer Architecture • Control lines: – Signal requests and acknowledgments – Indicate what type of information is on the data lines • Data lines carry information between the source and the destination: – Data and Addresses – Complex commands Data Lines Control Lines General Organization of a Bus
9 204521 Digital Computer Architecture • A bus transaction includes two parts: – Issuing the command (and address) – request – Transferring the data – action • Master is the one who starts the bus transaction by: – issuing the command (and address) • Slave is the one who responds to the address by: – Sending data to the master if the master ask for data – Receiving data from the master if the master wants to send data Bus Master Bus Slave Master issues command Data can go either way Master versus Slave
10 204521 Digital Computer Architecture Types of Busses • Processor-Memory Bus (design specific) – Short and high speed – Only need to match the memory system • Maximize memory-to-processor bandwidth – Connects directly to the processor – Optimized for cache block transfers • I/O Bus (industry standard) – Usually is lengthy and slower – Need to match a wide range of I/O devices – Connects to the processor-memory bus or backplane bus • Backplane Bus (standard or proprietary) – Backplane: an interconnection structure within the chassis – Allow processors, memory, and I/O devices to coexist – Cost advantage: one bus for all components
11 204521 Digital Computer Architecture Processor/Memory Bus PCI Bus I/O Busses Example: Pentium System Organization
12 204521 Digital Computer Architecture A Computer System with One Bus: Backplane Bus • A single bus (the backplane bus) is used for: – Processor to memory communication – Communication between I/O devices and memory • Advantages: Simple and low cost • Disadvantages: slow and the bus can become a major bottleneck • Example: IBM PC - AT Processor Memory I/O Devices Backplane Bus
13 204521 Digital Computer Architecture A Two-Bus System • I/O buses tap into the processor-memory bus via bus adaptors: – Processor-memory bus: mainly for processor-memory traffic – I/O buses: provide expansion slots for I/O devices • Apple Macintosh-II – NuBus: Processor, memory, and a few selected I/O devices – SCCI Bus: the rest of the I/O devices Processor Memory I/O Bus Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus
14 204521 Digital Computer Architecture A Three-Bus System • A small number of backplane buses tap into the processor-memory bus – Processor-memory bus is only used for processor-memory traffic – I/O buses are connected to the backplane bus • Advantage: loading on the processor bus is greatly reduced Processor Memory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus
15 204521 Digital Computer Architecture North/South Bridge architectures: separate busses • Separate sets of pins for different functions – Memory bus – Caches – Graphics bus (for fast frame buffer) – I/O busses are connected to the backplane bus • Advantage: – Busses can run at different speeds – Much less overall loading! Processor Memory Processor Memory Bus Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus “backside cache”
16 204521 Digital Computer Architecture Bunch of Wires Physical / Mechanical Characteristics – the connectors Electrical Specification Timing and Signaling Specification Transaction Protocol What defines a bus?
17 204521 Digital Computer Architecture • Synchronous Bus: – Includes a clock in the control lines – A fixed protocol for communication that is relative to the clock – Advantage: involves very little logic and can run very fast – Disadvantages: • Every device on the bus must run at the same clock rate • To avoid clock skew, they cannot be long if they are fast • Asynchronous Bus: – It is not clocked – It can accommodate a wide range of devices – It can be lengthened without worrying about clock skew – It requires a handshaking protocol Synchronous and Asynchronous Bus
18 204521 Digital Computer Architecture ° ° ° Master Slave Control Lines Address Lines Data Lines Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. Busses so far
19 204521 Digital Computer Architecture Bus Transaction • Arbitration: Who gets the bus • Request: What do we want to do • Action: What happens in response
20 204521 Digital Computer Architecture • One of the most important issues in bus design: – How is the bus reserved by a device that wishes to use it? • Chaos is avoided by a master-slave arrangement: – Only the bus master can control access to the bus: It initiates and controls all bus requests – A slave responds to read and write requests • The simplest system: – Processor is the only bus master – All bus requests must be controlled by the processor – Major drawback: the processor is involved in every transaction Bus Master Bus Slave Control: Master initiates requests Data can go either way Arbitration: Obtaining Access to the Bus
21 204521 Digital Computer Architecture Multiple Potential Bus Masters: the Need for Arbitration • Bus arbitration scheme: – A bus master wanting to use the bus asserts the bus request – A bus master cannot use the bus until its request is granted – A bus master must signal to the arbiter the end of the bus utilization • Bus arbitration schemes usually try to balance two factors: – Bus priority: the highest priority device should be serviced first – Fairness: Even the lowest priority device should never be completely locked out from the bus • Bus arbitration schemes can be divided into four broad classes: – Daisy chain arbitration – Centralized, parallel arbitration – Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. – Distributed arbitration by collision detection: Each device just “goes for it”. Problems found after the fact.
22 204521 Digital Computer Architecture The Daisy Chain Bus Arbitrations Scheme • Advantage: simple • Disadvantages: – Cannot assure fairness: A low-priority device may be locked out indefinitely – The use of the daisy chain grant signal also limits the bus speed Bus Arbiter Device 1 Highes t Priorit y Device N Lowest Priority Device 2 Grant Grant Grant Release Request wired-OR
23 204521 Digital Computer Architecture • Used in essentially all processor-memory busses and in high-speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req Centralized Parallel Arbitration
24 204521 Digital Computer Architecture • All agents operate synchronously • All can source / sink data at same rate • => simple protocol – just manage the source and target Simplest bus paradigm
25 204521 Digital Computer Architecture • Even memory busses are more complex than this – memory (slave) may take time to respond – it may need to control data rate BReq BG Cmd+Addr R/W Address Data1 Data2 Data Simple Synchronous Protocol
26 204521 Digital Computer Architecture • Slave indicates when it is prepared for data xfer • Actual transfer goes at bus rate BReq BG Cmd+Addr R/W Address Data1 Data2 Data Data1 Wait Typical Synchronous Protocol
27 204521 Digital Computer Architecture • Separate versus multiplexed address and data lines: – Address and data can be transmitted in one bus cycle if separate address and data lines are available – Cost: (a) more bus lines, (b) increased complexity • Data bus width: – By increasing the width of the data bus, transfers of multiple words require fewer bus cycles – Example: SPARCstation 20’s memory bus is 128 bit wide – Cost: more bus lines • Block transfers: – Allow the bus to transfer multiple words in back-to-back bus cycles – Only one address needs to be sent at the beginning – The bus is not released until the last word is transferred – Cost: (a) increased complexity (b) decreased response time for request Increasing the Bus Bandwidth
28 204521 Digital Computer Architecture • Overlapped arbitration – perform arbitration for next transaction during current transaction • Bus parking – master holds onto bus and performs multiple transactions as long as no other master makes request • Overlapped address / data phases – requires one of the above techniques • Split-phase (or packet switched) bus – completely separate address and data phases – arbitrate separately for each – address phase yield a tag which is matched with data phase • ”All of the above” in most modern memory buses Increasing Transaction Rate on Multimaster Bus
29 204521 Digital Computer Architecture Bus MBus Summit Challenge XDBus Originator Sun HP SGI Sun Clock Rate (MHz) 40 60 48 66 Address lines 36 48 40 muxed Data lines 64 128 256 144 (parity) Data Sizes (bits) 256 512 1024 512 Clocks/transfer 4 5 4? Peak (MB/s) 320(80) 960 1200 1056 Master Multi Multi Multi Multi Arbitration Central Central Central Central Slots 16 9 10 Busses/system 1 1 1 2 Length 13 inches 12? inches 17 inches 1993 CPU- Memory Bus Survey
30 204521 Digital Computer Architecture Address Data Read Req Ack Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 • t0 : Master has obtained control and asserts address, direction, data • Waits a specified amount of time for slaves to decode target • t1: Master asserts request line • t2: Slave asserts ack, indicating data received • t3: Master releases req • t4: Slave releases ack Asynchronous Handshake (4- phase)
31 204521 Digital Computer Architecture Address Data Read Req Ack Master Asserts Address Next Address t0 t1 t2 t3 t4 t5 • t0 : Master has obtained control and asserts address, direction, data • Waits a specified amount of time for slaves to decode target • t1: Master asserts request line • t2: Slave asserts ack, indicating ready to transmit data • t3: Master releases req, data received • t4: Slave releases ack Read Transaction Slave Data
32 204521 Digital Computer Architecture Bus SBus TurboChannel MicroChannel PCI Originator Sun DEC IBM Intel Clock Rate (MHz) 16-25 12.5-25 async 33 Addressing Virtual Physical Physical Physical Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64 Master Multi Single Multi Multi Arbitration Central Central Central Central 32 bit read (MB/s) 33 25 20 33 Peak (MB/s) 89 84 75 111 (222) Max Power (W) 16 26 13 25 1993 Backplane/IO Bus Survey
33 204521 Digital Computer Architecture • Examples – graphics – fast networks • Limited number of devices • Data transfer bursts at full rate • DMA transfers important – small controller spools stream of bytes to or from memory • Either side may need to squelch transfer – buffers fill up High Speed I/O Bus
34 204521 Digital Computer Architecture • All signals sampled on rising edge • Centralized Parallel Arbitration – overlapped with previous transaction • All transfers are (unlimited) bursts • Address phase starts by asserting FRAME# • Next cycle “initiator” asserts cmd and address • Data transfers happen on when – IRDY# asserted by master when ready to transfer data – TRDY# asserted by target when ready to transfer data – transfer when both asserted on rising edge • FRAME# deasserted when master intends to complete only one more data transfer PCI Read/Write Transactions
35 204521 Digital Computer Architecture – Turn-around cycle on any signal driven by more than one agent PCI Read Transaction
36 204521 Digital Computer Architecture PCI Write Transaction
37 204521 Digital Computer Architecture The System-on-a-Chip Nightmare Bridge DMA CPU DSP Mem Ctrl. MPEG C I O O System Bus Peripheral Bus Control Wires Custom Interfaces The “Board-on-a-Chip Approach
38 204521 Digital Computer Architecture Sonics SOC Integration Architecture SiliconBackplane Agent™ Open Core Protocol™ SiliconBackplane™ (patented) MultiChip Backplane™ { DSP MPEG CPU DMA C MEM I O
39 204521 Digital Computer Architecture Open Core Protocol Goals • Bus Independent • Scalable • Configurable • Synthesis/Timing Analysis Friendly • Encompass entire core/system interface needs (data, control, and test flows)
40 204521 Digital Computer Architecture Data, Control, and Test Flows • Data Flow – Signals and protocols associated with moving data – Includes address, data, handshaking, etc. – Similar to services provided by traditional computer buses • Control Flow – Signals and protocols associated with non-data communication – Sideband - not synchronized to data flow (out of band) – Examples include interrupts, high-level flow control, etc. • Test Flow – Signals and protocols related to debug and manufacturing test
41 204521 Digital Computer Architecture OCP Overview • Point-to-point, uni-directional, synchronous – easy physical implementation • Master/Slave, request/response – well-defined, simple roles • Extensions – added functionality to support cores with more complex interface requirements • Configurability – pay only for the features needed for a given core
42 204521 Digital Computer Architecture Master vs. Slave IP Core IP Core IP Core On-Chip Bus Slave Master Slave Slave Slave Master Master Master Initiator Target Open Core Protocol Request Response
43 204521 Digital Computer Architecture Basic OCP Master MCmd [3] MAddr [N] MData [N] SResp [3] SData [N] Clk SCmdAccept Read: Command, Address Command Accept Response, Data Write (posted): Command, Address, Data MCmd, MAddr SCmdAccept SResp, SData MCmd, Maddr, MData SCmdAccept Slave
44 204521 Digital Computer Architecture Protocol Phases • Request Phase (begins Transfer) – Master presents request (command, address, etc.) to Slave • Response Phase (ends Transfer) – Slave presents response (success/fail, read data) to Master – Only available for read transfers (posted write model) • Datahandshake Phase (Optional) – Allows pipelining request ahead of write data – Only available for write transfers • Phase ordering – Request -> Datahandshake -> Response
45 204521 Digital Computer Architecture OCP Extensions • Simple Extensions – Byte Enables – Bursts – Flow Control – Data Handshake • Complex Extensions – Threads and Connections • Sideband Signals
46 204521 Digital Computer Architecture The Backplane: Why Not Use a Computer Bus? IP Core IP Core    IP Core IP Core    Computer Bus Transmit FIFO Receive FIFO Time Data Arbiter Address •Expensive to decouple •Not designed for real-time
47 204521 Digital Computer Architecture Communication Buses Decouple and Guarantee Real Time IP Core IP Core    IP Core IP Core    Communications Bus Transmit FIFO Receive FIFO Time Data TDMA TDMA •Connections are expensive •Poor read latency
48 204521 Digital Computer Architecture From Communications • Efficient BW decoupling • Guaranteed BW & latency • Side-band signaling SiliconBackplane™ Employs Best of Both From Computing • Address-based selection • Write and read transfers • Pipelining DSP MPEG CPU DMA C MEM I O
49 204521 Digital Computer Architecture Guaranteed Bandwidth Arbitration • Independent arbitration for every cycle includes two phases: -Distributed TDMA -Round robin • Provides fine control over system bandwidth Current Slot Arbitration Command
50 204521 Digital Computer Architecture Guaranteed Latency • Fixed latency between command/address and data/response phases • Matches pipelined CPU model ensuring high performance access to on-chip resources • Pipelined data routed through SiliconBackplane™ • Latency re-programmable in software • Variable-latency blocks do not tie up the SiliconBackplane
52 204521 Digital Computer Architecture Integrated Signaling Mechanism • Dedicated SiliconBackplane™ wires (Flags) support: – Bus-style out-of-band signaling (interrupts) – Point-to-point communications (flow control) – Dynamic point-to-point (retry mechanism) • Same design flow, timing, flexibility as address/data portion of SonicsIA™
53 204521 Digital Computer Architecture MultiChip Backplan SiliconBackplane MultiChip Backplane™ Extends SonicsIA™ Between Chips CPU-Based ASSP ASSP FPGA Seamless integration of protocols
54 204521 Digital Computer Architecture Validation / Test • SiliconBackplane™ highly visible for test – All subsystems communicate through SiliconBackplane • Test Interfaces: – MultiChip Backplane: 100’s MB/sec. – ServiceAgent: Scan-based • Each subsystem can be tested/validated stand-alone Test Vectors Test Vectors MultiChip Backplane™
55 204521 Digital Computer Architecture Summary • Busses are an important technique for building large-scale systems – Their speed is critically dependent on factors such as length, number of devices, etc. – Critically limited by capacitance – Tricks: esoteric drive technology such as GTL • Important terminology: – Master: The device that can initiate new transactions – Slaves: Devices that respond to the master • Two types of bus timing: – Synchronous: bus includes clock – Asynchronous: no clock, just REQ/ACK strobing • System-on-a-Chip approach invites new solutions – Well-defined and clear communication protocols – Physical layer hidden to designer
56 204521 Digital Computer Architecture Interconnect Trends Network >1000 m 10 - 100 Mb/s high (>ms) low Extensive CRC Channel 10 - 100 m 40 - 1000 Mb/s medium medium Byte Parity Backplane 1 m 320 - 1000+ Mb/s low (<µs) high Byte Parity Distance Bandwidth Latency Reliability • Interconnect = glue that interfaces computer system components • High speed hardware interfaces + logical protocols • Networks, channels, backplanes memory-mapped wide pathways centralized arb message-based narrow pathways distributed arb
57 204521 Digital Computer Architecture Backplane Architectures 128 No 16 - 32 Single/Multiple Multiple No Async 25 12.9 27.9 13.6 21 .5 m IEEE 1014 96 Yes 32 Single/Multiple Multiple Optional Async 37 15.5 95.2 20.8 20 .5 m IEEE 896 Metric VME FutureBus 96 Yes 32 Single/Multiple Multiple Optional Sync 20 10 40 13.3 21 .5 m ANSI/IEEE 1296 MultiBus II Bus Width (signals) Address/Data Multiplexed? Data Width Xfer Size # of Bus Masters Split Transactions Clocking Bandwidth, Single W ord (0 ns mem) Bandwidth, Single W ord (150 ns mem) Bandwidth Multiple W ord (0 ns mem) Bandwidth Multiple W ord (150 ns mem) Max # of devices Max Bus Length Standard 25 na 8 Single/Multiple Multiple Optional Either 5, 1.5 5, 1.5 5, 1.5 5, 1.5 7 25 m ANSI X3.131 SCSI-I Distinctions begin to blur: SCSI channel is like a bus FutureBus is like a channel (disconnect/reconnect) HIPPI forms links in high speed switching fabrics
58 204521 Digital Computer Architecture Bus-Based Interconnect • Bus: a shared communication link between subsystems – Low cost: a single set of wires is shared multiple ways – Versatility: Easy to add new devices & peripherals may even be ported between computers using common bus • Disadvantage – A communication bottleneck, possibly limiting the maximum I/O throughput • Bus speed is limited by physical factors – the bus length – the number of devices (and, hence, bus loading). – these physical limits prevent arbitrary bus speedup.
59 204521 Digital Computer Architecture Bus-Based Interconnect • Two generic types of busses: – I/O busses: lengthy, many types of devices connected, wide range in the data bandwidth), and follow a bus standard (sometimes called a channel) – CPU–memory buses: high speed, matched to the memory system to maximize memory–CPU bandwidth, single device (sometimes called a backplane) – To lower costs, low cost (older) systems combine together • Bus transaction – Sending address & receiving or sending data
60 204521 Digital Computer Architecture Bus Protocols ฐ ฐ ฐ Master Slave Control Lines Address Lines Data Lines Multibus: 20 address, 16 data, 5 control, 50ns Pause Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req., ack.) serve to orchestrate sequencing Synchronous Bus Transfers: sequence relative to common clock
61 204521 Digital Computer Architecture Synchronous Bus Protocols Address Data Read Wait Clock Address Data Wait Pipelined/Split transaction Bus Protocol addr 1 data 0 addr 2 wait 1 data 1 addr 3 OK 1 data 2 begin read Read complete
62 204521 Digital Computer Architecture Asynchronous Handshake Address Data Read Req. Ack. Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack 4 Cycle Handshake
63 204521 Digital Computer Architecture Read Transaction Address Data Read Req Ack Master Asserts Address Next Address t0 t1 t2 t3 t4 t5 Time Multiplexed Bus: address and data share lines t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack 4 Cycle Handshake
64 204521 Digital Computer Architecture Bus Arbitration Parallel (Centralized) Arbitration Serial Arbitration (daisy chaining) Polling BR BG M BR BG M BR BG M M BGi BGo BR M BGi BGo BR M BGi BGo BR BG BR A.U. BR A C M BR A C M BR A C M BR A A.U. Bus Request Bus Grant
65 204521 Digital Computer Architecture Bus Options Option High performance Low cost Bus width Separate address Multiplex address & data lines & data lines Data width Wider is faster Narrower is cheaper (e.g., 32 bits) (e.g., 8 bits) Transfer size Multiple words has Single-word transfer less bus overhead is simpler Bus masters Multiple Single master (requires arbitration) (no arbitration) Split Yes—separate No—continuous transaction? Request and Reply connection is cheaper packets gets higher and has lower latency bandwidth (needs multiple masters) Clocking Synchronous Asynchronous
66 204521 Digital Computer Architecture 1990 Bus Survey (P&H, 1st Ed) VME FutureBus Multibus II IPI SCSI Signals 128 96 96 16 8 Addr/Data mux no yes yes n/a n/a Data width 16 - 32 32 32 16 8 Masters multi multi multi single multi Clocking Async Async Sync Async either MB/s (0ns, word) 2537 20 25 1.5 (asyn) 5 (sync) 150ns word 12.9 15.5 10 = = 0ns block 27.9 95.2 40 = = 150ns block 13.6 20.8 13.3 = = Max devices 21 20 21 8 7 Max meters 0.5 0.5 0.5 50 25 Standard IEEE 1014 IEEE 896.1 ANSI/IEEE ANSI X3.129 ANSI X3.131 1296
67 204521 Digital Computer Architecture VME • 3 96-pin connectors • 128 defined as standard, rest customer defined – 32 address – 32 data – 64 command & power/ground lines
68 204521 Digital Computer Architecture SCSI: Small Computer System Interface • Clock rate: 5 MHz / 10 MHz (fast) / 20 MHz (ultra) • Width: n = 8 bits / 16 bits (wide); up to n – 1 devices to communicate on a bus or “string” • Devices can be slave (“target”) or master(“initiator”) • SCSI protocol: a series of “phases”, during which specif- ic actions are taken by the controller and the SCSI disks – Bus Free: No device is currently accessing the bus – Arbitration: When the SCSI bus goes free, multiple devices may request (arbitrate for) the bus; fixed priority by address – Selection: informs the target that it will participate (Reselection if disconnected) – Command: the initiator reads the SCSI command bytes from host memory and sends them to the target – Data Transfer: data in or out, initiator: target – Message Phase: message in or out, initiator: target (identify, save/restore data pointer, disconnect, command complete) – Status Phase: target, just before command complete
69 204521 Digital Computer Architecture SCSI “Bus”: Channel Architecture Command Setup Arbitration Selection Message Out (Identify) Command Disconnect to seek/¼ll buffer Message In (Disconnect) - - Bus Free - - Arbitration Reselection Message In (Identify) Data Transfer Data In Disconnect to ¼ll buffer Message In (Save Data Ptr) Message In (Disconnect) - - Bus Free - - Arbitration Reselection Message In (Identify) Command Completion Status Message In (Command Complete) If no disconnect is needed Completion Message In (Restore Data Ptr) peer-to-peer protocols initiator/target linear byte streams disconnect/reconnect
70 204521 Digital Computer Architecture 1993 I/O Bus Survey (P&H, 2nd Ed) Bus SBus TurboChannel MicroChannel PCI Originator Sun DEC IBM Intel Clock Rate (MHz) 16-25 12.5-25 async 33 Addressing Virtual Physical Physical Physical Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64 Master Multi Single Multi Multi Arbitration Central Central Central Central 32 bit read (MB/s) 33 25 20 33 Peak (MB/s) 89 84 75 111 (222) Max Power (W) 16 26 13 25
71 204521 Digital Computer Architecture 1993 MP Server Memory Bus Survey Bus Summit Challenge XDBus Originator HP SGI Sun Clock Rate (MHz) 60 48 66 Split transaction? Yes Yes Yes? Address lines 48 40 ?? Data lines 128 256 144 (parity) Data Sizes (bits) 512 1024 512 Clocks/transfer 4 5 4? Peak (MB/s) 960 1200 1056 Master Multi Multi Multi Arbitration Central Central Central Addressing Physical Physical Physical Slots 16 9 10 Busses/system 1 1 2 Length 13 inches 12? inches 17 inches
72 204521 Digital Computer Architecture Communications Networks Performance limiter is memory system, OS overhead Node Processor Control Reg. I/F Net I/F Memory Request Block Receive Block Media Network Controller Peripheral Backplane Bus DMA . . . Processor Memory List of request blocks Data to be transmitted . . . List of receive blocks Data received DMA . . . List of free blocks • Send/receive queues in processor memories • Network controller copies back and forth via DMA • No host intervention needed • Interrupt host when message sent or received
73 204521 Digital Computer Architecture I/O Controller Architecture Peripheral Bus (VME, FutureBus, etc.) Host Memory Processor Cache Host Processor Peripheral Bus Interface/DMA I/O Channel Interface Buffer Memory ROM µProc I/O Controller Request/response block interface Backdoor access to host memory
74 204521 Digital Computer Architecture I/O Data Flow Memory-to-Memory Copy DMAover Peripheral Bus Xfer over Disk Channel Xfer over Serial Interface Application Address Space OS Buffers (>10 MByte) HBABuffers (1 M - 4 MBytes) Track Buffers (32K - 256KBytes) I/O Device I/O Controller Embedded Controller Head/Disk Assembly Host Processor Impediment to high performance: multiple copies, complex hierarchy

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Digital computer architecture issues in IO

  • 1.
    1 204521 Digital ComputerArchitecture Lecture 10b I/O Introduction: Storage Devices, Metrics, & Productivity Pradondet Nilagupta Original note from Professor David A. Patterson Spring 2001
  • 2.
    2 204521 Digital ComputerArchitecture Storage System Issues • Historical Context of Storage I/O • Secondary and Tertiary Storage Devices • Storage I/O Performance Measures • Processor Interface Issues • A Little Queuing Theory • Redundant Arrarys of Inexpensive Disks (RAID) • I/O Buses
  • 3.
    3 204521 Digital ComputerArchitecture A Communication-Centric World • Computation is getting distributed … – Internet, WAN, LAN, BodyLAN, Home Networks, Microprocessor Peripherals, Processor-Memory Interface, System-on-a-Chip • Efficient Networking and Communication is Crucial • The System-on-a-Chip implies the Network- on-a-Chip • In Next Set of Lectures: – Busses and Networks – But more importantly, the impact of integration
  • 4.
    4 204521 Digital ComputerArchitecture A Bus Is: • shared communication link • single set of wires used to connect multiple subsystems • A Bus is also a fundamental tool for composing large, complex systems – systematic means of abstraction Control Datapath Memory Processor Input Output What is a bus?
  • 5.
    5 204521 Digital ComputerArchitecture Busses
  • 6.
    6 204521 Digital ComputerArchitecture • Versatility: – New devices can be added easily – Peripherals can be moved between computer systems that use the same bus standard • Low Cost: – A single set of wires is shared in multiple ways Memory Processe r I/O Device I/O Device I/O Device Advantages of Buses
  • 7.
    7 204521 Digital ComputerArchitecture • It creates a communication bottleneck – The bandwidth of that bus can limit the maximum I/O throughput • The maximum bus speed is largely limited by: – The length of the bus – The number of devices on the bus – The need to support a range of devices with: • Widely varying latencies • Widely varying data transfer rates Memor y Processo r I/O Device I/O Device I/O Device Disadvantage of Buses
  • 8.
    8 204521 Digital ComputerArchitecture • Control lines: – Signal requests and acknowledgments – Indicate what type of information is on the data lines • Data lines carry information between the source and the destination: – Data and Addresses – Complex commands Data Lines Control Lines General Organization of a Bus
  • 9.
    9 204521 Digital ComputerArchitecture • A bus transaction includes two parts: – Issuing the command (and address) – request – Transferring the data – action • Master is the one who starts the bus transaction by: – issuing the command (and address) • Slave is the one who responds to the address by: – Sending data to the master if the master ask for data – Receiving data from the master if the master wants to send data Bus Master Bus Slave Master issues command Data can go either way Master versus Slave
  • 10.
    10 204521 Digital ComputerArchitecture Types of Busses • Processor-Memory Bus (design specific) – Short and high speed – Only need to match the memory system • Maximize memory-to-processor bandwidth – Connects directly to the processor – Optimized for cache block transfers • I/O Bus (industry standard) – Usually is lengthy and slower – Need to match a wide range of I/O devices – Connects to the processor-memory bus or backplane bus • Backplane Bus (standard or proprietary) – Backplane: an interconnection structure within the chassis – Allow processors, memory, and I/O devices to coexist – Cost advantage: one bus for all components
  • 11.
    11 204521 Digital ComputerArchitecture Processor/Memory Bus PCI Bus I/O Busses Example: Pentium System Organization
  • 12.
    12 204521 Digital ComputerArchitecture A Computer System with One Bus: Backplane Bus • A single bus (the backplane bus) is used for: – Processor to memory communication – Communication between I/O devices and memory • Advantages: Simple and low cost • Disadvantages: slow and the bus can become a major bottleneck • Example: IBM PC - AT Processor Memory I/O Devices Backplane Bus
  • 13.
    13 204521 Digital ComputerArchitecture A Two-Bus System • I/O buses tap into the processor-memory bus via bus adaptors: – Processor-memory bus: mainly for processor-memory traffic – I/O buses: provide expansion slots for I/O devices • Apple Macintosh-II – NuBus: Processor, memory, and a few selected I/O devices – SCCI Bus: the rest of the I/O devices Processor Memory I/O Bus Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus
  • 14.
    14 204521 Digital ComputerArchitecture A Three-Bus System • A small number of backplane buses tap into the processor-memory bus – Processor-memory bus is only used for processor-memory traffic – I/O buses are connected to the backplane bus • Advantage: loading on the processor bus is greatly reduced Processor Memory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus
  • 15.
    15 204521 Digital ComputerArchitecture North/South Bridge architectures: separate busses • Separate sets of pins for different functions – Memory bus – Caches – Graphics bus (for fast frame buffer) – I/O busses are connected to the backplane bus • Advantage: – Busses can run at different speeds – Much less overall loading! Processor Memory Processor Memory Bus Bus Adaptor Bus Adaptor I/O Bus Backplane Bus I/O Bus “backside cache”
  • 16.
    16 204521 Digital ComputerArchitecture Bunch of Wires Physical / Mechanical Characteristics – the connectors Electrical Specification Timing and Signaling Specification Transaction Protocol What defines a bus?
  • 17.
    17 204521 Digital ComputerArchitecture • Synchronous Bus: – Includes a clock in the control lines – A fixed protocol for communication that is relative to the clock – Advantage: involves very little logic and can run very fast – Disadvantages: • Every device on the bus must run at the same clock rate • To avoid clock skew, they cannot be long if they are fast • Asynchronous Bus: – It is not clocked – It can accommodate a wide range of devices – It can be lengthened without worrying about clock skew – It requires a handshaking protocol Synchronous and Asynchronous Bus
  • 18.
    18 204521 Digital ComputerArchitecture ° ° ° Master Slave Control Lines Address Lines Data Lines Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. Busses so far
  • 19.
    19 204521 Digital ComputerArchitecture Bus Transaction • Arbitration: Who gets the bus • Request: What do we want to do • Action: What happens in response
  • 20.
    20 204521 Digital ComputerArchitecture • One of the most important issues in bus design: – How is the bus reserved by a device that wishes to use it? • Chaos is avoided by a master-slave arrangement: – Only the bus master can control access to the bus: It initiates and controls all bus requests – A slave responds to read and write requests • The simplest system: – Processor is the only bus master – All bus requests must be controlled by the processor – Major drawback: the processor is involved in every transaction Bus Master Bus Slave Control: Master initiates requests Data can go either way Arbitration: Obtaining Access to the Bus
  • 21.
    21 204521 Digital ComputerArchitecture Multiple Potential Bus Masters: the Need for Arbitration • Bus arbitration scheme: – A bus master wanting to use the bus asserts the bus request – A bus master cannot use the bus until its request is granted – A bus master must signal to the arbiter the end of the bus utilization • Bus arbitration schemes usually try to balance two factors: – Bus priority: the highest priority device should be serviced first – Fairness: Even the lowest priority device should never be completely locked out from the bus • Bus arbitration schemes can be divided into four broad classes: – Daisy chain arbitration – Centralized, parallel arbitration – Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. – Distributed arbitration by collision detection: Each device just “goes for it”. Problems found after the fact.
  • 22.
    22 204521 Digital ComputerArchitecture The Daisy Chain Bus Arbitrations Scheme • Advantage: simple • Disadvantages: – Cannot assure fairness: A low-priority device may be locked out indefinitely – The use of the daisy chain grant signal also limits the bus speed Bus Arbiter Device 1 Highes t Priorit y Device N Lowest Priority Device 2 Grant Grant Grant Release Request wired-OR
  • 23.
    23 204521 Digital ComputerArchitecture • Used in essentially all processor-memory busses and in high-speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req Centralized Parallel Arbitration
  • 24.
    24 204521 Digital ComputerArchitecture • All agents operate synchronously • All can source / sink data at same rate • => simple protocol – just manage the source and target Simplest bus paradigm
  • 25.
    25 204521 Digital ComputerArchitecture • Even memory busses are more complex than this – memory (slave) may take time to respond – it may need to control data rate BReq BG Cmd+Addr R/W Address Data1 Data2 Data Simple Synchronous Protocol
  • 26.
    26 204521 Digital ComputerArchitecture • Slave indicates when it is prepared for data xfer • Actual transfer goes at bus rate BReq BG Cmd+Addr R/W Address Data1 Data2 Data Data1 Wait Typical Synchronous Protocol
  • 27.
    27 204521 Digital ComputerArchitecture • Separate versus multiplexed address and data lines: – Address and data can be transmitted in one bus cycle if separate address and data lines are available – Cost: (a) more bus lines, (b) increased complexity • Data bus width: – By increasing the width of the data bus, transfers of multiple words require fewer bus cycles – Example: SPARCstation 20’s memory bus is 128 bit wide – Cost: more bus lines • Block transfers: – Allow the bus to transfer multiple words in back-to-back bus cycles – Only one address needs to be sent at the beginning – The bus is not released until the last word is transferred – Cost: (a) increased complexity (b) decreased response time for request Increasing the Bus Bandwidth
  • 28.
    28 204521 Digital ComputerArchitecture • Overlapped arbitration – perform arbitration for next transaction during current transaction • Bus parking – master holds onto bus and performs multiple transactions as long as no other master makes request • Overlapped address / data phases – requires one of the above techniques • Split-phase (or packet switched) bus – completely separate address and data phases – arbitrate separately for each – address phase yield a tag which is matched with data phase • ”All of the above” in most modern memory buses Increasing Transaction Rate on Multimaster Bus
  • 29.
    29 204521 Digital ComputerArchitecture Bus MBus Summit Challenge XDBus Originator Sun HP SGI Sun Clock Rate (MHz) 40 60 48 66 Address lines 36 48 40 muxed Data lines 64 128 256 144 (parity) Data Sizes (bits) 256 512 1024 512 Clocks/transfer 4 5 4? Peak (MB/s) 320(80) 960 1200 1056 Master Multi Multi Multi Multi Arbitration Central Central Central Central Slots 16 9 10 Busses/system 1 1 1 2 Length 13 inches 12? inches 17 inches 1993 CPU- Memory Bus Survey
  • 30.
    30 204521 Digital ComputerArchitecture Address Data Read Req Ack Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 • t0 : Master has obtained control and asserts address, direction, data • Waits a specified amount of time for slaves to decode target • t1: Master asserts request line • t2: Slave asserts ack, indicating data received • t3: Master releases req • t4: Slave releases ack Asynchronous Handshake (4- phase)
  • 31.
    31 204521 Digital ComputerArchitecture Address Data Read Req Ack Master Asserts Address Next Address t0 t1 t2 t3 t4 t5 • t0 : Master has obtained control and asserts address, direction, data • Waits a specified amount of time for slaves to decode target • t1: Master asserts request line • t2: Slave asserts ack, indicating ready to transmit data • t3: Master releases req, data received • t4: Slave releases ack Read Transaction Slave Data
  • 32.
    32 204521 Digital ComputerArchitecture Bus SBus TurboChannel MicroChannel PCI Originator Sun DEC IBM Intel Clock Rate (MHz) 16-25 12.5-25 async 33 Addressing Virtual Physical Physical Physical Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64 Master Multi Single Multi Multi Arbitration Central Central Central Central 32 bit read (MB/s) 33 25 20 33 Peak (MB/s) 89 84 75 111 (222) Max Power (W) 16 26 13 25 1993 Backplane/IO Bus Survey
  • 33.
    33 204521 Digital ComputerArchitecture • Examples – graphics – fast networks • Limited number of devices • Data transfer bursts at full rate • DMA transfers important – small controller spools stream of bytes to or from memory • Either side may need to squelch transfer – buffers fill up High Speed I/O Bus
  • 34.
    34 204521 Digital ComputerArchitecture • All signals sampled on rising edge • Centralized Parallel Arbitration – overlapped with previous transaction • All transfers are (unlimited) bursts • Address phase starts by asserting FRAME# • Next cycle “initiator” asserts cmd and address • Data transfers happen on when – IRDY# asserted by master when ready to transfer data – TRDY# asserted by target when ready to transfer data – transfer when both asserted on rising edge • FRAME# deasserted when master intends to complete only one more data transfer PCI Read/Write Transactions
  • 35.
    35 204521 Digital ComputerArchitecture – Turn-around cycle on any signal driven by more than one agent PCI Read Transaction
  • 36.
    36 204521 Digital ComputerArchitecture PCI Write Transaction
  • 37.
    37 204521 Digital ComputerArchitecture The System-on-a-Chip Nightmare Bridge DMA CPU DSP Mem Ctrl. MPEG C I O O System Bus Peripheral Bus Control Wires Custom Interfaces The “Board-on-a-Chip Approach
  • 38.
    38 204521 Digital ComputerArchitecture Sonics SOC Integration Architecture SiliconBackplane Agent™ Open Core Protocol™ SiliconBackplane™ (patented) MultiChip Backplane™ { DSP MPEG CPU DMA C MEM I O
  • 39.
    39 204521 Digital ComputerArchitecture Open Core Protocol Goals • Bus Independent • Scalable • Configurable • Synthesis/Timing Analysis Friendly • Encompass entire core/system interface needs (data, control, and test flows)
  • 40.
    40 204521 Digital ComputerArchitecture Data, Control, and Test Flows • Data Flow – Signals and protocols associated with moving data – Includes address, data, handshaking, etc. – Similar to services provided by traditional computer buses • Control Flow – Signals and protocols associated with non-data communication – Sideband - not synchronized to data flow (out of band) – Examples include interrupts, high-level flow control, etc. • Test Flow – Signals and protocols related to debug and manufacturing test
  • 41.
    41 204521 Digital ComputerArchitecture OCP Overview • Point-to-point, uni-directional, synchronous – easy physical implementation • Master/Slave, request/response – well-defined, simple roles • Extensions – added functionality to support cores with more complex interface requirements • Configurability – pay only for the features needed for a given core
  • 42.
    42 204521 Digital ComputerArchitecture Master vs. Slave IP Core IP Core IP Core On-Chip Bus Slave Master Slave Slave Slave Master Master Master Initiator Target Open Core Protocol Request Response
  • 43.
    43 204521 Digital ComputerArchitecture Basic OCP Master MCmd [3] MAddr [N] MData [N] SResp [3] SData [N] Clk SCmdAccept Read: Command, Address Command Accept Response, Data Write (posted): Command, Address, Data MCmd, MAddr SCmdAccept SResp, SData MCmd, Maddr, MData SCmdAccept Slave
  • 44.
    44 204521 Digital ComputerArchitecture Protocol Phases • Request Phase (begins Transfer) – Master presents request (command, address, etc.) to Slave • Response Phase (ends Transfer) – Slave presents response (success/fail, read data) to Master – Only available for read transfers (posted write model) • Datahandshake Phase (Optional) – Allows pipelining request ahead of write data – Only available for write transfers • Phase ordering – Request -> Datahandshake -> Response
  • 45.
    45 204521 Digital ComputerArchitecture OCP Extensions • Simple Extensions – Byte Enables – Bursts – Flow Control – Data Handshake • Complex Extensions – Threads and Connections • Sideband Signals
  • 46.
    46 204521 Digital ComputerArchitecture The Backplane: Why Not Use a Computer Bus? IP Core IP Core    IP Core IP Core    Computer Bus Transmit FIFO Receive FIFO Time Data Arbiter Address •Expensive to decouple •Not designed for real-time
  • 47.
    47 204521 Digital ComputerArchitecture Communication Buses Decouple and Guarantee Real Time IP Core IP Core    IP Core IP Core    Communications Bus Transmit FIFO Receive FIFO Time Data TDMA TDMA •Connections are expensive •Poor read latency
  • 48.
    48 204521 Digital ComputerArchitecture From Communications • Efficient BW decoupling • Guaranteed BW & latency • Side-band signaling SiliconBackplane™ Employs Best of Both From Computing • Address-based selection • Write and read transfers • Pipelining DSP MPEG CPU DMA C MEM I O
  • 49.
    49 204521 Digital ComputerArchitecture Guaranteed Bandwidth Arbitration • Independent arbitration for every cycle includes two phases: -Distributed TDMA -Round robin • Provides fine control over system bandwidth Current Slot Arbitration Command
  • 50.
    50 204521 Digital ComputerArchitecture Guaranteed Latency • Fixed latency between command/address and data/response phases • Matches pipelined CPU model ensuring high performance access to on-chip resources • Pipelined data routed through SiliconBackplane™ • Latency re-programmable in software • Variable-latency blocks do not tie up the SiliconBackplane
  • 51.
    52 204521 Digital ComputerArchitecture Integrated Signaling Mechanism • Dedicated SiliconBackplane™ wires (Flags) support: – Bus-style out-of-band signaling (interrupts) – Point-to-point communications (flow control) – Dynamic point-to-point (retry mechanism) • Same design flow, timing, flexibility as address/data portion of SonicsIA™
  • 52.
    53 204521 Digital ComputerArchitecture MultiChip Backplan SiliconBackplane MultiChip Backplane™ Extends SonicsIA™ Between Chips CPU-Based ASSP ASSP FPGA Seamless integration of protocols
  • 53.
    54 204521 Digital ComputerArchitecture Validation / Test • SiliconBackplane™ highly visible for test – All subsystems communicate through SiliconBackplane • Test Interfaces: – MultiChip Backplane: 100’s MB/sec. – ServiceAgent: Scan-based • Each subsystem can be tested/validated stand-alone Test Vectors Test Vectors MultiChip Backplane™
  • 54.
    55 204521 Digital ComputerArchitecture Summary • Busses are an important technique for building large-scale systems – Their speed is critically dependent on factors such as length, number of devices, etc. – Critically limited by capacitance – Tricks: esoteric drive technology such as GTL • Important terminology: – Master: The device that can initiate new transactions – Slaves: Devices that respond to the master • Two types of bus timing: – Synchronous: bus includes clock – Asynchronous: no clock, just REQ/ACK strobing • System-on-a-Chip approach invites new solutions – Well-defined and clear communication protocols – Physical layer hidden to designer
  • 55.
    56 204521 Digital ComputerArchitecture Interconnect Trends Network >1000 m 10 - 100 Mb/s high (>ms) low Extensive CRC Channel 10 - 100 m 40 - 1000 Mb/s medium medium Byte Parity Backplane 1 m 320 - 1000+ Mb/s low (<µs) high Byte Parity Distance Bandwidth Latency Reliability • Interconnect = glue that interfaces computer system components • High speed hardware interfaces + logical protocols • Networks, channels, backplanes memory-mapped wide pathways centralized arb message-based narrow pathways distributed arb
  • 56.
    57 204521 Digital ComputerArchitecture Backplane Architectures 128 No 16 - 32 Single/Multiple Multiple No Async 25 12.9 27.9 13.6 21 .5 m IEEE 1014 96 Yes 32 Single/Multiple Multiple Optional Async 37 15.5 95.2 20.8 20 .5 m IEEE 896 Metric VME FutureBus 96 Yes 32 Single/Multiple Multiple Optional Sync 20 10 40 13.3 21 .5 m ANSI/IEEE 1296 MultiBus II Bus Width (signals) Address/Data Multiplexed? Data Width Xfer Size # of Bus Masters Split Transactions Clocking Bandwidth, Single W ord (0 ns mem) Bandwidth, Single W ord (150 ns mem) Bandwidth Multiple W ord (0 ns mem) Bandwidth Multiple W ord (150 ns mem) Max # of devices Max Bus Length Standard 25 na 8 Single/Multiple Multiple Optional Either 5, 1.5 5, 1.5 5, 1.5 5, 1.5 7 25 m ANSI X3.131 SCSI-I Distinctions begin to blur: SCSI channel is like a bus FutureBus is like a channel (disconnect/reconnect) HIPPI forms links in high speed switching fabrics
  • 57.
    58 204521 Digital ComputerArchitecture Bus-Based Interconnect • Bus: a shared communication link between subsystems – Low cost: a single set of wires is shared multiple ways – Versatility: Easy to add new devices & peripherals may even be ported between computers using common bus • Disadvantage – A communication bottleneck, possibly limiting the maximum I/O throughput • Bus speed is limited by physical factors – the bus length – the number of devices (and, hence, bus loading). – these physical limits prevent arbitrary bus speedup.
  • 58.
    59 204521 Digital ComputerArchitecture Bus-Based Interconnect • Two generic types of busses: – I/O busses: lengthy, many types of devices connected, wide range in the data bandwidth), and follow a bus standard (sometimes called a channel) – CPU–memory buses: high speed, matched to the memory system to maximize memory–CPU bandwidth, single device (sometimes called a backplane) – To lower costs, low cost (older) systems combine together • Bus transaction – Sending address & receiving or sending data
  • 59.
    60 204521 Digital ComputerArchitecture Bus Protocols ฐ ฐ ฐ Master Slave Control Lines Address Lines Data Lines Multibus: 20 address, 16 data, 5 control, 50ns Pause Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req., ack.) serve to orchestrate sequencing Synchronous Bus Transfers: sequence relative to common clock
  • 60.
    61 204521 Digital ComputerArchitecture Synchronous Bus Protocols Address Data Read Wait Clock Address Data Wait Pipelined/Split transaction Bus Protocol addr 1 data 0 addr 2 wait 1 data 1 addr 3 OK 1 data 2 begin read Read complete
  • 61.
    62 204521 Digital ComputerArchitecture Asynchronous Handshake Address Data Read Req. Ack. Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack 4 Cycle Handshake
  • 62.
    63 204521 Digital ComputerArchitecture Read Transaction Address Data Read Req Ack Master Asserts Address Next Address t0 t1 t2 t3 t4 t5 Time Multiplexed Bus: address and data share lines t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack 4 Cycle Handshake
  • 63.
    64 204521 Digital ComputerArchitecture Bus Arbitration Parallel (Centralized) Arbitration Serial Arbitration (daisy chaining) Polling BR BG M BR BG M BR BG M M BGi BGo BR M BGi BGo BR M BGi BGo BR BG BR A.U. BR A C M BR A C M BR A C M BR A A.U. Bus Request Bus Grant
  • 64.
    65 204521 Digital ComputerArchitecture Bus Options Option High performance Low cost Bus width Separate address Multiplex address & data lines & data lines Data width Wider is faster Narrower is cheaper (e.g., 32 bits) (e.g., 8 bits) Transfer size Multiple words has Single-word transfer less bus overhead is simpler Bus masters Multiple Single master (requires arbitration) (no arbitration) Split Yes—separate No—continuous transaction? Request and Reply connection is cheaper packets gets higher and has lower latency bandwidth (needs multiple masters) Clocking Synchronous Asynchronous
  • 65.
    66 204521 Digital ComputerArchitecture 1990 Bus Survey (P&H, 1st Ed) VME FutureBus Multibus II IPI SCSI Signals 128 96 96 16 8 Addr/Data mux no yes yes n/a n/a Data width 16 - 32 32 32 16 8 Masters multi multi multi single multi Clocking Async Async Sync Async either MB/s (0ns, word) 2537 20 25 1.5 (asyn) 5 (sync) 150ns word 12.9 15.5 10 = = 0ns block 27.9 95.2 40 = = 150ns block 13.6 20.8 13.3 = = Max devices 21 20 21 8 7 Max meters 0.5 0.5 0.5 50 25 Standard IEEE 1014 IEEE 896.1 ANSI/IEEE ANSI X3.129 ANSI X3.131 1296
  • 66.
    67 204521 Digital ComputerArchitecture VME • 3 96-pin connectors • 128 defined as standard, rest customer defined – 32 address – 32 data – 64 command & power/ground lines
  • 67.
    68 204521 Digital ComputerArchitecture SCSI: Small Computer System Interface • Clock rate: 5 MHz / 10 MHz (fast) / 20 MHz (ultra) • Width: n = 8 bits / 16 bits (wide); up to n – 1 devices to communicate on a bus or “string” • Devices can be slave (“target”) or master(“initiator”) • SCSI protocol: a series of “phases”, during which specif- ic actions are taken by the controller and the SCSI disks – Bus Free: No device is currently accessing the bus – Arbitration: When the SCSI bus goes free, multiple devices may request (arbitrate for) the bus; fixed priority by address – Selection: informs the target that it will participate (Reselection if disconnected) – Command: the initiator reads the SCSI command bytes from host memory and sends them to the target – Data Transfer: data in or out, initiator: target – Message Phase: message in or out, initiator: target (identify, save/restore data pointer, disconnect, command complete) – Status Phase: target, just before command complete
  • 68.
    69 204521 Digital ComputerArchitecture SCSI “Bus”: Channel Architecture Command Setup Arbitration Selection Message Out (Identify) Command Disconnect to seek/¼ll buffer Message In (Disconnect) - - Bus Free - - Arbitration Reselection Message In (Identify) Data Transfer Data In Disconnect to ¼ll buffer Message In (Save Data Ptr) Message In (Disconnect) - - Bus Free - - Arbitration Reselection Message In (Identify) Command Completion Status Message In (Command Complete) If no disconnect is needed Completion Message In (Restore Data Ptr) peer-to-peer protocols initiator/target linear byte streams disconnect/reconnect
  • 69.
    70 204521 Digital ComputerArchitecture 1993 I/O Bus Survey (P&H, 2nd Ed) Bus SBus TurboChannel MicroChannel PCI Originator Sun DEC IBM Intel Clock Rate (MHz) 16-25 12.5-25 async 33 Addressing Virtual Physical Physical Physical Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64 Master Multi Single Multi Multi Arbitration Central Central Central Central 32 bit read (MB/s) 33 25 20 33 Peak (MB/s) 89 84 75 111 (222) Max Power (W) 16 26 13 25
  • 70.
    71 204521 Digital ComputerArchitecture 1993 MP Server Memory Bus Survey Bus Summit Challenge XDBus Originator HP SGI Sun Clock Rate (MHz) 60 48 66 Split transaction? Yes Yes Yes? Address lines 48 40 ?? Data lines 128 256 144 (parity) Data Sizes (bits) 512 1024 512 Clocks/transfer 4 5 4? Peak (MB/s) 960 1200 1056 Master Multi Multi Multi Arbitration Central Central Central Addressing Physical Physical Physical Slots 16 9 10 Busses/system 1 1 2 Length 13 inches 12? inches 17 inches
  • 71.
    72 204521 Digital ComputerArchitecture Communications Networks Performance limiter is memory system, OS overhead Node Processor Control Reg. I/F Net I/F Memory Request Block Receive Block Media Network Controller Peripheral Backplane Bus DMA . . . Processor Memory List of request blocks Data to be transmitted . . . List of receive blocks Data received DMA . . . List of free blocks • Send/receive queues in processor memories • Network controller copies back and forth via DMA • No host intervention needed • Interrupt host when message sent or received
  • 72.
    73 204521 Digital ComputerArchitecture I/O Controller Architecture Peripheral Bus (VME, FutureBus, etc.) Host Memory Processor Cache Host Processor Peripheral Bus Interface/DMA I/O Channel Interface Buffer Memory ROM µProc I/O Controller Request/response block interface Backdoor access to host memory
  • 73.
    74 204521 Digital ComputerArchitecture I/O Data Flow Memory-to-Memory Copy DMAover Peripheral Bus Xfer over Disk Channel Xfer over Serial Interface Application Address Space OS Buffers (>10 MByte) HBABuffers (1 M - 4 MBytes) Track Buffers (32K - 256KBytes) I/O Device I/O Controller Embedded Controller Head/Disk Assembly Host Processor Impediment to high performance: multiple copies, complex hierarchy

Editor's Notes

  • #6 The two major advantages of the bus organization are versatility and low cost. By versatility, we mean new devices can easily be added. Furthermore, if a device is designed according to a industry bus standard, it can be move between computer systems that use the same bus standard. The bus organization is a low cost solution because a single set of wires is shared in multiple ways. +1 = 7 min. (X:47)
  • #7 The major disadvantage of the bus organization is that it creates a communication bottleneck. When I/O must pass through a single bus, the bandwidth of that bus can limit the maximum I/O throughput. The maximum bus speed is also largely limited by: (a) The length of the bus. (b) The number of I/O devices on the bus. (C) And the need to support a wide range of devices with a widely varying latencies and data transfer rates. +2 = 9 min. (Y:49)
  • #8 A bus generally contains a set of control lines and a set of data lines. The control lines are used to signal requests and acknowledgments and to indicate what type of information is on the data lines. The data lines carry information between the source and the destination. This information may consists of data, addresses, or complex commands. A bus transaction includes tow parts: (a) sending the address and (b) then receiving or sending the data. +1 = 10 min (X:50)
  • #9 The bus master is the one who starts the bus transaction by sending out the address. The slave is the one who responds to the master by either sending data to the master if the master asks for data. Or the slave may end up receiving data from the master if the master wants to send data. In most simple I/O operations, the processor will be the bus master but as I will show you later in today’s lecture, this is not always be the case. +1 = 11 min. (X:51)
  • #10 Buses are traditionally classified as one of 3 types: processor memory buses, I/O buses, or backplane buses. The processor memory bus is usually design specific while the I/O and backplane buses are often standard buses. In general processor bus are short and high speed. It tries to match the memory system in order to maximize the memory-to-processor BW and is connected directly to the processor. I/O bus usually is lengthy and slow because it has to match a wide range of I/O devices and it usually connects to the processor-memory bus or backplane bus. Backplane bus receives its name because it was often built into the backplane of the computer--it is an interconnection structure within the chassis. It is designed to allow processors, memory, and I/O devices to coexist on a single bus so it has the cost advantage of having only one single bus for all components. +2 = 16 min. (X:56)
  • #12 Here is an example showing a single bus, the backplane bus is used to provide communication between the processor and memory. As well as communication between I/O devices and memory. The advantage here is of course low cost. One disadvantage of this approach is that the bus with so many things attached to it will be lengthy and slow. Furthermore, the bus can become a major communication bottleneck if everybody wants to use the bus at the same time. The IBM PC is an example that uses only a backplane bus for all communication. +2 = 18 min. (X:58)
  • #13 Right before the break, I showed you a system with one bus only. Here is an example using two buses where multiple I/O buses tap into the processor-memory bus via bus adaptors. The Processor-memory bus is used mainly for processor-memory traffic while the I/O buses are used to provide expansion slots for the I/O devices. The Apple Macintosh-II adopts this organization where the NuBus is used to connect processor, memory, and a few selected I/O devices together. The rest of the I/O devices reside on an industry standard bus, the SCCI Bus, which is connected to the NuBus via a bus adaptor. +2 = 25 min. (Y:05)
  • #14 Finally, in a 3-bus system, a small number of backplane buses (in our example here, just 1) tap into the processor-memory bus. The processor-memory bus is used mainly for processor memory traffic while the I/O buses are connected to the backplane bus via bus adaptors. An advantage of this organization is that the loading on the processor-memory bus is greatly reduced because of the small number of taps into the high-speed processor-memory bus. +1 = 26 min. (Y:06)
  • #15 Finally, in a 3-bus system, a small number of backplane buses (in our example here, just 1) tap into the processor-memory bus. The processor-memory bus is used mainly for processor memory traffic while the I/O buses are connected to the backplane bus via bus adaptors. An advantage of this organization is that the loading on the processor-memory bus is greatly reduced because of the small number of taps into the high-speed processor-memory bus. +1 = 26 min. (Y:06)
  • #17 There are substantial differences between the design requirements for the I/O buses and processor-memory buses and the backplane buses. Consequently, there are two different schemes for communication on the bus: synchronous and asynchronous. Synchronous bus includes a clock in the control lines and a fixed protocol for communication that is relative to the clock. Since the protocol is fixed and everything happens with respect to the clock, it involves very logic and can run very fast. Most processor-memory buses fall into this category. Synchronous buses have two major disadvantages: (1) every device on the bus must run at the same clock rate. (2) And if they are fast, they must be short to avoid clock skew problem. By definition, an asynchronous bus is not clocked so it can accommodate a wide range of devices at different clock rates and can be lengthened without worrying about clock skew. The draw back is that it can be slow and more complex because a handshaking protocol is needed to coordinate the transmission of data between the sender and receiver. +2 = 28 min. (Y:08)
  • #20 Taking about trying to get onto the bus: how does a device get onto the bus anyway? If everybody tries to use the bus at the same time, chaos will result. Chaos is avoided by a maser-slave arrangement where only the bus master is allow to initiate and control bus requests. The slave has no control over the bus. It just responds to the master’s response. Pretty sad. In the simplest system, the processor is the one and ONLY one bus master and all bus requests must be controlled by the processor. The major drawback of this simple approach is that the processor needs to be involved in every bus transaction and can use up too many processor cycles. +2 = 35 min. (Y:15)
  • #21 A more aggressive approach is to allow multiple potential bus masters in the system. With multiple potential bus masters, a mechanism is needed to decide which master gets to use the bus next. This decision process is called bus arbitration and this is how it works. A potential bus master (which can be a device or the processor) wanting to use the bus first asserts the bus request line and it cannot start using the bus until the request is granted. Once it finishes using the bus, it must tell the arbiter that it is done so the arbiter can allow other potential bus master to get onto the bus. All bus arbitration schemes try to balance two factors: bus priority and fairness. Priority is self explanatory. Fairness means even the device with the lowest priority should never be completely locked out from the bus. Bus arbitration schemes can be divided into four broad classes. In the fist one: (a) Each device wanting the bus places a code indicating its identity on the bus. (b) By examining the bus, the device can determine the highest priority device that has made a request and decide whether it can get on. In the second scheme, each device independently requests the bus and collision will result in garbage on the bus if multiple request occurs simultaneously. Each device will detect whether its request result in a collision and if it does, it will back off for an random period of time before trying again. The Ethernet you use for your workstation uses this scheme. We will talk about the 3rd and 4th schemes in the next two slides. +3 = 38 min. (Y:18)
  • #22 The daisy chain arbitration scheme got its name from the structure for the grant line which chains through each device from the highest priority to the lowest priority. The higher priority device will pass the grant line to the lower priority device ONLY if it does not want it so priority is built into the scheme. The advantage of this scheme is simple. The disadvantages are: (a) It cannot assure fairness. A low priority device may be locked out indefinitely. (b) Also, the daisy chain grant line will limit the bus speed. +1 = 39 min. (Y:19)
  • #27 Our handshaking example in the previous slide used the same wires to transmit the address as well as data. The advantage is saving in signal wires. The disadvantage is that it will take multiple cycles to transmit address and data. By having separate lines for addresses and data, we can increase the bus bandwidth by transmitting address and data in the same cycle at the cost of more bus lines and increased complexity. This (1st bullet) is one way to increase bus bandwidth. Another way is to increase the width of the data bus so multiple words can be transferred in a single cycle. For example, the SPARCstation memory bus is 128 bits of 16 bytes wide. The cost of this approach is more bus lines. Finally, we can also increase the bus bandwidth by allowing the bus to transfer multiple words in back-to-back bus cycles without sending an address or releasing the bus. The cost of this last approach is an increase of complexity in the bus controller as well as a decease in response time for other parties who want to get onto the bus. +2 = 33 min. (Y:13)