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Dateof birthdesignproblem 1_
- 1. Date of Birth Design Problem Digital Electronics
- 2. Design Specifications Design a combinational logic circuit that meets the following design specifications: •There are three (3) three inputs and seven (7) outputs. •As the inputs count from 000 to 111, the outputs (a – g) will generate the logic to display a date of birth (DOB) on a 7-segment display. •The 7-segment display is a common cathode display. •The DOB will be displayed in the MM-DD-YY format. a Date of Birth X b 7-Segment c d Y Display e Driver Logic f Z g Circuit 2
- 3. Example – DOB 02/13/10 X Y Z Display 0 0 0 0 0 1 0 1 0 February 13, 1910 (02-13-10) 0 1 1 is the date of birth of William 1 0 0 Shockley. Shockley, along with John Bardeen and Walter 1 0 1 Brattain, invented the transistor 1 1 0 while working at Bell Labs in the 1940s. 1 1 1 3
- 4. DOB Truth Table X Y Z Display a b c d e f g 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 4
- 5. DOB Truth Table X Y Z Display a b c d e f g 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 5
- 6. K-Map for Segment (a) X Y Z Display a Z Z 0 0 0 1 XY 1 1 0 0 1 1 XY 0 1 0 0 XY 0 0 0 1 1 0 0 1 XY XYZ 1 0 0 1 XY 1 0 1 0 1 0 YZ 1 1 0 0 1 1 1 1 a= XY+ YZ+ XYZ 6
- 7. Segment (a) – AOI Logic X Y Z a 7
- 8. K-Map for Segment (b) X Y Z Display b Z Z 0 0 0 1 XY 1 1 0 0 1 1 XY 0 1 0 0 XY 0 1 0 1 1 1 1 1 XY YZ 1 0 0 1 XY 1 0 1 0 1 0 XZ 1 1 0 1 1 1 1 1 b= XY+ YZ+ XZ 8
- 9. Segment (b) – NAND Logic X Y Z b 9
- 10. K-Map for Segment (c) X Y Z Display c Z Z 0 0 0 1 XY 1 0 0 0 1 0 YZ 0 1 0 0 XY 0 1 0 1 1 1 1 1 XY YZ 1 0 0 1 XY 1 0 XY 1 0 1 0 1 1 0 1 1 1 1 1 c = YZ+ YZ+ XY 10
- 11. Segment (c) – NOR Logic X Y Z c 11
- 12. All Segments a= XY+ YZ+ XYZ b= XY+ YZ+ XZ c = YZ+ YZ+ XY d= a e= XY+ XYZ f = XYZ+ XYZ g= XY+ XYZ+ YZ 12
- 13. X Y Z Complete Date of Birth Circuit 02-13-10 Common Cathode 7-Segment Display AOI Segment a & d NAND Segment b NOR Segment c AOI Segment e NAND Segment f NOR Segment g 13
Editor's Notes
- Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This slide contains the design specifications for the “Date of Birth” project. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is an example of the “Date of Birth” problem using the birth date 02-13-10. http://web.mit.edu/invent/iow/shockleyetal.html Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is the truth table column for Segment (a). After reviewing how this truth table was developed, pause the presentation and allow the students to complete the truth table columns for segments (b) thru (g). The complete truth table is on the next slide. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is the completed truth table. If you print handouts, do not print this page. Note that segment (a) & (d) are the same, thus you only need to design one circuit to be used for both segments. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is the truth table column, its associated K-Map, & simplified logic expressions for segment (a). Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is logic diagram for segment (a). The circuit was implemented using AOI logic for demonstration purposes. It could have also been implemented with NAND or NOR logic. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is the truth table column, its associated K-Map, & simplified logic expressions for segment (b). Note : In this example, the K-Map could have been grouped differently resulting in a different but equally simple logic expression (i.e., b = X’ Z + Y’ Z’ + X Y). Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is a logic diagram for segment (b). The circuit was implemented in NAND for demonstration purposes. It could also have been implemented with AOI or NOR logic. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is the truth table column, its associated K-Map, & simplified logic expressions for segment (c). Note : Again, in this example, the K-Map could have been group differently resulting in a different but equally simple logic expression (i.e., b = Y’ Z’ + Y Z + X Z’). Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is a logic diagram for segment (c). The circuit was implemented in NOR for demonstration purposes. It could also have been implemented with AOI or NAND logic. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- Here are all of the segments (a) – (g). Simplification and implementation of the segments (d) – (g) are left as an exercise that the students can complete as class work or homework. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009
- This is the complete solution for the DOB problem for DOB 02-13-10. DON’T FORGET THE CURRENT LIMITING RESISTORS. The design will work in simulation without them, but if you build the circuit (i.e., in hardware) and do not include the resistors, the SSD will be destroyed. Date of Birth Design Problem Digital Electronics 2.3 Date of Birth Design Problem Project Lead The Way, Inc. Copyright 2009