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Akram Malak 
Analog IC Designer 
Address : 38 rue Alsace Lorraine, 31000 Toulouse Date of Birth: 01/01/1987 
Email : akram.malak.86@gmail.com Marital status: Single 
Telephone:+337 62 415834 Nationality: Egyptian 
PROFILE : 
A motivated analog designer (working on transistor level, cadence environement), having the experience 
to work in driver for power transistors, ADC and High frequencies PLL. Strong experience in design 
and Layout and chips Test benches. 4 operating chips fabricated and Tested CEA-LETI, Grenoble. 
Having also the potential to suggest projects and working on it. 
EMPLOYEMENT HISTORY : 
-Personal current research : 
1) Circuit + System level idea for a DC/DC current mode boost converter. (better effiency, better cost 
and temperature stability) 
2) Noise free DC to DC inverting voltage converter (charge pump) using normally on transistors (this 
product would help any company interested in this subject to open up a start up) 
June 2014- October 2014 : Analog IC-Designer, Freescale Semi conductor ,Toulouse - France 
 Verification of linear regulators. 
 Design of a charge pump generating negative voltage. 
(vision to generate negative voltage equals to the CP supply without using Level Shifter) 
 Evaluation of electrical simulator tool detecting the floating nodes. 
3) November 2013- April 2014: Analog IC-Designer, LIP6, Paris-France 
 Design of a DC/DC buck converter. Starting by modeling the system level in MATLAB/SIMULINK. 
A macro Model using Cadence is done setting the specifications for each Analog bloc. Design of the 
analog blocs has been done. 
 Techno : AMS 0.35 HV. 
4) May 2012- October 2013 : Analog IC-Designer, CEA-LETI, Grenoble-France 
 Driver for power transistors, design of DRIVER analog circuit blocs. Design of Oscillateur, Bande 
Gap, programmable comparateur, Galvanique decoder, buffer and Temperature detector (Test Bench 
after fabrication + fonctional circuit after TEST).
 Techno : AMS 0.35 HV – HOTMOS Fraunhofer 1 μm (Techno Haute Température) - HOTMOS 
Fraunhofer 0.35 μm (Techno High Temperature). 
 New ideas for a charge pump and a driver for power transistor with the minimum possible integrated 
circuits. 
 Trials to evaluate high temperature technology by designing an oscillator of hundreds of MHz with 
stable performance within Temperature (0° C to 250° C). 
5) October 2011-April 2012 : Research Engineer for CAD and analog design, LIP6, Paris –France 
 Optimizer for automatic sizing of analog circuits. Using CHAMS tools ( possessed by LIP6), we can 
compute the transistors widths given the lengths and the currents of transistors as input parameters 
and through ELDO we can extract the circuits performances. The optimizer uses an intelligent 
global search followed by a Simplex of type Nelder-Mead. The optimization loop is tested by a 
MILLER amplifier having linear specifications (Gain, Unity gain frequency…) and non linear (input 
noise@ 1 Hz, input noise @ unity gain frequency ….) in collaboration with CEA DAM. (journal 
article under review). 
6) 2009: Designer for Σ-Δ modulator for PLL high frequency application (SATA) 
 Project supported by Si-Ware Systems, SWS Egypt. My work concerned the design of the bloc Σ- 
Δ. The bloc Σ-Δ is of 3rd order, realised with a single loop topology to reduce spurs at low frequency 
taking into account the stability problem. The used simulation tools: MATLAB, Modelsim and 
Cadence. 
Techincal Summary : 
1) SYSTEM LEVEL LANGUAGE 
C, C++, MATLAB, SIMULINK, SYSTEM-C. 
2) TOOLS AND ANALOG/DIGITAL DESIGN 
Cadence, VHDL, VHDL AMS, Questa, ELDO, PSPICE. 
3) ENVIRONEMENT 
Linux, Windows. 
Education : 
2011 Getting Master II SESI : Systèmes Electroniques et Systèmes Informatiques- (degree 
very good) - Laboratory LIP 6, University Paris 6 – Pierre et Marie Curie. 
2009-2010 Getting du Master I : Electronic and Telecommunication-(degree very good), University 
Aïn Chams, Cairo. 
2004-2009 Getting the diploma of Engineering in Electronics and Telecommunications (degree 
Excellent) – Faculty of Engineering, University Aïn Chams, Cairo.
1991-2004 Primary and Secondary at « collège Saint Jean Baptiste de La Salle », Cairo. Egyptian 
Bachelor – Series S (degree Excellent). 
Languages : 
English fluent, TOEFL 84/120. 
French fluent. 
Personnel : 
Sport Tennis and Football 
Others Reading in the history of Science, Classic music.

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CV_Akram_Malak

  • 1. Akram Malak Analog IC Designer Address : 38 rue Alsace Lorraine, 31000 Toulouse Date of Birth: 01/01/1987 Email : akram.malak.86@gmail.com Marital status: Single Telephone:+337 62 415834 Nationality: Egyptian PROFILE : A motivated analog designer (working on transistor level, cadence environement), having the experience to work in driver for power transistors, ADC and High frequencies PLL. Strong experience in design and Layout and chips Test benches. 4 operating chips fabricated and Tested CEA-LETI, Grenoble. Having also the potential to suggest projects and working on it. EMPLOYEMENT HISTORY : -Personal current research : 1) Circuit + System level idea for a DC/DC current mode boost converter. (better effiency, better cost and temperature stability) 2) Noise free DC to DC inverting voltage converter (charge pump) using normally on transistors (this product would help any company interested in this subject to open up a start up) June 2014- October 2014 : Analog IC-Designer, Freescale Semi conductor ,Toulouse - France  Verification of linear regulators.  Design of a charge pump generating negative voltage. (vision to generate negative voltage equals to the CP supply without using Level Shifter)  Evaluation of electrical simulator tool detecting the floating nodes. 3) November 2013- April 2014: Analog IC-Designer, LIP6, Paris-France  Design of a DC/DC buck converter. Starting by modeling the system level in MATLAB/SIMULINK. A macro Model using Cadence is done setting the specifications for each Analog bloc. Design of the analog blocs has been done.  Techno : AMS 0.35 HV. 4) May 2012- October 2013 : Analog IC-Designer, CEA-LETI, Grenoble-France  Driver for power transistors, design of DRIVER analog circuit blocs. Design of Oscillateur, Bande Gap, programmable comparateur, Galvanique decoder, buffer and Temperature detector (Test Bench after fabrication + fonctional circuit after TEST).
  • 2.  Techno : AMS 0.35 HV – HOTMOS Fraunhofer 1 μm (Techno Haute Température) - HOTMOS Fraunhofer 0.35 μm (Techno High Temperature).  New ideas for a charge pump and a driver for power transistor with the minimum possible integrated circuits.  Trials to evaluate high temperature technology by designing an oscillator of hundreds of MHz with stable performance within Temperature (0° C to 250° C). 5) October 2011-April 2012 : Research Engineer for CAD and analog design, LIP6, Paris –France  Optimizer for automatic sizing of analog circuits. Using CHAMS tools ( possessed by LIP6), we can compute the transistors widths given the lengths and the currents of transistors as input parameters and through ELDO we can extract the circuits performances. The optimizer uses an intelligent global search followed by a Simplex of type Nelder-Mead. The optimization loop is tested by a MILLER amplifier having linear specifications (Gain, Unity gain frequency…) and non linear (input noise@ 1 Hz, input noise @ unity gain frequency ….) in collaboration with CEA DAM. (journal article under review). 6) 2009: Designer for Σ-Δ modulator for PLL high frequency application (SATA)  Project supported by Si-Ware Systems, SWS Egypt. My work concerned the design of the bloc Σ- Δ. The bloc Σ-Δ is of 3rd order, realised with a single loop topology to reduce spurs at low frequency taking into account the stability problem. The used simulation tools: MATLAB, Modelsim and Cadence. Techincal Summary : 1) SYSTEM LEVEL LANGUAGE C, C++, MATLAB, SIMULINK, SYSTEM-C. 2) TOOLS AND ANALOG/DIGITAL DESIGN Cadence, VHDL, VHDL AMS, Questa, ELDO, PSPICE. 3) ENVIRONEMENT Linux, Windows. Education : 2011 Getting Master II SESI : Systèmes Electroniques et Systèmes Informatiques- (degree very good) - Laboratory LIP 6, University Paris 6 – Pierre et Marie Curie. 2009-2010 Getting du Master I : Electronic and Telecommunication-(degree very good), University Aïn Chams, Cairo. 2004-2009 Getting the diploma of Engineering in Electronics and Telecommunications (degree Excellent) – Faculty of Engineering, University Aïn Chams, Cairo.
  • 3. 1991-2004 Primary and Secondary at « collège Saint Jean Baptiste de La Salle », Cairo. Egyptian Bachelor – Series S (degree Excellent). Languages : English fluent, TOEFL 84/120. French fluent. Personnel : Sport Tennis and Football Others Reading in the history of Science, Classic music.