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Chapter_5_Synchronous_Sequential_Circuit.ppt

The document covers digital logic design, specifically synchronous sequential logic and its components such as latches and flip-flops. It explains various types of sequential circuits, including their operation, state equations, and characteristic tables. Additionally, it discusses controlled latches, the differentiation between edge-triggered and level-triggered devices, and the analysis of clocked sequential circuits.

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Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu
2 2 Sequential Circuits Sequential Circuits Combinational Circuit Memory Elements Inputs Outputs Asynchronous Synchronous Combinational Circuit Flip-flops Inputs Outputs Clock
Eastern Mediterranean University Eastern Mediterranean University 3 3 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 0 1 Q = Q0 Initial Value
Eastern Mediterranean University Eastern Mediterranean University 4 4 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 0 1 0 Q = Q0 Q = Q0
Eastern Mediterranean University Eastern Mediterranean University 5 5 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 1 Q = 0 Q = Q0
Eastern Mediterranean University Eastern Mediterranean University 6 6 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 0 0 1 Q = 0 Q = Q0 Q = 0
Eastern Mediterranean University Eastern Mediterranean University 7 7 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 0 Q = 0 Q = Q0 Q = 1
Eastern Mediterranean University Eastern Mediterranean University 8 8 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 Q = 0 Q = Q0 Q = 1 Q = 1
Eastern Mediterranean University Eastern Mediterranean University 9 9 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 Q = 0 Q = Q0 Q = 1 Q = Q’ 0
Eastern Mediterranean University Eastern Mediterranean University 10 10 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 Q = 0 Q = Q0 Q = 1 Q = Q’ 0 Q = Q’
Eastern Mediterranean University Eastern Mediterranean University 11 11 Latches Latches SR Latch R S Q Q S R Q 0 0 Q0 0 1 0 1 0 1 1 1 Q=Q’=0 No change Reset Set Invalid S R Q Q S R Q 0 0 Q=Q’=1 0 1 1 1 0 0 1 1 Q0 Invalid Set Reset No change
Eastern Mediterranean University Eastern Mediterranean University 12 12 Latches Latches SR Latch R S Q Q S R Q 0 0 Q0 0 1 0 1 0 1 1 1 Q=Q’=0 No change Reset Set Invalid S’ R’ Q 0 0 Q=Q’=1 0 1 1 1 0 0 1 1 Q0 Invalid Set Reset No change S R Q Q
Eastern Mediterranean University Eastern Mediterranean University 13 13 Controlled Latches Controlled Latches SR Latch with Control Input C S R Q 0 x x Q0 1 0 0 Q0 1 0 1 0 1 1 0 1 1 1 1 Q=Q’ No change No change Reset Set Invalid S R Q Q S R C S R Q Q S R C
Eastern Mediterranean University Eastern Mediterranean University 14 14 Controlled Latches Controlled Latches D Latch (D = Data) C D Q 0 x Q0 1 0 0 1 1 1 No change Reset Set S R Q Q D C C Timing Diagram D Q t Output may change
Eastern Mediterranean University Eastern Mediterranean University 15 15 Controlled Latches Controlled Latches D Latch (D = Data) C D Q 0 x Q0 1 0 0 1 1 1 No change Reset Set C Timing Diagram D Q Output may change S R Q Q D C
Eastern Mediterranean University Eastern Mediterranean University 16 16 Flip-Flops Flip-Flops Controlled latches are level-triggered Flip-Flops are edge-triggered C CLK Positive Edge CLK Negative Edge
Eastern Mediterranean University Eastern Mediterranean University 17 17 Flip-Flops Flip-Flops Master-Slave D Flip-Flop D Latch (Master) D C Q D Latch (Slave) D C Q Q D CLK CLK D QMaster QSlave Looks like it is negative edge-triggered Master Slave
Eastern Mediterranean University Eastern Mediterranean University 18 18 Flip-Flops Flip-Flops Edge-Triggered D Flip-Flop D CLK Q Q D Q Q D Q Q Positive Edge Negative Edge
Eastern Mediterranean University Eastern Mediterranean University 19 19 Flip-Flops Flip-Flops JK Flip-Flop D Q Q Q Q CLK J K J Q Q K D = JQ’ + K’Q
Eastern Mediterranean University Eastern Mediterranean University 20 20 Flip-Flops Flip-Flops T Flip-Flop D = TQ’ + T’Q = T  Q J Q Q K T D Q Q T D = JQ’ + K’Q T Q Q
Eastern Mediterranean University Eastern Mediterranean University 21 21 Flip-Flop Characteristic Tables Flip-Flop Characteristic Tables D Q Q D Q(t+1) 0 0 1 1 Reset Set J K Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q’(t) No change Reset Set Toggle J Q Q K T Q Q T Q(t+1) 0 Q(t) 1 Q’(t) No change Toggle
Eastern Mediterranean University Eastern Mediterranean University 22 22 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations D Q Q D Q(t+1) 0 0 1 1 Q(t+1) = D J K Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q’(t) Q(t+1) = JQ’ + K’Q J Q Q K T Q Q T Q(t+1) 0 Q(t) 1 Q’(t) Q(t+1) = T  Q
Eastern Mediterranean University Eastern Mediterranean University 23 23 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 No change Reset Set Toggle
Eastern Mediterranean University Eastern Mediterranean University 24 24 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 No change Reset Set Toggle
Eastern Mediterranean University Eastern Mediterranean University 25 25 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 No change Reset Set Toggle
Eastern Mediterranean University Eastern Mediterranean University 26 26 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 No change Reset Set Toggle
Eastern Mediterranean University Eastern Mediterranean University 27 27 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 K 0 1 0 0 J 1 1 0 1 Q Q(t+1) = JQ’ + K’Q
Eastern Mediterranean University Eastern Mediterranean University 28 28 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Reset D Q Q R Reset R’ D CLK Q(t+1) 0 x x 0
Eastern Mediterranean University Eastern Mediterranean University 29 29 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Reset D Q Q R Reset R’ D CLK Q(t+1) 0 x x 0 1 0 ↑ 0 1 1 ↑ 1
Eastern Mediterranean University Eastern Mediterranean University 30 30 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’ CLR’ D CLK Q(t+1) 1 0 x x 0 D Q Q CLR Reset PR Preset
Eastern Mediterranean University Eastern Mediterranean University 31 31 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’ CLR’ D CLK Q(t+1) 1 0 x x 0 0 1 x x 1 D Q Q CLR Reset PR Preset
Eastern Mediterranean University Eastern Mediterranean University 32 32 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’ CLR’ D CLK Q(t+1) 1 0 x x 0 0 1 x x 1 1 1 0 ↑ 0 1 1 1 ↑ 1 D Q Q CLR Reset PR Preset
Eastern Mediterranean University Eastern Mediterranean University 33 33 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits The State ● State = Values of all Flip-Flops Example A B = 0 0 D Q Q CLK D Q Q A B y x
Eastern Mediterranean University Eastern Mediterranean University 34 34 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits State Equations D Q Q CLK D Q Q A B y x A(t+1) = DA = A(t) x(t)+B(t) x(t) = A x + B x B(t+1) = DB = A’(t) x(t) = A’ x y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’
Eastern Mediterranean University Eastern Mediterranean University 35 35 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits State Table (Transition Table) D Q Q CLK D Q Q A B y x A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output A B x A B y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 t+1 t t 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0
Eastern Mediterranean University Eastern Mediterranean University 36 36 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits State Table (Transition Table) D Q Q CLK D Q Q A B y x A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next State Output x = 0 x = 1 x = 0 x = 1 A B A B A B y y 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0 t+1 t t
Eastern Mediterranean University Eastern Mediterranean University 37 37 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits  State Diagram D Q Q CLK D Q Q A B y x 0 0 1 0 0 1 1 1 0/0 0/1 1/0 1/0 1/0 1/0 0/1 0/1 AB input/output Present State Next State Output x = 0 x = 1 x = 0 x = 1 A B A B A B y y 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0
Eastern Mediterranean University Eastern Mediterranean University 38 38 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits D Flip-Flops Example: D Q Q x CLK y A Present State Input Next State A x y A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 1 00,11 00,11 01,10 01,10 A(t+1) = DA = A  x  y
Eastern Mediterranean University Eastern Mediterranean University 39 39 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits JK Flip-Flops Example: J Q Q K CLK J Q Q K x A B JA = B KA = B x’ JB = x’ KB = A  x A(t+1) = JA Q’A + K’A QA = A’B + AB’ + Ax B(t+1) = JB Q’B + K’B QB = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1
Eastern Mediterranean University Eastern Mediterranean University 40 40 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits JK Flip-Flops Example: J Q Q K CLK J Q Q K x A B Present State I/P Next State Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1
Eastern Mediterranean University Eastern Mediterranean University 41 41 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits T Flip-Flops Example: TA = B x TB = x y = A B A(t+1) = TA Q’A + T’A QA = AB’ + Ax’ + A’Bx B(t+1) = TB Q’B + T’B QB = x  B A B T Q Q R T Q Q R CLK Reset x y Present State I/P Next State F.F Inputs O/P A B x A B TA TB y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1
Eastern Mediterranean University Eastern Mediterranean University 42 42 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits T Flip-Flops Example: A B T Q Q R T Q Q R CLK Reset x y Present State I/P Next State F.F Inputs O/P A B x A B TA TB y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0/0 1/0 0/0 1/0 1/0 1/1 0/0 0/1
Eastern Mediterranean University Eastern Mediterranean University 43 43 Mealy and Moore Models Mealy and Moore Models The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15). ● The outputs may change if the inputs change during the clock pulse period. ♦ The outputs may have momentary false values unless the inputs are synchronized with the clocks. The Moore model: the outputs are functions of the present state only (Fig. 5-20). ● The outputs are synchronous with the clocks.
Eastern Mediterranean University Eastern Mediterranean University 44 44 Mealy and Moore Models Mealy and Moore Models Fig. 5.21 Block diagram of Mealy and Moore state machine
Eastern Mediterranean University Eastern Mediterranean University 45 45 Mealy and Moore Models Mealy and Moore Models Present State I/P Next State O/P A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 Mealy Mealy For the same state state, the output output changes with the input input Present State I/P Next State O/P A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 Moore Moore For the same state state, the output output does not change with the input input
Eastern Mediterranean University Eastern Mediterranean University 46 46 Moore State Diagram Moore State Diagram State / Output 0 0 / 0 0 1 / 0 1 1 / 1 1 0 / 0 0 1 1 1 0 0 0 1
Eastern Mediterranean University Eastern Mediterranean University 47 47 State Reduction and Assignment State Reduction and Assignment State Reduction Reductions on the number of flip-flops and the number of gates. ● A reduction in the number of states may result in a reduction in the number of flip-flops. ● An example state diagram showing in Fig. 5.25. Fig. 5.25 State diagram
Eastern Mediterranean University Eastern Mediterranean University 48 48 State Reduction State Reduction ● Only the input-output sequences are important. ● Two circuits are equivalent ♦ Have identical outputs for all input sequences; ♦ The number of states is not important. Fig. 5.25 State diagram State: a a b c d e f f g f g a Input: 0 1 0 1 0 1 1 0 1 0 0 Output: 0 0 0 0 0 1 1 0 1 0 0
Eastern Mediterranean University Eastern Mediterranean University 49 49 Equivalent states ● Two states are said to be equivalent ♦ For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. ♦ One of them can be removed.
Eastern Mediterranean University Eastern Mediterranean University 50 50 Reducing the state table ● e = g (remove g); ● d = f (remove f);
Eastern Mediterranean University Eastern Mediterranean University 51 51 ● The reduced finite state machine State: a a b c d e d d e d e a Input: 0 1 0 1 0 1 1 0 1 0 0 Output : 0 0 0 0 0 1 1 0 1 0 0
Eastern Mediterranean University Eastern Mediterranean University 52 52 ● The checking of each pair of states for possible equivalence can be done systematically using Implication Table. ● The unused states are treated as don't-care condition  fewer combinational gates. Fig. 5.26 Reduced State diagram
Eastern Mediterranean University Eastern Mediterranean University 53 53 Implication Table Implication Table  The state-reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined into one if they can be shown to be equivalent. There are occasions when a pair of states do not have the same next states, but, nonetheless, go to equivalent next states. Consider the following state table:  (a, b) imply (c, d) and (c, d) imply (a, b). Both pairs of states are equivalent; i.e., a and b are equivalent as well as c and d.
Eastern Mediterranean University Eastern Mediterranean University 54 54 Implication Table Implication Table The checking of each pair of states for possible equivalence in a table with a large number of states can be done systematically by means of an implication table. This a chart that consists of squares, one for every possible pair of states, that provide spaces for listing any possible implied states. Consider the following state table:
Eastern Mediterranean University Eastern Mediterranean University 55 55 Implication Table Implication Table The implication table is:
Eastern Mediterranean University Eastern Mediterranean University 56 56 Implication Table Implication Table  On the left side along the vertical are listed all the states defined in the state table except the last, and across the bottom horizontally are listed all the states except the last.  The states that are not equivalent are marked with a ‘x’ in the corresponding square, whereas their equivalence is recorded with a ‘√’.  Some of the squares have entries of implied states that must be further investigated to determine whether they are equivalent or not.  The step-by-step procedure of filling in the squares is as follows: 1. Place a cross in any square corresponding to a pair of states whose outputs are not equal for every input. 2. Enter in the remaining squares the pairs of states that are implied by the pair of states representing the squares. We do that by starting from the top square in the left column and going down and then proceeding with the next column to the right.
Eastern Mediterranean University Eastern Mediterranean University 57 57 Implication Table Implication Table 3. Make successive passes through the table to determine whether any additional squares should be marked with a ‘x’. A square in the table is crossed out if it contains at least one implied pair that is not equivalent. 4. Finally, all the squares that have no crosses are recorded with check marks. The equivalent states are: (a, b), (d, e), (d, g), (e, g). We now combine pairs of states into larger groups of equivalent states. The last three pairs can be combined into a set of three equivalent states (d, e,g) because each one of the states in the group is equivalent to the other two. The final partition of these states consists of the equivalent states found from the implication table, together with all the remaining states in the state table that are not equivalent to any other state: (a, b) (c) (d, e, g) (f) The reduced state table is:
Eastern Mediterranean University Eastern Mediterranean University 58 58 Implication Table Implication Table
Eastern Mediterranean University Eastern Mediterranean University 59 59 State Assignment State Assignment State Assignment To minimize the cost of the combinational circuits. ● Three possible binary state assignments. (m states need n-bits, where 2n > m)
Eastern Mediterranean University Eastern Mediterranean University 60 60 ● Any binary number assignment is satisfactory as long as each state is assigned a unique number. ● Use binary assignment 1.
Eastern Mediterranean University Eastern Mediterranean University 61 61 Design Procedure Design Procedure Design Procedure for sequential circuit ● The word description of the circuit behavior to get a state diagram; ● State reduction if necessary; ● Assign binary values to the states; ● Obtain the binary-coded state table; ● Choose the type of flip-flops; ● Derive the simplified flip-flop input equations and output equations; ● Draw the logic diagram;
Eastern Mediterranean University Eastern Mediterranean University 62 62 Design of Clocked Sequential Circuits Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s S0 / 0 S1 / 0 S3 / 1 S2 / 0 0 1 1 0 0 1 0 1 State A B S0 0 0 S1 0 1 S2 1 0 S3 1 1
Eastern Mediterranean University Eastern Mediterranean University 63 63 Design of Clocked Sequential Circuits Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output A B x A B y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 S0 / 0 S1 / 0 S3 / 1 S2 / 0 0 1 1 0 0 1 0 1
Eastern Mediterranean University Eastern Mediterranean University 64 64 Design of Clocked Sequential Circuits Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output A B x A B y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 A(t+1) = DA (A, B, x) = ∑ (3, 5, 7) B(t+1) = DB (A, B, x) = ∑ (1, 5, 7) y(A, B, x) = ∑ (6, 7) Synthesis using D D Flip-Flops
Eastern Mediterranean University Eastern Mediterranean University 65 65 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with D D F.F. F.F. Example: Detect 3 or more consecutive 1’s DA (A, B, x) = ∑ (3, 5, 7) = A x + B x DB (A, B, x) = ∑ (1, 5, 7) = A x + B’ x y(A, B, x) = ∑ (6, 7) = A B Synthesis using D D Flip-Flops B 0 0 1 0 A 0 1 1 0 x B 0 1 0 0 A 0 1 1 0 x B 0 0 0 0 A 0 0 1 1 x
Eastern Mediterranean University Eastern Mediterranean University 66 66 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with D D F.F. F.F. Example: Detect 3 or more consecutive 1’s DA = A x + B x DB = A x + B’ x y = A B Synthesis using D D Flip-Flops D Q Q A CLK x B D Q Q y
Eastern Mediterranean University Eastern Mediterranean University 67 67 Flip-Flop Excitation Tables Flip-Flop Excitation Tables Present State Next State F.F. Input Q(t) Q(t+1) D 0 0 0 1 1 0 1 1 Present State Next State F.F. Input Q(t) Q(t+1) J K 0 0 0 1 1 0 1 1 0 0 (No change) 0 1 (Reset) 0 x 1 x x 1 x 0 0 1 0 1 1 0 (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set) Q(t) Q(t+1) T 0 0 0 1 1 0 1 1 0 1 1 0
Eastern Mediterranean University Eastern Mediterranean University 68 68 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JK JK F.F. F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 x 0 x 0 x 1 x x 1 x 0 x 1 x 0 JA (A, B, x) = ∑ (3) dJA (A, B, x) = ∑ (4,5,6,7) KA (A, B, x) = ∑ (4, 6) dKA (A, B, x) = ∑ (0,1,2,3) JB (A, B, x) = ∑ (1, 5) dJB (A, B, x) = ∑ (2,3,6,7) KB (A, B, x) = ∑ (2, 3, 6) dKB (A, B, x) = ∑ (0,1,4,5) Synthesis using JK JK F.F. 0 x 1 x x 1 x 1 0 x 1 x x 1 x 0
Eastern Mediterranean University Eastern Mediterranean University 69 69 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JK JK F.F. F.F. Example: Detect 3 or more consecutive 1’s JA = B x KA = x’ JB = x KB = A’ + x’ Synthesis using JK JK Flip-Flops B 0 0 1 0 A x x x x x B x x x x A 1 0 0 1 x B 0 1 x x A 0 1 x x x B x x 1 1 A x x 0 1 x CLK J Q Q K x A B J Q Q K y
Eastern Mediterranean University Eastern Mediterranean University 70 70 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with T T F.F. F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State F.F. Input A B x A B TA TB 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 0 Synthesis using T T Flip-Flops 0 1 1 1 0 1 1 0 TA (A, B, x) = ∑ (3, 4, 6) TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
Eastern Mediterranean University Eastern Mediterranean University 71 71 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with T T F.F. F.F. Example: Detect 3 or more consecutive 1’s TA = A x’ + A’ B x TB = A’ B + B  x Synthesis using T T Flip-Flops B 0 0 1 0 A 1 0 0 1 x B 0 1 1 1 A 0 1 0 1 x A B y T Q Q x CLK T Q Q

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Chapter_5_Synchronous_Sequential_Circuit.ppt

  • 1.
    Digital Logic DesignI Synchronous Sequential Logic Mustafa Kemal Uyguroğlu
  • 2.
    2 2 Sequential Circuits Sequential Circuits Combinational Circuit Memory Elements InputsOutputs Asynchronous Synchronous Combinational Circuit Flip-flops Inputs Outputs Clock
  • 3.
    Eastern Mediterranean University EasternMediterranean University 3 3 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 0 1 Q = Q0 Initial Value
  • 4.
    Eastern Mediterranean University EasternMediterranean University 4 4 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 0 1 0 Q = Q0 Q = Q0
  • 5.
    Eastern Mediterranean University EasternMediterranean University 5 5 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 1 Q = 0 Q = Q0
  • 6.
    Eastern Mediterranean University EasternMediterranean University 6 6 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 0 0 1 Q = 0 Q = Q0 Q = 0
  • 7.
    Eastern Mediterranean University EasternMediterranean University 7 7 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 0 Q = 0 Q = Q0 Q = 1
  • 8.
    Eastern Mediterranean University EasternMediterranean University 8 8 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 Q = 0 Q = Q0 Q = 1 Q = 1
  • 9.
    Eastern Mediterranean University EasternMediterranean University 9 9 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 Q = 0 Q = Q0 Q = 1 Q = Q’ 0
  • 10.
    Eastern Mediterranean University EasternMediterranean University 10 10 Latches Latches SR Latch R S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 Q = 0 Q = Q0 Q = 1 Q = Q’ 0 Q = Q’
  • 11.
    Eastern Mediterranean University EasternMediterranean University 11 11 Latches Latches SR Latch R S Q Q S R Q 0 0 Q0 0 1 0 1 0 1 1 1 Q=Q’=0 No change Reset Set Invalid S R Q Q S R Q 0 0 Q=Q’=1 0 1 1 1 0 0 1 1 Q0 Invalid Set Reset No change
  • 12.
    Eastern Mediterranean University EasternMediterranean University 12 12 Latches Latches SR Latch R S Q Q S R Q 0 0 Q0 0 1 0 1 0 1 1 1 Q=Q’=0 No change Reset Set Invalid S’ R’ Q 0 0 Q=Q’=1 0 1 1 1 0 0 1 1 Q0 Invalid Set Reset No change S R Q Q
  • 13.
    Eastern Mediterranean University EasternMediterranean University 13 13 Controlled Latches Controlled Latches SR Latch with Control Input C S R Q 0 x x Q0 1 0 0 Q0 1 0 1 0 1 1 0 1 1 1 1 Q=Q’ No change No change Reset Set Invalid S R Q Q S R C S R Q Q S R C
  • 14.
    Eastern Mediterranean University EasternMediterranean University 14 14 Controlled Latches Controlled Latches D Latch (D = Data) C D Q 0 x Q0 1 0 0 1 1 1 No change Reset Set S R Q Q D C C Timing Diagram D Q t Output may change
  • 15.
    Eastern Mediterranean University EasternMediterranean University 15 15 Controlled Latches Controlled Latches D Latch (D = Data) C D Q 0 x Q0 1 0 0 1 1 1 No change Reset Set C Timing Diagram D Q Output may change S R Q Q D C
  • 16.
    Eastern Mediterranean University EasternMediterranean University 16 16 Flip-Flops Flip-Flops Controlled latches are level-triggered Flip-Flops are edge-triggered C CLK Positive Edge CLK Negative Edge
  • 17.
    Eastern Mediterranean University EasternMediterranean University 17 17 Flip-Flops Flip-Flops Master-Slave D Flip-Flop D Latch (Master) D C Q D Latch (Slave) D C Q Q D CLK CLK D QMaster QSlave Looks like it is negative edge-triggered Master Slave
  • 18.
    Eastern Mediterranean University EasternMediterranean University 18 18 Flip-Flops Flip-Flops Edge-Triggered D Flip-Flop D CLK Q Q D Q Q D Q Q Positive Edge Negative Edge
  • 19.
    Eastern Mediterranean University EasternMediterranean University 19 19 Flip-Flops Flip-Flops JK Flip-Flop D Q Q Q Q CLK J K J Q Q K D = JQ’ + K’Q
  • 20.
    Eastern Mediterranean University EasternMediterranean University 20 20 Flip-Flops Flip-Flops T Flip-Flop D = TQ’ + T’Q = T  Q J Q Q K T D Q Q T D = JQ’ + K’Q T Q Q
  • 21.
    Eastern Mediterranean University EasternMediterranean University 21 21 Flip-Flop Characteristic Tables Flip-Flop Characteristic Tables D Q Q D Q(t+1) 0 0 1 1 Reset Set J K Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q’(t) No change Reset Set Toggle J Q Q K T Q Q T Q(t+1) 0 Q(t) 1 Q’(t) No change Toggle
  • 22.
    Eastern Mediterranean University EasternMediterranean University 22 22 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations D Q Q D Q(t+1) 0 0 1 1 Q(t+1) = D J K Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 Q’(t) Q(t+1) = JQ’ + K’Q J Q Q K T Q Q T Q(t+1) 0 Q(t) 1 Q’(t) Q(t+1) = T  Q
  • 23.
    Eastern Mediterranean University EasternMediterranean University 23 23 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 No change Reset Set Toggle
  • 24.
    Eastern Mediterranean University EasternMediterranean University 24 24 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 No change Reset Set Toggle
  • 25.
    Eastern Mediterranean University EasternMediterranean University 25 25 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 No change Reset Set Toggle
  • 26.
    Eastern Mediterranean University EasternMediterranean University 26 26 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 No change Reset Set Toggle
  • 27.
    Eastern Mediterranean University EasternMediterranean University 27 27 Flip-Flop Characteristic Equations Flip-Flop Characteristic Equations Analysis / Derivation J Q Q K J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 K 0 1 0 0 J 1 1 0 1 Q Q(t+1) = JQ’ + K’Q
  • 28.
    Eastern Mediterranean University EasternMediterranean University 28 28 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Reset D Q Q R Reset R’ D CLK Q(t+1) 0 x x 0
  • 29.
    Eastern Mediterranean University EasternMediterranean University 29 29 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Reset D Q Q R Reset R’ D CLK Q(t+1) 0 x x 0 1 0 ↑ 0 1 1 ↑ 1
  • 30.
    Eastern Mediterranean University EasternMediterranean University 30 30 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’ CLR’ D CLK Q(t+1) 1 0 x x 0 D Q Q CLR Reset PR Preset
  • 31.
    Eastern Mediterranean University EasternMediterranean University 31 31 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’ CLR’ D CLK Q(t+1) 1 0 x x 0 0 1 x x 1 D Q Q CLR Reset PR Preset
  • 32.
    Eastern Mediterranean University EasternMediterranean University 32 32 Flip-Flops with Direct Inputs Flip-Flops with Direct Inputs Asynchronous Preset and Clear PR’ CLR’ D CLK Q(t+1) 1 0 x x 0 0 1 x x 1 1 1 0 ↑ 0 1 1 1 ↑ 1 D Q Q CLR Reset PR Preset
  • 33.
    Eastern Mediterranean University EasternMediterranean University 33 33 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits The State ● State = Values of all Flip-Flops Example A B = 0 0 D Q Q CLK D Q Q A B y x
  • 34.
    Eastern Mediterranean University EasternMediterranean University 34 34 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits State Equations D Q Q CLK D Q Q A B y x A(t+1) = DA = A(t) x(t)+B(t) x(t) = A x + B x B(t+1) = DB = A’(t) x(t) = A’ x y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’
  • 35.
    Eastern Mediterranean University EasternMediterranean University 35 35 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits State Table (Transition Table) D Q Q CLK D Q Q A B y x A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output A B x A B y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 t+1 t t 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0
  • 36.
    Eastern Mediterranean University EasternMediterranean University 36 36 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits State Table (Transition Table) D Q Q CLK D Q Q A B y x A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next State Output x = 0 x = 1 x = 0 x = 1 A B A B A B y y 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0 t+1 t t
  • 37.
    Eastern Mediterranean University EasternMediterranean University 37 37 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits  State Diagram D Q Q CLK D Q Q A B y x 0 0 1 0 0 1 1 1 0/0 0/1 1/0 1/0 1/0 1/0 0/1 0/1 AB input/output Present State Next State Output x = 0 x = 1 x = 0 x = 1 A B A B A B y y 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0
  • 38.
    Eastern Mediterranean University EasternMediterranean University 38 38 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits D Flip-Flops Example: D Q Q x CLK y A Present State Input Next State A x y A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 1 00,11 00,11 01,10 01,10 A(t+1) = DA = A  x  y
  • 39.
    Eastern Mediterranean University EasternMediterranean University 39 39 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits JK Flip-Flops Example: J Q Q K CLK J Q Q K x A B JA = B KA = B x’ JB = x’ KB = A  x A(t+1) = JA Q’A + K’A QA = A’B + AB’ + Ax B(t+1) = JB Q’B + K’B QB = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1
  • 40.
    Eastern Mediterranean University EasternMediterranean University 40 40 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits JK Flip-Flops Example: J Q Q K CLK J Q Q K x A B Present State I/P Next State Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1
  • 41.
    Eastern Mediterranean University EasternMediterranean University 41 41 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits T Flip-Flops Example: TA = B x TB = x y = A B A(t+1) = TA Q’A + T’A QA = AB’ + Ax’ + A’Bx B(t+1) = TB Q’B + T’B QB = x  B A B T Q Q R T Q Q R CLK Reset x y Present State I/P Next State F.F Inputs O/P A B x A B TA TB y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1
  • 42.
    Eastern Mediterranean University EasternMediterranean University 42 42 Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits T Flip-Flops Example: A B T Q Q R T Q Q R CLK Reset x y Present State I/P Next State F.F Inputs O/P A B x A B TA TB y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0/0 1/0 0/0 1/0 1/0 1/1 0/0 0/1
  • 43.
    Eastern Mediterranean University EasternMediterranean University 43 43 Mealy and Moore Models Mealy and Moore Models The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15). ● The outputs may change if the inputs change during the clock pulse period. ♦ The outputs may have momentary false values unless the inputs are synchronized with the clocks. The Moore model: the outputs are functions of the present state only (Fig. 5-20). ● The outputs are synchronous with the clocks.
  • 44.
    Eastern Mediterranean University EasternMediterranean University 44 44 Mealy and Moore Models Mealy and Moore Models Fig. 5.21 Block diagram of Mealy and Moore state machine
  • 45.
    Eastern Mediterranean University EasternMediterranean University 45 45 Mealy and Moore Models Mealy and Moore Models Present State I/P Next State O/P A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 Mealy Mealy For the same state state, the output output changes with the input input Present State I/P Next State O/P A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 Moore Moore For the same state state, the output output does not change with the input input
  • 46.
    Eastern Mediterranean University EasternMediterranean University 46 46 Moore State Diagram Moore State Diagram State / Output 0 0 / 0 0 1 / 0 1 1 / 1 1 0 / 0 0 1 1 1 0 0 0 1
  • 47.
    Eastern Mediterranean University EasternMediterranean University 47 47 State Reduction and Assignment State Reduction and Assignment State Reduction Reductions on the number of flip-flops and the number of gates. ● A reduction in the number of states may result in a reduction in the number of flip-flops. ● An example state diagram showing in Fig. 5.25. Fig. 5.25 State diagram
  • 48.
    Eastern Mediterranean University EasternMediterranean University 48 48 State Reduction State Reduction ● Only the input-output sequences are important. ● Two circuits are equivalent ♦ Have identical outputs for all input sequences; ♦ The number of states is not important. Fig. 5.25 State diagram State: a a b c d e f f g f g a Input: 0 1 0 1 0 1 1 0 1 0 0 Output: 0 0 0 0 0 1 1 0 1 0 0
  • 49.
    Eastern Mediterranean University EasternMediterranean University 49 49 Equivalent states ● Two states are said to be equivalent ♦ For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. ♦ One of them can be removed.
  • 50.
    Eastern Mediterranean University EasternMediterranean University 50 50 Reducing the state table ● e = g (remove g); ● d = f (remove f);
  • 51.
    Eastern Mediterranean University EasternMediterranean University 51 51 ● The reduced finite state machine State: a a b c d e d d e d e a Input: 0 1 0 1 0 1 1 0 1 0 0 Output : 0 0 0 0 0 1 1 0 1 0 0
  • 52.
    Eastern Mediterranean University EasternMediterranean University 52 52 ● The checking of each pair of states for possible equivalence can be done systematically using Implication Table. ● The unused states are treated as don't-care condition  fewer combinational gates. Fig. 5.26 Reduced State diagram
  • 53.
    Eastern Mediterranean University EasternMediterranean University 53 53 Implication Table Implication Table  The state-reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined into one if they can be shown to be equivalent. There are occasions when a pair of states do not have the same next states, but, nonetheless, go to equivalent next states. Consider the following state table:  (a, b) imply (c, d) and (c, d) imply (a, b). Both pairs of states are equivalent; i.e., a and b are equivalent as well as c and d.
  • 54.
    Eastern Mediterranean University EasternMediterranean University 54 54 Implication Table Implication Table The checking of each pair of states for possible equivalence in a table with a large number of states can be done systematically by means of an implication table. This a chart that consists of squares, one for every possible pair of states, that provide spaces for listing any possible implied states. Consider the following state table:
  • 55.
    Eastern Mediterranean University EasternMediterranean University 55 55 Implication Table Implication Table The implication table is:
  • 56.
    Eastern Mediterranean University EasternMediterranean University 56 56 Implication Table Implication Table  On the left side along the vertical are listed all the states defined in the state table except the last, and across the bottom horizontally are listed all the states except the last.  The states that are not equivalent are marked with a ‘x’ in the corresponding square, whereas their equivalence is recorded with a ‘√’.  Some of the squares have entries of implied states that must be further investigated to determine whether they are equivalent or not.  The step-by-step procedure of filling in the squares is as follows: 1. Place a cross in any square corresponding to a pair of states whose outputs are not equal for every input. 2. Enter in the remaining squares the pairs of states that are implied by the pair of states representing the squares. We do that by starting from the top square in the left column and going down and then proceeding with the next column to the right.
  • 57.
    Eastern Mediterranean University EasternMediterranean University 57 57 Implication Table Implication Table 3. Make successive passes through the table to determine whether any additional squares should be marked with a ‘x’. A square in the table is crossed out if it contains at least one implied pair that is not equivalent. 4. Finally, all the squares that have no crosses are recorded with check marks. The equivalent states are: (a, b), (d, e), (d, g), (e, g). We now combine pairs of states into larger groups of equivalent states. The last three pairs can be combined into a set of three equivalent states (d, e,g) because each one of the states in the group is equivalent to the other two. The final partition of these states consists of the equivalent states found from the implication table, together with all the remaining states in the state table that are not equivalent to any other state: (a, b) (c) (d, e, g) (f) The reduced state table is:
  • 58.
    Eastern Mediterranean University EasternMediterranean University 58 58 Implication Table Implication Table
  • 59.
    Eastern Mediterranean University EasternMediterranean University 59 59 State Assignment State Assignment State Assignment To minimize the cost of the combinational circuits. ● Three possible binary state assignments. (m states need n-bits, where 2n > m)
  • 60.
    Eastern Mediterranean University EasternMediterranean University 60 60 ● Any binary number assignment is satisfactory as long as each state is assigned a unique number. ● Use binary assignment 1.
  • 61.
    Eastern Mediterranean University EasternMediterranean University 61 61 Design Procedure Design Procedure Design Procedure for sequential circuit ● The word description of the circuit behavior to get a state diagram; ● State reduction if necessary; ● Assign binary values to the states; ● Obtain the binary-coded state table; ● Choose the type of flip-flops; ● Derive the simplified flip-flop input equations and output equations; ● Draw the logic diagram;
  • 62.
    Eastern Mediterranean University EasternMediterranean University 62 62 Design of Clocked Sequential Circuits Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s S0 / 0 S1 / 0 S3 / 1 S2 / 0 0 1 1 0 0 1 0 1 State A B S0 0 0 S1 0 1 S2 1 0 S3 1 1
  • 63.
    Eastern Mediterranean University EasternMediterranean University 63 63 Design of Clocked Sequential Circuits Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output A B x A B y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 S0 / 0 S1 / 0 S3 / 1 S2 / 0 0 1 1 0 0 1 0 1
  • 64.
    Eastern Mediterranean University EasternMediterranean University 64 64 Design of Clocked Sequential Circuits Design of Clocked Sequential Circuits Example: Detect 3 or more consecutive 1’s Present State Input Next State Output A B x A B y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 A(t+1) = DA (A, B, x) = ∑ (3, 5, 7) B(t+1) = DB (A, B, x) = ∑ (1, 5, 7) y(A, B, x) = ∑ (6, 7) Synthesis using D D Flip-Flops
  • 65.
    Eastern Mediterranean University EasternMediterranean University 65 65 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with D D F.F. F.F. Example: Detect 3 or more consecutive 1’s DA (A, B, x) = ∑ (3, 5, 7) = A x + B x DB (A, B, x) = ∑ (1, 5, 7) = A x + B’ x y(A, B, x) = ∑ (6, 7) = A B Synthesis using D D Flip-Flops B 0 0 1 0 A 0 1 1 0 x B 0 1 0 0 A 0 1 1 0 x B 0 0 0 0 A 0 0 1 1 x
  • 66.
    Eastern Mediterranean University EasternMediterranean University 66 66 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with D D F.F. F.F. Example: Detect 3 or more consecutive 1’s DA = A x + B x DB = A x + B’ x y = A B Synthesis using D D Flip-Flops D Q Q A CLK x B D Q Q y
  • 67.
    Eastern Mediterranean University EasternMediterranean University 67 67 Flip-Flop Excitation Tables Flip-Flop Excitation Tables Present State Next State F.F. Input Q(t) Q(t+1) D 0 0 0 1 1 0 1 1 Present State Next State F.F. Input Q(t) Q(t+1) J K 0 0 0 1 1 0 1 1 0 0 (No change) 0 1 (Reset) 0 x 1 x x 1 x 0 0 1 0 1 1 0 (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set) Q(t) Q(t+1) T 0 0 0 1 1 0 1 1 0 1 1 0
  • 68.
    Eastern Mediterranean University EasternMediterranean University 68 68 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JK JK F.F. F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State Flip-Flop Inputs A B x A B JA KA JB KB 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 x 0 x 0 x 1 x x 1 x 0 x 1 x 0 JA (A, B, x) = ∑ (3) dJA (A, B, x) = ∑ (4,5,6,7) KA (A, B, x) = ∑ (4, 6) dKA (A, B, x) = ∑ (0,1,2,3) JB (A, B, x) = ∑ (1, 5) dJB (A, B, x) = ∑ (2,3,6,7) KB (A, B, x) = ∑ (2, 3, 6) dKB (A, B, x) = ∑ (0,1,4,5) Synthesis using JK JK F.F. 0 x 1 x x 1 x 1 0 x 1 x x 1 x 0
  • 69.
    Eastern Mediterranean University EasternMediterranean University 69 69 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with JK JK F.F. F.F. Example: Detect 3 or more consecutive 1’s JA = B x KA = x’ JB = x KB = A’ + x’ Synthesis using JK JK Flip-Flops B 0 0 1 0 A x x x x x B x x x x A 1 0 0 1 x B 0 1 x x A 0 1 x x x B x x 1 1 A x x 0 1 x CLK J Q Q K x A B J Q Q K y
  • 70.
    Eastern Mediterranean University EasternMediterranean University 70 70 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with T T F.F. F.F. Example: Detect 3 or more consecutive 1’s Present State Input Next State F.F. Input A B x A B TA TB 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 0 Synthesis using T T Flip-Flops 0 1 1 1 0 1 1 0 TA (A, B, x) = ∑ (3, 4, 6) TB (A, B, x) = ∑ (1, 2, 3, 5, 6)
  • 71.
    Eastern Mediterranean University EasternMediterranean University 71 71 Design of Clocked Sequential Circuits with Design of Clocked Sequential Circuits with T T F.F. F.F. Example: Detect 3 or more consecutive 1’s TA = A x’ + A’ B x TB = A’ B + B  x Synthesis using T T Flip-Flops B 0 0 1 0 A 1 0 0 1 x B 0 1 1 1 A 0 1 0 1 x A B y T Q Q x CLK T Q Q