This document discusses input/output (I/O) in computer systems. It defines I/O as the transfer of data between a computer's CPU and memory and external peripheral devices. Peripherals connect to the computer via I/O modules and operate more slowly than the CPU and RAM. The document outlines different types of peripherals and describes generic I/O module functions like controlling data transfer and buffering. It also explains the three main I/O techniques: programmed I/O, interrupt-driven I/O, and direct memory access (DMA), where the I/O module transfers data directly between memory and peripherals without CPU involvement.
Feza BUZLUCA, Bilgisayar Mimarisi Ders Notları, Bölüm 03, Giriş/Çıkış Organizasyonu, Asenkron yol (bellek) erişimi (IO Organization, Asynchronous bus (memory) access)
discuss the drawbacks of programmed and interrupt driven io and des.pdfinfo998421
discuss the drawbacks of programmed and interrupt driven i/o and describe in general the
functionality of the DNA
Solution
Programmed I/O
Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver software control
to access registers or memory on a device.
The CPU issues a command then waits for I/O operations to be complete. As the CPU is faster
than the I/O module, the problem with programmed I/O is that the CPU has to wait a long time
for the I/O module of concern to be ready for either reception or transmission of data. The CPU,
while waiting, must repeatedly check the status of the I/O module, and this process is known as
Polling. As a result, the level of the performance of the entire system is severely degraded.
Programmed I/O basically works in these ways:
Interrupt
The CPU issues commands to the I/O module then proceeds with its normal work until
interrupted by I/O device on completion of its work.
For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved
by the system processor. The actual actions to perform depend on whether the device uses I/O
ports, memory mapping.
For output, the device delivers an interrupt either when it is ready to accept new data or to
acknowledge a successful data transfer. Memory-mapped and DMA-capable devices usually
generate interrupts to tell the system they are done with the buffer.
Although Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in
data transfer of large amount because the CPU has to transfer the data word by word between I/O
module and memory.
The main limitation of programmed I/O and interrupt driven I/O is given below:
Programmed I/O
Each instructions selects one I/O device (by number) and transfers a single character (byte)
Example: microprocessor controlled video terminal.
Four registers: input status and character, output status and character.
Interrupt-driven I/O
Primary disadvantage of programmed I/O is that CPU spends most of its time in a tight loop
waiting for the device to become ready. This is called busy waiting.
With interrupt-driven I/O, the CPU starts the device and tells it to generate an interrupt when it is
finished.
Done by setting interrupt-enable bit in status register.
Still requires an interrupt for every character read or written.
Interrupting a running process is an expensive business (requires saving context).
Requires extra hardware (DMA controller chip).
All these limitation can be overcome by the Introduction of DMA (Direct Memory Access)
To write block of 32 bytes from memory address 100 to device 4
1. CPU writes 32, 100, 4 into the first three DMA registers (memory address, count, device
number)
2. CPU puts code for WRITE (say 1) into fourth (direction) DMA register, which signals DMA
controller to begin operation
3. Controller reads (via bus request as CPU would) byte 100 from memory
4. Controller makes I/O request to write to device 4
5. Controller increments m.
Feza BUZLUCA, Bilgisayar Mimarisi Ders Notları, Bölüm 03, Giriş/Çıkış Organizasyonu, Asenkron yol (bellek) erişimi (IO Organization, Asynchronous bus (memory) access)
discuss the drawbacks of programmed and interrupt driven io and des.pdfinfo998421
discuss the drawbacks of programmed and interrupt driven i/o and describe in general the
functionality of the DNA
Solution
Programmed I/O
Programmed I/O (PIO) refers to data transfers initiated by a CPU under driver software control
to access registers or memory on a device.
The CPU issues a command then waits for I/O operations to be complete. As the CPU is faster
than the I/O module, the problem with programmed I/O is that the CPU has to wait a long time
for the I/O module of concern to be ready for either reception or transmission of data. The CPU,
while waiting, must repeatedly check the status of the I/O module, and this process is known as
Polling. As a result, the level of the performance of the entire system is severely degraded.
Programmed I/O basically works in these ways:
Interrupt
The CPU issues commands to the I/O module then proceeds with its normal work until
interrupted by I/O device on completion of its work.
For input, the device interrupts the CPU when new data has arrived and is ready to be retrieved
by the system processor. The actual actions to perform depend on whether the device uses I/O
ports, memory mapping.
For output, the device delivers an interrupt either when it is ready to accept new data or to
acknowledge a successful data transfer. Memory-mapped and DMA-capable devices usually
generate interrupts to tell the system they are done with the buffer.
Although Interrupt relieves the CPU of having to wait for the devices, but it is still inefficient in
data transfer of large amount because the CPU has to transfer the data word by word between I/O
module and memory.
The main limitation of programmed I/O and interrupt driven I/O is given below:
Programmed I/O
Each instructions selects one I/O device (by number) and transfers a single character (byte)
Example: microprocessor controlled video terminal.
Four registers: input status and character, output status and character.
Interrupt-driven I/O
Primary disadvantage of programmed I/O is that CPU spends most of its time in a tight loop
waiting for the device to become ready. This is called busy waiting.
With interrupt-driven I/O, the CPU starts the device and tells it to generate an interrupt when it is
finished.
Done by setting interrupt-enable bit in status register.
Still requires an interrupt for every character read or written.
Interrupting a running process is an expensive business (requires saving context).
Requires extra hardware (DMA controller chip).
All these limitation can be overcome by the Introduction of DMA (Direct Memory Access)
To write block of 32 bytes from memory address 100 to device 4
1. CPU writes 32, 100, 4 into the first three DMA registers (memory address, count, device
number)
2. CPU puts code for WRITE (say 1) into fourth (direction) DMA register, which signals DMA
controller to begin operation
3. Controller reads (via bus request as CPU would) byte 100 from memory
4. Controller makes I/O request to write to device 4
5. Controller increments m.
computer hardware,
Internal Hardware
Processor (CPU)
Motherboard
RAM
Hard Disk Drive
Sound Card
Video Card
Network Card
Power Supply
External Hardware
Monitor or LCD
Keyboard
Mouse
Printer
Scanner
USB Drive
Internal Hardware
Processor (CPU)
Motherboard
RAM
Hard Disk Drive
Sound Card
Video Card
Network Card
Power Supply
External Hardware
Monitor or LCD
Keyboard
Mouse
Printer
Scanner
USB Drive
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6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
computer hardware,
Internal Hardware
Processor (CPU)
Motherboard
RAM
Hard Disk Drive
Sound Card
Video Card
Network Card
Power Supply
External Hardware
Monitor or LCD
Keyboard
Mouse
Printer
Scanner
USB Drive
Internal Hardware
Processor (CPU)
Motherboard
RAM
Hard Disk Drive
Sound Card
Video Card
Network Card
Power Supply
External Hardware
Monitor or LCD
Keyboard
Mouse
Printer
Scanner
USB Drive
gfgbfvc cd dc c fvfvdbbbbbbb gfgbfvc cd dc c fvfvdbbbbbbb gfgbfvc cd dc c fvfvdbbbbbbb gfgbfvc cd dc c fvfvdbbbbbbb gfgbfvc cd dc c fvfvdbbbbbbb gfgbfvc cd dc c fvfvdbbbbbbb gfgbfvc cd dc c fvfvdbbbbbbb
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
Water billing management system project report.pdfKamal Acharya
Our project entitled “Water Billing Management System” aims is to generate Water bill with all the charges and penalty. Manual system that is employed is extremely laborious and quite inadequate. It only makes the process more difficult and hard.
The aim of our project is to develop a system that is meant to partially computerize the work performed in the Water Board like generating monthly Water bill, record of consuming unit of water, store record of the customer and previous unpaid record.
We used HTML/PHP as front end and MYSQL as back end for developing our project. HTML is primarily a visual design environment. We can create a android application by designing the form and that make up the user interface. Adding android application code to the form and the objects such as buttons and text boxes on them and adding any required support code in additional modular.
MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software. It is a stable ,reliable and the powerful solution with the advanced features and advantages which are as follows: Data Security.MySQL is free open source database that facilitates the effective management of the databases by connecting them to the software.
3. +
Input / Output Function
- Transfer data between the computer (CPU and Memory) and the connected
“peripherals (I/O devices)”.
◼ I/O operations are made by a wide variety of external
devices, simply called “peripherals”, these peripherals are
attached to the computer by a link to an I/O module.
◼ Delivering different amounts of data
◼ At different speeds
◼ In different formats
◼ All peripherals are slower than CPU and RAM
◼ Peripherals need I/O modules through which the exchange
of data can be done.
4. +
Generic Model of I/O Module
An Interface is required between the CPU bus and an I/O device to arrange
data transfer called “ports (I/O Module) ”
5. + External Devices classification :
1-Human readable: suitable for communicating with users.
◼ Screen, printer, keyboard
2- Machine readable, suitable for communicating with
equipment.
◼ Monitoring and control
3- Communication, suitable for communicating with
remote devices.
◼ Modem
◼ Network Interface Card (NIC)
6. +
The I/O devices
◼ The I/O Device Contains:
◼ 1- buffer: to temporary store data
◼ 2- Logic circuit to:
◼ receive command from I/O module for specific function as Read
data,Write data, disk head position.
◼ Provide the I/O device state as “Ready, Not Ready”.
◼ 3- Transducer: convert electrical data to other form of energy
during output and vise versa during input.
For Example: Keyboard and Monitor
When a user press a key , a corresponding binary
code is generated and transmitted to the computer ,
then same code transmitted to the Monitor to
display.
7. +
I/O Module Functions
◼ The major function of an I/O module are:
◼ 1- Control & Timing, to coordinate the flow of traffic between internal
resources & external devices.
◼ 2- CPU Communication: Involves command decoding, data, status
reporting, address recognition
◼ 3- Device Communication: Involves commands, status information, and
data
◼ 4- Data Buffering: Performs the needed buffering operation to balance
device and memory speeds
◼ 5- Error Detection: Detects and reports transmission errors
8. +
I/O Steps (transfer of data between
cpu & external device)
1- CPU asks the I/O module to check the device status
2- The I/O module returns the device status
3- If ready, the CPU requests the transfer of data
4- I/O module gets data from external device (8 or 16 bits,…)
5- The I/O module transfers data to the CPU
13. +
Example: 82C55 Programmable
Peripheral Interface(continued)
◼ The Control register is loaded
by the CPU to control the
Operation mode:
◼ Mode 0 : programmed I/O
◼ Ports A,B, and C programmed
as buffered input or output .
◼ Mode 1: Interrupt driven I/O
◼ Port A and B programmed as
buffered input or output. Port C
used for handshaking, strobe ,
and Interrupt request signals
14. +
USING 82C55A with Mode1 operation to
interface with Keyboard/Display
Port A is input from keyboard, PortB is output to display, ½ Port C
is used for handshaking and Interrupt request for the keyboard, the
other half for the display.
15. + Direct Memory Access (DMA)
◼ In the previous techniques, interrupt driven and
programmed I/O require active CPU intervention to transfer
data between memory and an I/O module, and any data
transfer must traverse through the cpu, so:
◼ The transfer rate is limited by the speed with which the cpu
can test and service a device.
◼ The CPU is tied up, a number of instructions must be
executed for each I/O transfer.
◼ The DMA module is the solution
◼ In this mode, the I/O module and main memory exchange
data directly, without involving the processor.
16. +
DMA Function and operation
◼ The DMA involved additional Module (hardware) on the system bus.
◼ The DMA module must use the bus only when the cpu does not need it,
or it forces the cpu to suspend operation temporarily.
◼ When the cpu wishes to read/write a block of data it sends the following
information to the DMA module:
◼ The requested operation Read or Write
◼ The I/O device address
◼ The starting address of memory block for data to be R/W
◼ The amount of data to be transferred
◼ Then the CPU carries on with other work
◼ DMA controller deals with data transfer and sends interrupt when
finished
19. +
Direct Memory Access (DMA 8237)
◼ Used to exchange large amounts of data between The I/O devices and
main memory .
◼ 1- The CPU initiate the transfer (determine location of data on I/O
device - the starting location in memory - the size of the block -
read/write)
◼ 2- The CPU do other operations while the transfer is in progress.
◼ 3-The DMA Controller supplies the memory and I/O with control
signals and memory address information during the DMA transfer.
◼ 4-the CPU receive an interrupt from the DMA controller once the
operation has been done.
◼ The DMA 8237 has 8 channels, each channel is dedicated to I/O device
as disk drive controllers, graphics cards, network cards and sound
cards.
◼ South bridge in ISA bus contains two DMA . (not in PCI bus)