This document discusses trends in integrated circuit applications and technologies. It focuses on artificial intelligence, internet of things, and system-on-chip designs. The document presents diagrams of typical system-on-chip architectures that integrate processors, memory, and other components. It also discusses challenges related to the growing gap between computing power and data storage, and approaches to address this like near-memory computing and computing in memory. The overall trends are driving the development of more complex, specialized integrated circuits.

1. Applications and Trends of ICs
Jin-Fu Li
Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
Taoyuan, Taiwan

2. Global Semiconductor Sales by Month (89-21)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
Source: Semiconductor Industry Association (SIA)
PC
3C
Smart
Handheld
AIoT

3. AIoT
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
AIoT
Algorithm Infrastructure
Artificial Intelligence Internet of Things

4. AIoTs
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
Smart Cars
Smart Energy
Smart Home
Smart Appliances
Smart Control
Smart Lighting
….
Smart Health

5. A Generic IoT Topology
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
Source: B. Krysiak, STMicroelectronics

6. System-on-Chip (SOC)
 A product class and design style that integrates technology and design elements
from other system driver classes (microprocessor unit, embedded memory,
analog/mixed-signal component—as well as reprogrammable logic) into a wide
range of high-complexity, high-value semiconductor products (ITRS 2011)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

7. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
Fundamental Elements of Electronic Systems
Computation
Data (Content) Communication
Processor (multi-core architecture)
Memory
Interface; Bus; Network

8. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
Conventional Computer Architecture
Main Memory System
Von Neumann Architecture
Input/Output
Arithmetic
and
Logic Unit
Operational
Registers
Program
Counter
Control Unit
Data/Instruction
Address
Central Processing Unit

9.  Multi-core chip architecture
 Use multiple identical cores to design a chip
 Network-on-chip communication infrastructure
 Multiple point-to-point data links interconnected by switches (i.e., routers)
Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
Typical SOC Chip Architecture
Source: IEEE Computer, 2005.
DDR2
Controller
DDR2
Controller
μ
Engine
Source: IEEE Micro, 2007.
RAM unit
Compute unit

10. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
SOC Consumer Portable Driver Architecture
Source: ITRS 2011

11. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
Examples
Source: IEEE JSSC, 2006.
SPARC V9 (Sun) Cell Processor (IBM)
Source: IEEE JSSC, 2006.
Teraflops processor (Intel)
Source: IEEE Micro, 2007.
Source: IEEE Micro, 2007.
4x4 mesh built with Xpipes
library components
Niagara2 (Sun)
Source: IEEE JSSC, 2008.

12. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
Cell Processor (JSSC, Jan. 2006)

13. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
Example: Niagara2 & POWER6 (JSSC, 2008)
Niagara2 (Sun) POWER6 (IBM)
Design-for-Testability Features:
1. 32 Scans + ATPG
2. BIST for arrays
3. ….
Design-for-Testability
Features:
1. Logic BIST
2. BIST for arrays
3. BISR for arrays
4. …

14. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
Example: SPARC (JSSC, 2011)
Process: TSMC 40nm
Metal layers (Cu): 11
Transistor types: 4
# of Cores: 16
6MB L2 cache
Die area: 377mm2
# of pins: 2117

15. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
The Bit Picture ─ Gap Between Computing & Data

16. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
The Bit Picture ─ Power
Sources: J. Lunteren, IBM
(refer to S. Borkar, “Exascale computing – a fact or a fiction?,” IPDPS, 2013)
Sources: J. Lunteren, IBM
(refer to R. Nair, “Active Memory Cube,” 2nd Workshop on Near-
Data Processing, 2014)
Sources: ITRS 2011

17. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
Conventional Computing Architecture
Processor Main Memory
Bottleneck
(Data Width & Latency)
Processor Main Memory
Cache
Source: H. Kim, et al.,
MEMSYS’15

18. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
Near Memory Computing & Computing in Memory
 Overcome the memory wall & power wall
◼ Bring computation closer to the data
◼ Reduce power-expensive data transfer
 Approaches
◼ Near memory computing (NMC)
◼ Computing in memory (CIM)
Processor Memory
computing
computing
Computing in Memory (PIM)
Near Memory Computing (NMC)
3D Integration Technology

19. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
What will you learn from this course?
Source: T. Kurafuji, et al., JSSC 2011
1. Low-power design
2. Design-for-test
Infrastructure
Subsystem
Subsystem
Chip Architecture