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ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011     Performance Analysis of Interconnect Driv...
ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011                                              ...
ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011also increases exponentially in subthreshold r...
ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011            Figure 8. PDP as function of suppl...
ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011                                              ...
ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011               TABLE I. PROCESS ASSUMPTION    ...
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Performance Analysis of Interconnect Drivers for Ultralow Power Applications

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ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.

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Performance Analysis of Interconnect Drivers for Ultralow Power Applications

  1. 1. ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011 Performance Analysis of Interconnect Drivers for Ultralow Power Applications S.D.Pable, Mohd. Hasan Department of Electronics Engineering Zakir Husain College of Engg. and Technology Aligarh Muslim University, Aligarh, U.P., IndiaAbstract—ultralow power consumption requirement of low these limitations, the use of the bundles of metallic carbonthroughput applications needs to operate circuits in nanotubes (CNT) as interconnect has been proposed as asubthreshold region where subthreshold leakage current is used possible replacement for Cu interconnect [3][4].as active current for necessary computations. This paper Electromigration is negligible in Cu interconnect withinvestigates the impact of interconnect drivers on digital circuit subtheshold circuits because of low current density but higherperformance in subthreshold region. In particular, we have resistance of driver degrades interconnects performances.investigates the performance of Si-MOSFET and CNFETs at32nm deep submicron technology node. Performance Analysis With reported current density of around 109 A/cm2, CNTis carried out for different interconnect drivers driving global have larger current carrying capabilities than traditional Cuinterconnect. We have proposed an optimized CNFET driver interconnect of the order of 103 A/cm2. For Nanotube basedwhich gives the significant improvement in delay and PDP over interconnects previous research primarily focused on impactconventional CNFET in subthreshold for global and semi-global of RLC on power dissipation and delay [5][6]. In this workinterconnect length. HSPICE device model files generated from equivalent RLC parameters of the interconnect line are“Nano CMOS” tool are use for Si-MOSFET to analyze the extracted from PTM [7] tool for Cu. The equivalent RLCimpact of Process and Temperature (P, T) variations on parameters of CNT interconnect are extracted using Carbonrobustness of circuit for fair comparison with CNFET. Nanotube Interconnect Analyser (CNIA) [8] withVariability of design metric parameters is evaluated by applyingGaussian distribution using Monte Carlo simulation run. interconnect geometry suggested in [9]. Performance analysis of different interconnectIndex Terms— Subthreshold, Ultra-low power, CNFET, Monte- drivers is carried out for CNT and copper wire interconnectCarlo analysis. for different semi-global and global interconnect lengths. For fair comparison between MOSFET and Carbon Nano I INTRODUCTION Tube Field Effect Transistors (CNFET) drivers same Vth is selected. For simulation purpose, we have used PTM model Minimizing power consumption is a challenging parameter of Si-MOSFET at 32nm technology node [7]. Hightask to the researchers for designing digital circuits with ultra performance Stanford CNFET device model files whichlow power (ULP) digital portable applications. Due to successfully accounts for CNFET practical non-idealities,aggressive scaling of transistor size according to Moore’s such as scattering, effects of the source/drain extensionlaw, gate leakage, drain substrate junction band to band region, and inter-CNT charge screening effects [6] are usedtunneling current and subthreshold current increases for CNFET simulation.significantly in super threshold, limiting further scaling down The rest of the paper is organized as follows. Inof devices for ULP applications. Recently, subthreshold section II, basic structure of CNFET is explores. In sectionoperating region is of very much interest to reduce the energy III, CMOS and CNFET device performance analysis carriedup to the ultralow levels. Subthreshold operation of transistor out to obtain optimal parameter for CNFET to achieve highercan have order of magnitude power saving over super drive current. Section IV compares the interconnect driversthreshold circuits [1]. In subthreshold operating region performances for Cu and CNT interconnects. In section V,leakage current is used as drive current. This small leakage variability analysis of CMOS and CNFET basedcurrent, however limits the maximum performance at which interconnects resource is carried out using sufficient Montethe subthreshold circuit can be operated. Since supply voltage Carlo simulation run and Section VI draws the conclusion(VDD) is less than threshold voltage (Vth), delay increases from this paper.exponentially [1]. Subthreshold circuits operation uses lowVDD to minimize the energy consumed by digital circuits and II BASIC STRUCTURE OF CNFEThas thus become popular option for research in ULP. As CMOS process scales into the deep submicron CNFETs is one of the most promising devices amongregion, lithography limitation, electro migration and delay emerging technologies. Most of the fundamental limitationsof copper interconnect has driven the need to find alternative for traditional MOSFETs are mitigated in CNFETs. Researchinterconnect solution [2]. In order to overcome community actively investigates CNFET as promising device for integrated circuit technology at the end or beyond the ITRS roadmap [2]. The CNFET offers many potential© 2011 ACEEE 30DOI: 01.IJEPE.02.01.71
  2. 2. ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011 The switching energy of CNFET is proportional to capacitance of CNFET and given by, [13] Energy CNFET, n  CCNFET,n V DD 2 (4) Where, CCNFET, n is capacitance of CNFET gate and is approximately equal to its gate capacitance (CCNFET,n). Gate capacitance of CNFET with n number of tubes is given by is given by, CCNFET, n  n.C g L  C W (5) -CNT1 g, CNT g-parasitic g,CNT Figure 1. Basic structure of CNFET Where, Wg, CNT is width of CNFET and Lg, CNT is the length of the gate. Cg-CNT1 is almost constant for n. [13].advantages with respect to MOSFET due to improvement in Total gate capacitance is proportion to number of CNTs inCV/I of intrinsic CNFET (19, 0). CNFETs show 13×CV/ with channel, length of channel and pitch. It is necessary to useI improvement over NMOS in superthreshold region at 32nm optimum value of number of tubes and pitch to increase thetechnology node due to near ballistic CNT transport [6].These drive current as well as to keep the capacitance withinadvantage leads us to investigate the CNFET performance acceptable limit.in subthreshold region also. The single wall carbon nanotubes (SWCNTs) is one III.CMOS AND CNFET INVERTER ANALYSIS INdimensional conductor obtained by sheets of grapheme rolled SUBTHRESHOLD REGIONin the forms of tubes, depending on the chirality’s, the singlewalled CNTs can be either metallic or semi conducting A. Subthreshold leakage Current[10][11]. CNFET is obtained by replacing the channel of a For very long wire, interconnect delay would be soconventional MOSFET by a number of carbon nanotubes, long that it can be dominate the gate delay. In ICs, a globalas shown in Fig. 1. As shown in Fig. 1 CNTs are placed on wire tends to be very long since they must be distributed allthe bulk substrate (k2), a high (k1) dielectric separates the over the chip. These wires are associated with clocks, busses,CNTs from metal gate electrode by an insulator thickness and other major signals in the design. Since delay for longTox=4nm with dielectric constant of 16. The diameter of wire is quadratic with respect to interconnect length (L), theCNT is given by the (1), standard solution is to insert repeaters or buffer periodically along the wire. As drive current in subthreshold circuit is a m 2  mn  n 2 D CNT  (1) leakage current due to diffusion, therefore delay penalty is π very high which degrades the circuit performance in Where (m, n) are chirality number of CNT, ‘a’ is Lattice subthreshold regime. To overcome this problems driver withconstant (a=2.49e-10). SWCNTs can be grouped as either better delay response needed to be design. metallic nanotubes if m-n is an integer multiple of 3 or Unlike conventional CMOS in which the drain current IDS is semiconducting nanotubes if m-n is not an integer dominated by transport of carrier due to drift, diffusion multiple of 3 current dominates in subthreshold operation. Transistors are Threshold voltage of CNFET given by (2) [12], operated in subthreshold region by keeping VDD less than the Vth and leakage current flowing through the device is 3 aV  used as drive current for ultra low power applications. VTH  (2) 3 DCNT Subthreshold current is exponentially dependant on gate toWhere V  3.03 q is the carbon PI-PI bond energy. . source voltage (VGS) because channel of transistor is not inverted. Subthreshold current is given by (5),In this work, chirality numbers (m, n)= 13,0 is used for 1nmCNT diameter which gives Vth near to Vth of MOSFET at (VGS -Vth + VDS ) -VDS32nm technology node. Drive current in CNFET is function ID = I0e nVT (1 - e VT ) (5)number of CNTs per device (n), device transconductance Where I0 is the drain current when VGS=0V[14].gCNFET, VDD, Chirality vectors and hence CNT diameter and Wvoltage drop across the doped CNT source region (VSS). I 0   0 C ox (n  1)VT 2 (6)gCNFET, decreases with increasing the inter CNT pitch where Las Vth is constant for given diameter. Delay of CNFET given Where Vth is transistor threshold voltage, n is subthresholdby, [13]. slop factor (n=1+Cd/Cox), VT is the thermal voltage, η is DIBL coefficient. C CNFET, n VDD TCNFET, n α B. CNFET optimisation for subthreshold region (3) I CNFET , n Since subthreshold leakage current in Si-MOSFET is exponential function of supply voltage resistance of device© 2011 ACEEE 31DOI: 01.IJEPE.02.01.71
  3. 3. ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011also increases exponentially in subthreshold region. Insubthreshold domain this increase in resistance dominatesthe interconnect resistance as shown in Fig.2.Therefore it isnecessary to examine the scope of alternative device insubthreshold interconnect resources applications. In thissection we compared the performance of CNFET asinterconnect driver with Si-MOSFET in subthreshold regionfor global interconnect length from 200ìm to 1000ìm and forsemi-global interconnect length ranging from 100ìm to 500ìmwith Cu and MWCNT as interconnects. Since device technology parameters designed forsuperthreshold region may not give the optimum Figure 4. Drive current as function of supply voltage for various CNT pitchperformance in subthreshold region. Hence it is necessaryto evaluate the performance of CNFET for different deviceparameters in subthreshold region to optimize these deviceparameters for better performance. Fig. 3 shows Ids asfunction of VDD at various gate oxide thicknesses. It is foundthat current increases exponentially up to 200mV and thensaturated, at TOX=2nm drive current shows 36% improvementover TOX=4nm due higher gate control over channel. Fig. 4shows I-V characteristics of CNFET at various inter CNTpitch and it is observe that varying pitch above 20nm doesnot show any significant advantage in Ids. Analysis fromFig. 3 is verified by measuring delay of FO4 at TOX=2nmand TOX=4nm, pitch=20nm as shown in Fig.5. Figure 2. Driver resistance and interconnect resistance as function of supply voltage and interconnect length respectively Figure 6. Drive current as a function of supply voltage A delay improvement of 67.5% is seen for TOX=2. Since as TOX reduces the charge distribution become tighter and the charge tends to accumulate just over the CNT channel, increasing drive current [15]. Conventional N-CNFET key parameters are Tox=4nm, Kox=16, pitch=20nm, [12]. Figure 3. Drive current as function of supply voltage© 2011 ACEEE 32DOI: 01.IJEPE.02.01.71
  4. 4. ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011 Figure 8. PDP as function of supply voltage To optimize CNFET (Opt-.CNFET) the selectedparameters are Tox=2nm from Fig. 3, pitch=20nm, numberof CNT tubes=10. Fig.6 shows I-V characteristicscomparison for NMOS, conventional NCNFET andOpt.CNFET. From simulated graph it is seen that Opt.NCNFET device is having better I-V characteristics overConventional NCNFET and NMOS device. For noise margincomparison between CNFET and CMOS device we havesimulate the device for voltage transfer characteristics. Fig.7 shows voltage transfer characteristics (VTC) of minimumsize Si-MOSFET and CNFET. For CNFET VTC curve issymmetric and switching threshold is at VDD/2 (200mv) and173mV for SI-MOSFET which degrades the SNM of Si-MOSFET in subthreshold. CNFET is having steeper curvesin transition region. This contributes to improvement in SNMover Si-MOSFET. To evaluate the performance comparisons betweenCMOS, CNFET and Opt. CNFET devices at circuit level,FO4 is use as a test bench for design metric comparison.Fig. 8 shows the Power Delay Product (PDP) as function ofVDD. From Fig. 8 it is clear that Opt. CNFET showsimprovement in PDP over conventional CNFET and CMOSdue to improvement in delay. Figure 11. PDP as function of global Cu interconnect lengthIV.PERFORMANCE ANALYSIS OF INTERCONNECT DRIVERS FOR CU AND CNT In any circuit or chip, the individual gates need tobe connected. While it is possible to use metals as inconventional circuits to make interconnects, the use ofmetallic carbon nanotubes would be much more desirabledue to better electrical properties. The ballistic transport ofthe metallic nanotubes provides significantly lower resistancein interconnect as compared to Cu. Fig. 9 show the test benchused for interconnect simulation with FO4 load .Theinterconnect considered for simulation is global and semi-global Cu and CNT. Fig. 10 and Fig.11 shows the delay andPDP performances of CMOS, CNFET and opt. CNFET baseddrivers for global Cu interconnect; similarly Fig. 12 and Fig.13 shows performances for MWCNT global interconnectlength from 200µm to 1000µm. Figure 12. Delay as function of global MWCNT interconnects length.© 2011 ACEEE 33DOI: 01.IJEPE.02.01.71
  5. 5. ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011 It is observed from these figures that CNFET based driver shows the 42% and 46% improvement in delay and PDP over Si-MOSFET based drivers at 1000µm interconnect length. Optimizing the CNFET parameters shows 52% and 63% performance improvement in delay and PDP over the SI-MOSFET based interconnect resource. It is also observed from Fig.10 to Fig. 15 that, replacing the Cu interconnect by MWCNT interconnect does not provide any significant advantage in delay as well as PDP due to higher driver resistance of Si-MOSFET in subthreshold region as shown in Fig.2. Fig. 14 and Fig. 15 shows the delay and PDP performances of semi-global interconnect of length 100 µm to 500 µm. CNFET and Opt.CNFET drivers shows significant improvement in delay and PDP over Si-MOSFET based interconnect drivers. Figure 13. PDP as function of global MWCNT interconnect length V.VARIABILITY ANALYSIS Random variation in process parameters, VDD and temperature (PVT) are posing a major design challenges for subthreshold circuit design. It is important to investigate the performance variability for the optimal device. There are a variety of device parameter variations and imperfection caused by today’s CNT synthesis/fabrication technique,(1) CNT diameter and chirality control , (2)Doping level control,(3) The probability of a CNT to be metallic [12]. Test bench used for interconnect simulation is shown in Fig. 9 for the analysis of process and temperature variation on circuit performance. Table I shows the device variable parameters and process variation assumption for the variability analysis. A 13% random variation is given to the CNT diameter so that it will reflect 10% random variation in Vth. Si-MOSFET HSPICE model files are generated from specific tool called “Nano CMOS” 32nm technology forFigure 14. Delay and PDP as function of semi global Cu-interconnect equal Vth for fair variability comparison with CNFET at length (13,0) chirality vector.. Ratio of mean (µ) and standard deviation (σ) for delay and PDP is calculated by Monte Carlo simulation for 50 runs per simulation. CNT diameter affects not only the CNT source and drain resistance, but also the conductivity of the channel [16]. TOX variation also affects the drive current of CNFET. Table 2 and Table 3 give variability coefficient (dispersion) (σ/ μ) for PDP and delay respectively. As shown in tables below, it has been found that CNFET (T OX=4nm) have superior robustness against process and temperature variations. Figure 15. Delay and PDP as function of semi global MWCNT interconnect length© 2011 ACEEE 34DOI: 01.IJEPE.02.01.71
  6. 6. ACEEE Int. J. on Electrical and Power Engineering, Vol. 02, No. 01, Feb 2011 TABLE I. PROCESS ASSUMPTION Reducing the variability problems in optimized CNFET drivers will further allow to reduce the supply voltage for ultra low energy applications REFERENCES [1] Hendrawan Soeleman, Kaushik Roy and Bipul C.paul,”Robust subthreshold logic for ultralow power operation,” in IEEE transactions on very large scale Integration (VLSI) system,Vol.9,No.1,pp. 90-99, Feb.2001 [2] International Technology Roadmap for Semiconductors., 2005 http://www.itrs.net. [3] Khyoupin khoo,et al, “Aspect ratio dependence of the resistivity of Fine Cu Interconnects,” in Japanese Journal of Applied physics, Vol.46, No.7A, pp 4070-4073, July2007. TABLE II. VARIABILITY COEFFICIENT OF PDP [4] F.Kreupl et al, “Carbon nanotube for interconnect application,” IEEE IEDM technical digest, pp 683 686, December 2004. [5] Fred Chen,et al, “Scaling and evalution of carbon nanotube interconnects for VLSI application,” in Nano-net’07,pp 24- 26, Sep. 2007. [6] J.Deng and H.-S.P.Wong, “A compact SPICE model for carbon nanotubes field effect transistors including non- idealities and its application-part I: Model of the intrinsic channel region,” Trans. IEEE Electron Devices, Vol.54, TABLEII I. VARIABILITY COEFFICIENT OF DELAY no.12, pp. 3186-3194, Dec. 2007 [7] http://www-device.eecs.berkeley.edu/~ptm/ [8] [online]. Available: http//www.nanohub.org/tools [9] H. Li, et al., Modeling of carbon nanotube interconnects and comparative analysis with Cu interconnects, in Proceedings of the Asia-Pacific Microwave Conference (APMC ’06), 2006.M. [10] Dresselhaus,G. Dresselhaus,and Ph. Avouris, “Carbon nanotubes: synthesis, structure properties and applications,” Springer-Verlag berlin,2001. VI. CONCLUSION [11] H.S.P.Wong,J.Deng, .Hazeghi,t.Krishnamohan,G.C.Wan, “Carbon nanotubes transistor circuits-models and tools for Interconnect drivers are successfully analyzed using design and performance optimization”,ICCAD,pp.651-654CMOS and CNFET devices at deep submicron technology [12] Jie Deng, “Device modeling and circuit performancenode. We have explored optimized CNFET in subthreshold evaluation for nanoscale devices: silicon technology beyondinterconnect applications. It is observed that CMOS devices 45nm node and carbon nanotube field effect transistors”,Ph.dare more prone to variation than CNFET. CNFET driver thesis, Stanford University,2007driving 1000µm cu-interconnect show 42% and 46% delay [13] C.Enz , F.Krummenacher and E.Vittoz, “An Analytical MOSand PDP improvement at 1000µm over Si-MOSFET based Transistor model valid in All region of operation and Dedicated to low-voltage and low current application,”buffers. Optimizing the CNFET parameters shows 52% and Special issues of the Analog integrated circuits and signal63% performance improvement in delay and PDP over the processing journal on Low-voltage and low powerSi-MOSFET based interconnect resource. Design,vol.8,pp.83-114,July 1996. The robustness of the drivers against process and [14] K.Roy, S.Mukhopadhay and H.Mahmmod, “Leakage currenttemperature variation has also investigated. From variability mechanisms and leakage reduction techniques in deep-subpoint of view, for Si-MOSFET there is tremendous impact micrometer CMOS circuits,” proceeding of the IEEE, vol.91,of process variation for subthreshold operation due to no.2, pp.305-327, Feb.2003.exponential dependence of current on the threshold voltage, [15] Kureshi A.K.,Mohd.Hasan, “Performance comparision ofwhere as in CNFET threshold voltage is inversely CNFET and cell in deep Submicron,” journal of Microelectronics,vol 40,No.6,pp. 179-182, June 2009.proportional to diameter of CNT. Optimized CNFET shows [16] Nishant Patiln,et al, “Circuit-level performancemore variation than conventional CNFET. benchmarking and scalability analysis of carbon nanotube transistor circuits,” IEEETrans.on Nanotechnology, Vol.8, No.1,, pp.37-45, January 2009.© 2011 ACEEE 35DOI: 01.IJEPE.02.01.71

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