The document presents a proposed built-in self-repair (BISR) scheme for multiple embedded memories. It discusses testing embedded memories using built-in self-test (BIST) and repairing faults using built-in redundancy analysis (BIRA). The proposed approach uses parallel BIST to test memories concurrently and then serial BIRA to repair faulty memories one by one, prioritizing larger memories. This trades off test time and repair time against optimal repair rate and reduced area overhead.

1. Presented By
Yogesh Pal
M.Tech(VLSI)
172221013

2.  Introduction
 Objective
 Types of BISR Methods
 Proposed BISR Scheme
 Conclusion
 References

3.  Built-in Self-repair is used to test semiconductor
embedded memories.
 BISR scheme includes built-in self test(BIST) and
built-in redundancy analysis(BIRA), to test and
repair embedded memory.
 BISR scheme based on a self-test and repair
processor can perform multiple time memory
repair.

4.  The performance of BISR is evaluated with BIST
and BIRA.
 BIST Criteria:
Test-Time, Fault-Coverage and Area-
Overhead
 BISR Criteria:
Repair-Rate, Repair-Time and Area-
Overhead
 Main objective of BISR is reduce test-time and
repair time, high repair rate and low area-
overhead

5.  There are three methods for multiple memories are
I. Parallel test and Parallel Repair ( n BIST and n
BIRA)
II. Parallel test and Series Repair ( n BIST and 1
BIRA)
III. Series test and Series Repair ( 1 BIST and 1
BIRA)

6.  Memories are tested and classified as faulty
memory or fault-free memory by parallel test
procedure.
 Fault-free memory are excluded.
 Faulty memory are tested serially and repaired
according to the size of memories in descending
order.

7. Figure : Block diagram of the proposed BISR architecture

8. Figure : Block diagram of the proposed BIST and wrapper modules

9. Figure : Block diagram of the proposed BIRA architecture

10.  All memories are concurrently tested by the small dedicated
BIST to figure out the faulty, the number of faults, and
irreparability.
 Only faulty memories are serially tested and repaired by the
global BIRA according to the sizes of memories in
descending order.
 The proposed BISR scheme finds the optimum point
between the test and repair time, and the area overhead by
maintaining the optimal repair rate.
 The verification procedure is simply conducted through the
parallel test.
 Therefore, the proposed BISR scheme is a solution that
trades off test and repair time, and area overhead to
accomplish an optimal repair rate for multiple embedded
memories in the SoC.

11.  Wooheon Kang, Changwook Lee, Hyunyul Lim, and Sungho Kang “Optimized
Built-in Self-Repair for multiple memories” IEEE TRANSACTIONS ON VERY
LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 6, JUNE
2016
 C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for
memory yield improvement,” IEEE Trans. Rel., vol. 52, no. 4, pp. 386–399, Dec.
2003.
 C.-H. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair
design for embedded memories,” in Proc. 12th Asian Test Symp., Nov. 2003, pp.
366–371.
 T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: A reconfigurable built-in self-
repair scheme for random access memories in SOCs,” IEEE Trans. Very Large
Scale Integr. (VLSI) Syst., vol. 18, no. 6, pp. 921–932, Jun. 2010.
 C. H. Stapper, A. N. McLaren, and M. Dreckmann, “Yield model for productivity
optimization of VLSI memory chips with redundancy and partially good product,”
IBM J. Res. Develop., vol. 24, no. 3, pp. 398–409, May 1980.