An Arm processor is a type of central processing unit (CPU) based on the RISC (Reduced Instruction Set Computing) architecture. ARM stands for Advanced RISC Machine. These processors are known for their energy efficiency and are widely used in mobile devices, embedded systems, and increasingly in servers and desktops. Here's a more detailed explanation: Key Characteristics: RISC Architecture: Unlike the more complex instruction sets found in some other processors (like x86), ARM processors use a streamlined set of instructions, which contributes to their efficiency. Energy Efficiency: ARM processors are designed to consume less power, making them ideal for battery-powered devices like smartphones, tablets, and wearables. Licensing Model: ARM Holdings, the company that designs the architecture, licenses it to other companies who then design and manufacture the actual processors. Wide Range of Applications: ARM processors are found in a vast array of devices, including smartphones, tablets, laptops, embedded systems, and even some supercomputers. Examples of ARM-based devices: Smartphones and Tablets: Most smartphones and tablets, including those from Apple, Samsung, and Qualcomm, utilize ARM processors. Laptops and Desktops: Apple's M1, M2, and M3 chips used in MacBooks and iMacs are based on the ARM architecture. Embedded Systems: ARM processors are commonly found in a wide range of embedded systems, such as those in cars, industrial equipment, and consumer electronics. Servers: ARM processors are increasingly being used in servers, particularly in cloud computing environments, due to their energy efficiency and scalability. In essence, ARM processors are a popular choice for devices where power consumption and size are critical factors, while still offering sufficient performance for demanding tasks. The ARM core uses RISC architecture. The RISC philosophy is implemented with four major design rules: 1. Instructions – RISC processors have a reduced number of instruction classes. These classes provide simple operations that can each execute in a single cycle. The compiler or programmer synthesizes complicated operations (a divide operation) by combining several simple instructions. Each instruction is a fixed length to allow the pipeline to fetch future instructions before decoding the current instruction. In contrast, in CISC processors the instructions are often of variable size and take many cycles to execute. 2. Pipelines —The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle for maximum throughput. There is no need for an instruction to be executed by a mini program called microcode as on CISC processors. 3. Registers—RISC machines have a large general-purpose register set. Any register can contain either data or an address. In contrast, CISC processors have dedicated registers for specific purposes. 4. Load-store archi

1. ARM Processor
Prepared by
DEBASISH MOHANTA
DEPARTMENT OF ELECTRICAL ENGINEERING
GOVERNMENT COLLEGE OF ENGINEERING, KEONJHAR

2. The RISC Design Philosophy
 RISC is a design philosophy aimed at delivering simple but powerful
instructions that execute within a single cycle at a high clock speed.
 The RISC philosophy concentrates on reducing the complexity of instructions
performed by the hardware because it is easier to provide greater flexibility
and intelligence in software rather than hardware.
 In contrast, the traditional complex instruction set computer (CISC) relies
more on the hardware for instruction functionality, and consequently the CISC
instructions are more complicated.
 Instructions-RISC processors have a reduced number of instruction classes
that can each execute in a single cycle.

3.  Pipelines-The processing of instructions is broken down into smaller units
that can be executed in parallel by pipelines.
 Registers-RISC machines have a large general-purpose register set. Any
register can contain either data or an address.
 Load-store architecture-The processor operates on data held in registers.
Separate load and store instructions transfer data between the register bank
and external memory.
The RISC Design Philosophy

4. History
 ARM means Advanced RISC Machines.
 ARM machines have a 32-bit Reduced Instruction Set Computer (RISC) Load Store
Architecture.
 It is first RISC microprocessor for commercial use and market-leader for low power and
cost-sensitive embedded applications..
 The processor originated in England in 1984.
 At its inception ARM stood for Acorn RISC Machine.
 The first ARM reliant systems include the Acorn : BBC Micro, Masters and the Archimedes.
During this early period they were used mostly for British educational systems and therefore,
were not widely available or known outside England.
 However in 1987 the ARM became the first commercial RISC processor.
INTRODUCTION

5. History
 The ARM is a Von Neumann, load/store architecture i.e. only 32-bit data bus for both
instruction and data. Also for the load/store instruction access memory.
 Licenses ARM core designs to semiconductor partners who fabricate and sell to their
customers. ARM does not fabricate silicon itself.
 First models had only a 26-bit program counter, limiting the memory space to 64 MB.
 In 1990, the research section of Acorn separated from the parent company and
formed : Advanced RISC Machines Limited.
 The ARM is a 32-bit architecture.
 Most ARM's implement two instruction sets 1. 32-bit ARM Instruction Set 2. 16-bit
Thumb Instruction Set.
INTRODUCTION

6. Physical features that have driven the ARM processor design:
 Portable embedded systems: It require some form of battery power. -(small, low
power consumption and extend battery operation)-(applications mobile phones
and PDA)
 High code density: Embedded systems have limited memory due to cost and/or
physical size restrictions. (High code density is useful for applications that have
limited on-board memory, such as mobile phones and mass storage devices. -In
addition, embedded systems are price sensitive and use slow and low-cost
memory devices.
 Reduce the area of the die: For a single-chip solution, the smaller the area used
by the embedded processor, the more available space for specialized peripherals.
Reduces the cost of the design and manufacturing since fewer discrete chips are
required for the end product.
The ARM Design Philosophy

7.  Incorporated hardware debug technology: Incorporated within the processor so
that software engineers can view what is happening while the processor is executing
code. -With greater visibility, software engineers can resolve issues faster, which has
a direct effect on the time to market and reduces overall development costs.
THE ARM Design Philosophy

8.  Multiprocessing System
 Tightly Coupled Memory
 Memory Management
 Thumb-2 Technology
 One-Cycle Execution Time
 Pipelining
 A large number of Registers
Features of ARM Processor

9. Features of ARM Processor
 Multiprocessing Systems: ARM processors are designed to be used in cases of
multiprocessing systems where more than one processor is used to process
information. The First AMP processor introduced by the name of ARMv6K could
support 4 CPUs along with its hardware.
 Tightly Coupled Memory: The memory of ARM processors is tightly coupled.
This has a very fast response time. It has low latency (quick response) that can
also be used in cases of cache memory being unpredictable.
 Memory Management: ARM processor has a management section. This
includes Memory Management Unit and Memory Protection Unit. These
management systems become very important in managing memory efficiently.

10. Features of ARM Processor
 Thumb-2 Technology: Thumb-2 Technology was introduced in 2003 and was used
to create variable-length instruction sets. It extends the 16-bit instructions of initial
Thumb technology to 32-bit instructions. It has better performance than previously
used Thumb technology.
 One-Cycle Execution Time: ARM processor is optimized for each instruction on
the CPU. Each instruction is of a fixed length that allows time for fetching future
instructions before executing the present instructions. ARM has CPI (Clock Per
Instruction) of one cycle.
 Pipelining: Processing of instructions is done in parallel using pipelines.
Instructions are broken down and decoded in one pipeline stage. The channel
advances one step at a time to increase throughput (rate of processing).
 A large number of Registers: A large number of registers are used in ARM
processors to prevent large amounts of memory interactions. Records contain data
and addresses. These act as a local memory store for all operations.

11. Difference between ARM and x86
ARM x86
ARM uses Reduced Instruction Set
Computing Architecture (RISC).
x86 uses Complex Instruction Set
Architecture (CISC).
ARM works by executing single instruction
per cycle.
x86 works by executing complex instructions
at once and it requires more than one cycle.
Performance can be optimized by a Software-
based approach.
Performance can be optimized by Hardware
based approach.
ARM processors require fewer registers, but
they require more memory.
x86 processors require less memory, but more
registers.
Execution is faster in ARM Processes. Execution is slower in an x86 Processor.
ARM processors use the memory which is
already available to them.
x86 processors require some extra memory
for calculations.
ARM processors are deployed in mobiles
which deal with the consumption of power,
speed, and size.
x86 processors are deployed in Servers,
Laptops where performance and stability
matter.
ARM Processor work by generating multiple
instructions from a complex instruction and
they are executed separately.
x86 Processors work by executing complex
statements at a single time.

12.  ARM processors deal with a single processor at a time, which makes it faster and it also
consumes lesser power.
 ARM processors work in the case of a multiprogramming system, where more than one
processor is used to process information.
 ARM processors are cheaper than other processors, which makes them usable in mobile
phones.
 ARM processors are scalable, and this feature helps it in using a variety of devices.
Advantages of ARM Processor

13.  ARM processors are not stable with x86 processors, and due to this, they cannot be
used in Windows Systems.
 ARM processors are not capable of very high performance, which limits them to a
variety of applications.
 ARM processor execution is a little hard, which requires skilled programmers to use it.
 ARM processor is inefficient in handling scheduling instructions.
Disadvantages of ARM Processor

14. Nomenclature

15. ARM Version Comparison
ARM11- Media processing(Supports vector floating-point
unit)
ARM9- Used for JAVA enabled device as 3G phones and
PDAs
MMU – Linux operating system (ARM720)

16. ARM CORTEX
 The latest in the sequence of ARM processor are CORTEX series( v7 architecture)
1) A Series: Used for high end applications, Used to handle high end embedded OS( mobile
phones and video system)
2) R Series- Used for high end applications which require real time capabilities (ABS and Safety
critical applications)
3) M Series- For embedded microcontroller systems. Industrial control where a large peripherals
has to be handled and controlled)

17.  The ARM architecture processor is an advanced reduced instruction set
computing [RISC] machine and it's a 32 bit RISC microcontroller.
 The ARM cortex is a complicated microcontroller within the ARM family
that has ARMv7 design.
 The ARM Architecture consists of following: a) Arithmetic Logic Unit b)
Booth multiplier c) Barrel shifter d) Control unit e) Register file
 The ARM processor conjointly has other components like the Program
status register, which contains the processor flags (Z, S, V and C).
ARM ARCHITECTURE

18.  The modes bits conjointly exist within the program standing register, in addition to the
interrupt and quick interrupt disable bits; Some special registers: Some registers are
used like the instruction, memory data read and write registers and memory address
register.
ARM ARCHITECTURE

19. 1. Priority encoder : The encoder is used in the multiple load and store instruction
to point which register within the register file to be loaded or kept.
2. Multiplexers : Several multiplexers are accustomed to the management operation
of the processor buses.
3. Arithmetic Logic Unit (ALU) : The ALU has two 32-bits inputs. The primary
comes from the register file, whereas the other comes from the shifter. Status
registers flags modified by the ALU outputs. The V-bit output goes to the V flag as
well as the Count goes to the C flag. Whereas the foremost significant bit really
represents the S flag, the ALU output operation is done by NORed to get the Z flag.
The ALU has a 4-bit function bus that permits up to 16 opcode to be implemented.
ARM ARCHITECTURE

20. 4. Booth multiplier factor : The multiplier factor has 3 32-bit inputs and the
inputs return from the register file. The multiplier output is barely 32-Least
Significant Bits of the merchandise. The entity representation of the multiplier
factor is shown in the above block diagram. The multiplication starts whenever the
beginning 04 input goes active. Fin of the output goes high when finishing.
5. Barrel shifter : The barrel shifter features a 32-bit input to be shifted. This input
is coming back from the register file or it might be immediate data. The shifter has
different control inputs coming back from the instruction register. The Shift field
within the instruction controls the operation of the barrel shifter. This field
indicates the kind of shift to be performed. The quantity by which the register
thought to be shifted is contained in an immediate field within the instruction or it
might be the lower 6 bits of a register within the register file.
ARM ARCHITECTURE

21. 6. Control unit : The control unit is sometimes a pure combinational circuit
design. Here, the control unit is implemented by easy state machine. The
processor timing is additionally included within the control unit. Signals from the
control unit are connected to each component within the processor to supervise
its operation.
7. Incremented :
o For load and store instructions, the incremented updates the contents of the
address register before the processor core reads or writes the next register
value from or to the consecutive memory location.
o The processor core continues the execution of instruction. Only when an
exception or interrupt occurs, the normal execution flow is changed.
ARM ARCHITECTURE

22. 8. Address Register : This holds the address generated by the load and store
instructions and places it on the address bus.
9. Instruction decoder : It decodes the instruction opcode read from the memory
and then the instruction is executed.
10.Register file : This is a bank of 32-bit registers used for storing data items.
ARM ARCHITECTURE

23. REGISTERS
 ARM processors provide general-purpose and special-purpose registers.
 Some additional registers are available in privileged execution modes.
 In all ARM processors, the following registers are available and accessible in
any processor mode:
o 13 general-purpose registers R0-R12.
o One Stack Pointer (SP).
o One Link Register (LR).
o One Program Counter (PC).
o One Application Program Status Register (APSR).

24.  The amount of registers depends on the ARM version.
 According to the ARM Reference Manual, there are 30 general-purpose 32-
bit registers, with the exception of ARMv6-M and ARMv7-M based
processors.
 The first 16 registers are accessible in user-level mode, the additional
registers are available in privileged software execution (with the exception
of ARMv6-M and ARMv7-M).
 These 16 registers can be split into two groups: general purpose and special
purpose registers
REGISTERS

25. REGISTERS

26. REGISTERS
Processor mode
The processor mode determines which registers are active and the access rights to the cpsr
register itself.
Each processor mode is either privileged or nonprivileged:
A privileged mode =>allows full read-write access to the cpsr. (6 no.s)
A nonprivileged mode =>only allows read access to the control field in the cpsr but still
allows read-write access to the condition flags. (1 No.)
Seven processor modes: six privileged modes (abort, fast interrupt request, interrupt request,
supervisor, system, and undefined) and one nonprivileged mode (user).

27. REGISTERS
MODE OPERATION
abort mode The processor enters abort mode when there is a failed attempt to access
memory
Fast interrupt request and
interrupt request
This mode correspond to the two interrupt levels available on the ARM
processor
Supervisor This is the mode that the processor is in after reset and is generally the
mode that an operating system kernel operates in.
System This mode is a special version of user mode that allows full read-write
access to the cpsr.
Undefined When the processor encounters an instruction that is undefined or not
supported by the implementation.
User It is used for programs and applications.

28. R0-R12: can be used during common operations to store temporary values,
pointers (locations to memory), etc.
R0, for example, can be referred as accumulator during the arithmetic operations
or for storing the result of a previously called function.
R7 becomes useful while working with syscalls as it stores the syscall number and
R11 helps us to keep track of boundaries on the stack serving as the frame pointer
(will be covered later).
Moreover, the function calling convention on ARM specifies that the first four
arguments of a function are stored in the registers r0-r3.
REGISTERS

29. R13: SP (Stack Pointer).
The Stack Pointer points to the top of the stack.
The stack is an area of memory used for function-specific storage, which is
reclaimed when the function returns.
The stack pointer is therefore used for allocating space on the stack, by
subtracting the value (in bytes) we want to allocate from the stack pointer.
In other words, if we want to allocate a 32 bit value, we subtract 4 from the
stack pointer. R14: LR (Link Register).
When a function call is made, the Link Register gets updated with a memory
address referencing the next instruction where the function was initiated from.
Doing this allows the program return to the “parent” function that initiated the
“child” function call after the “child” function is finished
REGISTERS

30. R15: PC (Program Counter).
The Program Counter is automatically incremented by the size of the instruction
executed.
This size is always 4 bytes in ARM state and 2 bytes in THUMB mode.
When a branch instruction is being executed, the PC holds the destination
address.
During execution, PC stores the address of the current instruction plus 8 (two
ARM instructions) in ARM state, and the current instruction plus 4 (two Thumb
instructions) in Thumb(v1) state.
This is different from x86 where PC always points to the next instruction to be
executed.
REGISTERS

31. REGISTERS
Banked Registers
These are 20 registers hidden from a program at different times.
When the processor is in a particular mode these registers are activated; (abort mode =>r13_abt,
r14_abt and spsr_abt) (register_mode).
Every processor mode except user mode can change mode by writing directly to the mode bits of the
cpsr.
All processor modes except system mode have a set of associated banked registers that are a subset of
the main 16 registers.
If you change processor mode => a banked register from the new mode will replace an existing
register.
In the interrupt request mode, the instructions you execute still access registers named r13 and r14.
(but the banked registers r13_irq and r14_irq).( r0 to r12)
The user mode registers r13_usr and r14_usr are not affected by the instruction referencing these
registers.
The processor mode can be changed by 1) program that writes directly to the cpsr (in privileged mode)
2)by hardware when the core responds to an exception or interrupt .

32. Current Program Status Register
 The ARM core uses the cpsr to monitor and control internal operations.
 The cpsr is a dedicated 32-bit register and resides in the register file. (shaded parts are reserved
for future expansion)
 The cpsr is divided into four fields, each 8 bits wide: flags, status, extension, and control.
 In current designs the extension and status fields are reserved for future use.
 The control field contains the processor mode, state, and interrupt mask bits.
 The flags field contains the condition flags.
 Some ARM processor cores have extra bits allocated. For example, the J bit, which can be
found in the flags field, is only available on Jazelle-enabled processors, which execute 8-bit
instructions.

33. Pipeline
 Using a pipeline speeds up execution by fetching the next instruction while other
instructions are being decoded and executed.
ARM7 Three-stage pipeline