FPL 2018: A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs
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1) The document discusses aggressive voltage underscaling or undervolting of FPGAs to achieve energy efficiency through reduced power consumption but with the overhead of potential timing faults that impact reliability. 2) It focuses on undervolting the block RAMs (BRAMs) of Xilinx FPGAs and analyzes the power/reliability tradeoffs when reducing voltages below the nominal guardband levels. 3) The experiments found a 10x reduction in power consumption is possible by undervolting BRAMs but fault rates increase exponentially as voltages go below the guardband, and there is a system crash point where the FPGA stops operating.
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FPL 2018: Fault Characterization Through FPGAs Undervolting
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Similar to FPL 2018: A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs
IOLTS 2019: Agressive Undervolting of FPGAs: Power and Reliability Trade-offs
In this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip vendors to ensure the worst-case process and environmental scenarios. Through experimenting on several FPGA architectures, we con¿rm a large voltage guardband for several FPGA components, which in turn, delivers signi¿cant power savings. However, further undervolting below the voltage guardband may cause reliability issues as the result of the circuit delay increase, and faults might start to appear. We extensively characterize the behavior of these faults in terms of the rate, location, type, as well as sensitivity to environmental temperature, primarily focusing on FPGA on-chip memories, or Block RAMs (BRAMs). Understanding this behavior can allow to deploy ef¿cient mitigation techniques, and in turn, FPGA-based designs can be improved for better energy, reliability, and performance trade-offs. Finally, as a case study, we evaluate a typical FPGA-based Neural Network (NN) accelerator when the FPGA voltage is underscaled. In consequence, the substantial NN energy savings come with the cost of NN accuracy loss. To attain power savings without NN accuracy loss below the voltage guardband gap, we proposed an application-aware technique and we also, evaluated the built-in Error-Correcting Code (ECC) mechanism. Hence, First, we developed an application-dependent BRAMs placement technique that relies on the deterministic behavior of undervolting faults, and mitigates these faults by mapping the most reliability sensitive NN parameters to BRAM blocks that are relatively more resistant to undervolting faults. Second, as a more general technique, we applied the built-in ECC of BRAMs and observed a signi¿cant fault coverage capability thanks to the behavior of undervolting faults, with a negligible power consumption overhead.
Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Underv...
This document evaluates the built-in error correction code (ECC) of FPGA on-chip memories for mitigating faults caused by aggressive undervolting. Experimental results on multiple FPGA platforms show that undervolting below the minimum safe voltage introduces mostly single-bit faults in BRAMs. The built-in ECC is over 90% effective in correcting faults and prevents significant accuracy loss in a neural network implementation when voltages drop below safe levels. While ECC adds minimal area and power overhead, it effectively allows further energy savings from aggressive undervolting of FPGA memories.
FPGA Undervolting and Checkpointing for Energy-Efficiency and Error-Resiliency
Tutorial by Behzad Salami, Osman Unsal and Leonardo Bautista at 30th International Conference on Field-Programmable Logic and Applications (FPL2020), 3 September 2020
Comprehensive evaluation of supply voltage underscaling in FPGA on chip memories
1) The document discusses aggressive undervolting of FPGAs to improve power efficiency while characterizing its impact on reliability.
2) Experiments were conducted on multiple FPGA platforms to determine safe, critical, and crash voltage ranges and characterize faults in on-chip memories.
3) A neural network implementation on FPGA showed significant power reduction from undervolting until the minimum safe voltage, but the network accuracy exponentially decreased beyond this point due to faults. Fault mitigation techniques were proposed to prevent accuracy loss.
ISCA2021 Tutorial-Methods for Characterization and Analysis of Voltage Margin...
The tutorial is given in ISCA2021: http://isca48.tutorial.di.uoa.gr/
Slides include only the FPGA part.
FPGAVolt: Low-power FPGA-based DNN Accelerator through Aggressive Undervolting
FPGAVolt exploits the aggressive supply voltage underscaling technique to improve the energy efficiency of FPGA-based NNs. Additionally, FPGAVolt also evaluates and improves the resilience of this accelerator. Through experiments on several representative FPGA fabrics, we observe that until a minimum safe voltage level, i.e., Vmin the NN accuracy is not affected. This safe region involves a large voltage guardband. Also, it involves a narrower voltage region where faults start to appear due to the increased circuit delay, but these faults are masked by NN, and thus, its accuracy is not affected. However, further undervolting causes significant
accuracy loss as a result of the exponentially-increasing high fault rates. Based on the characterization of these undervolting faults, we propose fault mitigation techniques that can effectively improve the resilience behavior of such accelerator. FPGAVolt is implemented on several FPGA platforms and on average, achieves >90% energy saving with a negligible accuracy loss of up to 0.1%.
Surge Protect, a critical issue you could not fail to know while implementing...
How high should we aim? Sparkovers (flashovers) which occur almost naturally in building wiring systems protect most equipment locations for surges above 6kV. So 6kV is the upper limit we should be concerned about. Note that poor or mediocre wiring insulation materials ironically help protect equipment better than excellent and expensive insulator materials.
There is increasing talk about “6kV surge protection”. We now realize why 6kV is being picked. However, we should keep in mind that so far such requirements are voluntary. But even if they do become mandatory, note that there are already designated “levels” of surge withstand capability: 2.5kV, 4kV, and 6kV, similar to CISPR 24. So it is probable that much like with CISPR 24/EN55024 we may only need to comply with a level lesser than max.
Selective Coordination "The Rest of the Story"
This document provides an overview of selective coordination and discusses key considerations for designing selectively coordinated electrical distribution systems. It defines selective coordination and different types of faults. It describes how ground fault protection, motor circuit protection, and circuit breaker components can impact coordination. The document emphasizes that coordination is dependent on system design and stresses minimizing protective device levels. It also notes that arc flash energy is influenced by fault current magnitude and protective device opening time.
Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAs
This document analyzes and compares different power gating techniques to reduce leakage current and ground bounce noise in FPGAs. It discusses stacking power gating, diode-based stacking power gating, and diode-based staggered phase damping techniques applied to a benchmark 74182 carry look ahead adder circuit implemented as a lookup table (LUT) in FPGAs. Simulation results show that the diode-based staggered phase damping technique provides up to 99% reduction in ground bounce noise and 75% reduction in leakage current. Performance analysis of the LUT implemented on different FPGAs also shows the diode-based staggered phase damping technique to be most effective at reducing leakage current and ground bounce noise.
H0144757
This document analyzes and compares different power gating techniques to reduce leakage current and ground bounce noise in FPGAs. It discusses stacking power gating, diode-based stacking power gating, and diode-based staggered phase damping techniques applied to a benchmark 74182 carry look ahead adder circuit implemented as a lookup table (LUT) in FPGAs. Simulation results show that the diode-based staggered phase damping technique provides up to 99% reduction in ground bounce noise and 75% reduction in leakage current. Performance analysis of the LUT implemented on different FPGAs also shows the diode-based staggered phase damping technique to be most effective at reducing leakage current and ground bounce noise.
Implementing AI: Hardware Challenges: Heterogeneous and Adaptive Computing fo...
Exploring strategies to deploy and adapt custom hardware such as Google Tensor Processing Units and Xilinx Deep-learning Processing Units to obtain high-performance and energy-efficient AI.
The Implementing AI: Hardware Challenges, hosted by KTN and eFutures, is the first event of the Implementing AI webinar series to address the challenges and opportunities that realising AI for hardware present.
There will be presentations from hardware organisations and from solution providers in the morning; followed by Q&A. The afternoon session will consist of virtual breakout rooms, where challenges raised in the morning session can be workshopped.
Artificial Intelligence now impacts every aspect of modern life and is key to the generation of valuable business insights.
Implementing AI webinar series is designed for people involved in the management and implementation of AI based solutions – from developers to CTOs.
Find out more: https://ktn-uk.co.uk/news/just-launched-implementing-ai-webinar-series
Understanding the Reliability and Power-Efficiency Trade-offs of Modern FPGAs...
SAFARI Live Seminar, 31st MAY, By: Behzad Salami
In this presentation, we will comprehensively cover our findings on the undervolting of multiple components of FPGAs, i.e., SRAM-based on-chip memories (BRAMs), Look-Up Tables (LUTs), and DRAM-based High-Bandwidth Memories (HBMs). The talk will conclude with a discussion of open problems and possible directions for future research.
Link: https://safari.ethz.ch/safari-live-seminar-behzad-salami-31-may-2022/
Nowka low-power-07
The document discusses techniques for reducing power consumption in VLSI circuits. It provides an overview of power consumption components in CMOS circuits and how power scales with technology. It also discusses trends in frequency scaling and supply voltage scaling. Various active power reduction techniques are presented, including capacitance minimization, clock gating, voltage scaling, frequency scaling, and minimizing shoot-through current.
Hx3313651367
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Embedded Systems Power Management
A review of basic concepts on power consumptions on VLSI architectures and techniques to reduce energy wastage both at architectural and system level
[IJET-V1I3P5] Authors :Dushyant Kumar Soni, Ashish Hiradhar
[IJET-V1I3P5] Authors :Dushyant Kumar Soni, Ashish HiradharIJET - International Journal of Engineering and Techniques
Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits.
One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This paper
we will present a comparative analysis of existing clock gating techniques on some synchronous digital design
like ALU (Arithmetic logical unit) etc. Also a new clock gating technique that provides more immunity to the
existing problem in available technique. In new proposed clock gating the Gated Clock Generation Circuit is using
tri state buffer and Gated logic is used which is created by the combination of double gated (AND, OR, AND
logic gate) with bubbled input respectively. This circuit saves power even when Target device's clock is ON. All
experiments are done on Xilinx14.1 EDA tool. Mentor Graphics Model SIM. For power calculation we are using
XPOWER. Sparten-3 (90nm) FPGA platform is used for result and analysis. The proposed design will reduce the
hardware complexity with approximately 10-20%. Similar clock power complexity will reduce with 5-10%.
Keywords — Tri state buffer; VLSI; Xilinx; glitches; hazards;Sparten.RT15 Berkeley | Power HIL Simulator (SimP) A prototype to develop a high band...
RT15 Berkeley | Power HIL Simulator (SimP) A prototype to develop a high band...OPAL-RT TECHNOLOGIES
This document discusses the development of a prototype high bandwidth power interface called a Power Simulator (SimP). The prototype aims to validate control algorithms and develop a stable interface between a power amplifier and real-time power system simulator. Key aspects of the prototype include a self-powered multi-level converter prototype, controller design, and interfacing the converter with a real-time simulator to test equipment performance and simulation models in a closed loop. The prototype will help inform the design of a full-scale Power Simulator for testing smart grid and renewable energy technologies.DETECTING POWER GRID SYNCHRONISATION FAILURE ON SENSING BAD VOLTAGE OR FREQUENCY
This paper presents the development of a microcontroller based islanding detection for grid connected inverter with very simple under/over voltage and under/over frequency islanding detection algorithms.
The microcontroller monitors the under/over voltage and under/over frequency from utility grid and the processed value of voltage and frequency for turning ON/OFF the relay between a grid connected inverter and the utility grid.
The project would alternatively use a variable frequency generator using 555timer for changing the frequency while a standard variac shall be used to vary the input voltage for achieving the test conditions as stated above.
Bc36330333
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
G.r.s. 02 04-01-12
1. Betagard 5SX4 miniature circuit breakers (MCBs) have rated breaking capacities up to 10kA and comply with national and international standards with current ratings from 0.5A to 63A.
2. 5SX4 MCBs significantly limit let-through current during faults, providing high protection. They have "C" and "D" tripping characteristics and an average service life of 20,000 operations.
3. 5SX4 MCBs provide selectivity (preventing unnecessary tripping of upstream devices) when used with fuses or other MCBs according to limits specified in the document.
Similar to FPL 2018: A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs (20)
IOLTS 2019: Agressive Undervolting of FPGAs: Power and Reliability Trade-offs
IOLTS 2019: Agressive Undervolting of FPGAs: Power and Reliability Trade-offs
Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Underv...
Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Underv...
FPGA Undervolting and Checkpointing for Energy-Efficiency and Error-Resiliency
FPGA Undervolting and Checkpointing for Energy-Efficiency and Error-Resiliency
Comprehensive evaluation of supply voltage underscaling in FPGA on chip memories
Comprehensive evaluation of supply voltage underscaling in FPGA on chip memories
ISCA2021 Tutorial-Methods for Characterization and Analysis of Voltage Margin...
ISCA2021 Tutorial-Methods for Characterization and Analysis of Voltage Margin...
FPGAVolt: Low-power FPGA-based DNN Accelerator through Aggressive Undervolting
FPGAVolt: Low-power FPGA-based DNN Accelerator through Aggressive Undervolting
Surge Protect, a critical issue you could not fail to know while implementing...
Surge Protect, a critical issue you could not fail to know while implementing...
Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAs
Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAs
Implementing AI: Hardware Challenges: Heterogeneous and Adaptive Computing fo...
Implementing AI: Hardware Challenges: Heterogeneous and Adaptive Computing fo...
Understanding the Reliability and Power-Efficiency Trade-offs of Modern FPGAs...
Understanding the Reliability and Power-Efficiency Trade-offs of Modern FPGAs...
[IJET-V1I3P5] Authors :Dushyant Kumar Soni, Ashish Hiradhar
[IJET-V1I3P5] Authors :Dushyant Kumar Soni, Ashish Hiradhar
RT15 Berkeley | Power HIL Simulator (SimP) A prototype to develop a high band...
RT15 Berkeley | Power HIL Simulator (SimP) A prototype to develop a high band...
DETECTING POWER GRID SYNCHRONISATION FAILURE ON SENSING BAD VOLTAGE OR FREQUENCY
DETECTING POWER GRID SYNCHRONISATION FAILURE ON SENSING BAD VOLTAGE OR FREQUENCY
More from LEGATO project
Scrooge Attack: Undervolting ARM Processors for Profit
Malicious cloud provider can intentionally undervolt cloud infrastructure for additional savings on the electricity bill. ARM processors are low power processors which can lead to substantial energy saving for cloud providers. In our scenario we consider a scrooge cloud provider which undervolts its ARM
infrastructure for profit. The instances can be undervolted in a stealthy manner by avoiding critical voltage regions.
Applications running under critical undervolting conditions can
malfunction. These conditions can be exploited by a cloud user to uncover the undervolted instances. For this novel attack scenario we present a detection method for cloud users. The detection method injects non-selectively faults into processes with the intend to crash the cloud instance. Even if the cloud
provider can spoof temperature and voltage readings of the processor, the cloud user is capable to uncover undervolted instances. By crashing instances simultaneously using the detection method, the cloud user is covered by the service licence agreement and exposes the scrooge cloud provider.
A practical approach for updating an integrity-enforced operating system
The document describes an approach for securely updating software on an integrity-enforced operating system. It involves a trusted software repository (TSR) that sanitizes software packages before they are installed. The sanitization process modifies installation scripts and predicts OS configuration changes. The TSR also digitally signs packages. When a package is installed, its signature and files are measured and verified by the integrity monitoring system to ensure the update does not violate integrity.
TEEMon: A continuous performance monitoring framework for TEEs
LEGaTO paper presented at ACM Middleware 2020 by Robert Krahn, Donald Dragoti, Franz Gregor, Do Le Quoc, Valerio Schiavoni, Pascal Felber, Clenimar Souza, Andrey Brito and Christof Fetzer
secureTF: A Secure TensorFlow Framework
LEGaTO paper presented at Middleware 2020 by Do Le Quoc, Franz Gregor, Sergei Arnautov, Roland Kunkeland, Pramod Bhatotia and Christof Fetzer
PipeTune: Pipeline Parallelism of Hyper and System Parameters Tuning for Deep...
LEGaTO presentation at ACM Middleware 2020, by Isabelly Rocha, Nathaniel Morris, Lydia Y. Chen, Pascal Felber, Robert Birke and Valerio Schiavoni
LEGaTO: Machine Learning Use Case
Presentation by Hans Salomonsson at the webinar AI4EU WebCafé: 'Energy-efficient AI, a perspective from the LEGaTO project' on 28 October 2020
Smart Home AI at the edge
Presentation by Nils Kucza at the webinar AI4EU WebCafé: 'Energy-efficient AI, a perspective from the LEGaTO project' on 28 October 2020
LEGaTO: Low-Energy Heterogeneous Computing Use of AI in the project
Presentation by Osman Unsal and Pirah Noor Soomro at the webinar AI4EU WebCafé: 'Energy-efficient AI, a perspective from the LEGaTO project' on 28 October 2020
LEGaTO Integration
Presentation given by Xavier Martorell at the ‘Low-Energy Heterogeneous Computing Workshop’ on 16 October 2020 within HiPEAC CSW Autumn 2020
LEGaTO: Use cases
Presentation given by Micha vor dem Berge at the ‘Low-Energy Heterogeneous Computing Workshop’ on 16 October 2020 within HiPEAC CSW Autumn 2020
LEGaTO: Software Stack Programming Models
Presentation given by Pascal Felber at the ‘Low-Energy Heterogeneous Computing Workshop’ on 16 October 2020 within HiPEAC CSW Autumn 2020
LEGaTO: Software Stack Runtimes
Presentation given by Mustafa Abduljabbar at the ‘Low-Energy Heterogeneous Computing Workshop’ on 16 October 2020 within HiPEAC CSW Autumn 2020
LEGaTO Heterogeneous Hardware
The LEGaTO project received funding from the EU's Horizon 2020 program to develop a heterogeneous hardware platform called RECS for cloud to edge computing. RECS uses a modular microserver approach integrating CPUs, GPUs, FPGAs, and SOCs. It allows for flexible node composition through virtual functions to enable different compute and communication topologies.
LEGaTO: Low-Energy Heterogeneous Computing Workshop
Presentation given by Osman Unsal at the ‘Low-Energy Heterogeneous Computing Workshop’ on 16 October 2020 within HiPEAC CSW Autumn 2020
TZ4Fabric: Executing Smart Contracts with ARM TrustZone
Paper presented by Christian Göttel at SRDS'20.
Abstract: Transparency in blockchains can be an advantage and a disadvantage, in particular if confidential information such as assets or business interactions are exposed. There are no confidentiality guarantees in blockchain systems to protect the logic of a smart contract or the data it processes. One solution to this problem can be trusted execution environments (TEE) which are an emerging technology for example available in edge or mobile-grade processors (e.g., ARM TrustZone) or in server-grade processors (e.g., Intel SGX). In this presentation we introduce TZ4Fabric, an extension of Hyperledger Fabric which leverages ARM TrustZone to shield the execution of smart contracts from compromised systems and powerful attackers. TZ4Fabric exploits the open source OP-TEE framework to enable ARM TrustZone features. We evaluate our prototype on the Raspberry Pi platform and highlight energy and performance trade-offs.
Infection Research with Maxeler Dataflow Computing
Presentation given by Tobias Becker (Maxeler) at the LEGaTO Final Event: Low-Energy Heterogeneous Computing Workshop on 4 September 2020
This event was collocated with FPL 2020
Smart Home - AI at the edge
Presentation given by Nils Kucza (Bielefeld University) at the LEGaTO Final Event: Low-Energy Heterogeneous Computing Workshop on 4 September 2020
This event was collocated with FPL 2020
Device Data Directory and Asynchronous execution: A path to heterogeneous com...
Poster presented by Rubén Cano at the LEGaTO Final Event: 'Low-Energy Heterogeneous Computing Workshop'
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments
Presentation by Jing Chen and Pirah Noor Soomro (Chalmers University of Technology) at the 16th International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS 2020) on 17 August 2020.
SRMPDS was a virtual event and collocated with ICPP’20 - 2020 International Conference on Parallel Processing.
RECS – Cloud to Edge Microserver Platform for Energy-Efficient Computing
Abstract:Today, application developers and data center operators face the challenging task to achieve high performance while at the same time needing to reduce the total cost of ownership, which is especially driven by the energy consumption of the server itself.
This poster shows the RECS Microserver platform, developed by Christmann and Bielefeld University. RECS simplifies the combined use of heterogeneous target architectures to achieve high performance and superior energy-efficiency.
Poster presented by Martin Kaiser at the LEGaTO Final Event: 'Low-Energy Heterogeneous Computing Workshop'
More from LEGATO project (20)
Scrooge Attack: Undervolting ARM Processors for Profit
Scrooge Attack: Undervolting ARM Processors for Profit
A practical approach for updating an integrity-enforced operating system
A practical approach for updating an integrity-enforced operating system
TEEMon: A continuous performance monitoring framework for TEEs
TEEMon: A continuous performance monitoring framework for TEEs
PipeTune: Pipeline Parallelism of Hyper and System Parameters Tuning for Deep...
PipeTune: Pipeline Parallelism of Hyper and System Parameters Tuning for Deep...
LEGaTO: Low-Energy Heterogeneous Computing Use of AI in the project
LEGaTO: Low-Energy Heterogeneous Computing Use of AI in the project
LEGaTO: Low-Energy Heterogeneous Computing Workshop
LEGaTO: Low-Energy Heterogeneous Computing Workshop
TZ4Fabric: Executing Smart Contracts with ARM TrustZone
TZ4Fabric: Executing Smart Contracts with ARM TrustZone
Infection Research with Maxeler Dataflow Computing
Infection Research with Maxeler Dataflow Computing
Device Data Directory and Asynchronous execution: A path to heterogeneous com...
Device Data Directory and Asynchronous execution: A path to heterogeneous com...
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments
RECS – Cloud to Edge Microserver Platform for Energy-Efficient Computing
RECS – Cloud to Edge Microserver Platform for Energy-Efficient Computing
Recently uploaded
The debris of the ‘last major merger’ is dynamically young
The Milky Way’s (MW) inner stellar halo contains an [Fe/H]-rich component with highly eccentric orbits, often referred to as the
‘last major merger.’ Hypotheses for the origin of this component include Gaia-Sausage/Enceladus (GSE), where the progenitor
collided with the MW proto-disc 8–11 Gyr ago, and the Virgo Radial Merger (VRM), where the progenitor collided with the
MW disc within the last 3 Gyr. These two scenarios make different predictions about observable structure in local phase space,
because the morphology of debris depends on how long it has had to phase mix. The recently identified phase-space folds in Gaia
DR3 have positive caustic velocities, making them fundamentally different than the phase-mixed chevrons found in simulations
at late times. Roughly 20 per cent of the stars in the prograde local stellar halo are associated with the observed caustics. Based
on a simple phase-mixing model, the observed number of caustics are consistent with a merger that occurred 1–2 Gyr ago.
We also compare the observed phase-space distribution to FIRE-2 Latte simulations of GSE-like mergers, using a quantitative
measurement of phase mixing (2D causticality). The observed local phase-space distribution best matches the simulated data
1–2 Gyr after collision, and certainly not later than 3 Gyr. This is further evidence that the progenitor of the ‘last major merger’
did not collide with the MW proto-disc at early times, as is thought for the GSE, but instead collided with the MW disc within
the last few Gyr, consistent with the body of work surrounding the VRM.
The use of Nauplii and metanauplii artemia in aquaculture (brine shrimp).pptx
Although Artemia has been known to man for centuries, its use as a food for the culture of larval organisms apparently began only in the 1930s, when several investigators found that it made an excellent food for newly hatched fish larvae (Litvinenko et al., 2023). As aquaculture developed in the 1960s and ‘70s, the use of Artemia also became more widespread, due both to its convenience and to its nutritional value for larval organisms (Arenas-Pardo et al., 2024). The fact that Artemia dormant cysts can be stored for long periods in cans, and then used as an off-the-shelf food requiring only 24 h of incubation makes them the most convenient, least labor-intensive, live food available for aquaculture (Sorgeloos & Roubach, 2021). The nutritional value of Artemia, especially for marine organisms, is not constant, but varies both geographically and temporally. During the last decade, however, both the causes of Artemia nutritional variability and methods to improve poorquality Artemia have been identified (Loufi et al., 2024).
Brine shrimp (Artemia spp.) are used in marine aquaculture worldwide. Annually, more than 2,000 metric tons of dry cysts are used for cultivation of fish, crustacean, and shellfish larva. Brine shrimp are important to aquaculture because newly hatched brine shrimp nauplii (larvae) provide a food source for many fish fry (Mozanzadeh et al., 2021). Culture and harvesting of brine shrimp eggs represents another aspect of the aquaculture industry. Nauplii and metanauplii of Artemia, commonly known as brine shrimp, play a crucial role in aquaculture due to their nutritional value and suitability as live feed for many aquatic species, particularly in larval stages (Sorgeloos & Roubach, 2021).
Randomised Optimisation Algorithms in DAPHNE
Slides from talk:
Aleš Zamuda: Randomised Optimisation Algorithms in DAPHNE .
Austrian-Slovenian HPC Meeting 2024 – ASHPC24, Seeblickhotel Grundlsee in Austria, 10–13 June 2024
https://ashpc.eu/
20240520 Planning a Circuit Simulator in JavaScript.pptx
Evaporation step counter work. I have done a physical experiment.
(Work in progress.)
ESR spectroscopy in liquid food and beverages.pptx
With increasing population, people need to rely on packaged food stuffs. Packaging of food materials requires the preservation of food. There are various methods for the treatment of food to preserve them and irradiation treatment of food is one of them. It is the most common and the most harmless method for the food preservation as it does not alter the necessary micronutrients of food materials. Although irradiated food doesn’t cause any harm to the human health but still the quality assessment of food is required to provide consumers with necessary information about the food. ESR spectroscopy is the most sophisticated way to investigate the quality of the food and the free radicals induced during the processing of the food. ESR spin trapping technique is useful for the detection of highly unstable radicals in the food. The antioxidant capability of liquid food and beverages in mainly performed by spin trapping technique.
3D Hybrid PIC simulation of the plasma expansion (ISSS-14)
3D Particle-In-Cell (PIC) algorithm,
Plasma expansion in the dipole magnetic field.
Unlocking the mysteries of reproduction: Exploring fecundity and gonadosomati...
The pygmy halfbeak Dermogenys colletei, is known for its viviparous nature, this presents an intriguing case of relatively low fecundity, raising questions about potential compensatory reproductive strategies employed by this species. Our study delves into the examination of fecundity and the Gonadosomatic Index (GSI) in the Pygmy Halfbeak, D. colletei (Meisner, 2001), an intriguing viviparous fish indigenous to Sarawak, Borneo. We hypothesize that the Pygmy halfbeak, D. colletei, may exhibit unique reproductive adaptations to offset its low fecundity, thus enhancing its survival and fitness. To address this, we conducted a comprehensive study utilizing 28 mature female specimens of D. colletei, carefully measuring fecundity and GSI to shed light on the reproductive adaptations of this species. Our findings reveal that D. colletei indeed exhibits low fecundity, with a mean of 16.76 ± 2.01, and a mean GSI of 12.83 ± 1.27, providing crucial insights into the reproductive mechanisms at play in this species. These results underscore the existence of unique reproductive strategies in D. colletei, enabling its adaptation and persistence in Borneo's diverse aquatic ecosystems, and call for further ecological research to elucidate these mechanisms. This study lends to a better understanding of viviparous fish in Borneo and contributes to the broader field of aquatic ecology, enhancing our knowledge of species adaptations to unique ecological challenges.
EWOCS-I: The catalog of X-ray sources in Westerlund 1 from the Extended Weste...
Context. With a mass exceeding several 104 M⊙ and a rich and dense population of massive stars, supermassive young star clusters
represent the most massive star-forming environment that is dominated by the feedback from massive stars and gravitational interactions
among stars.
Aims. In this paper we present the Extended Westerlund 1 and 2 Open Clusters Survey (EWOCS) project, which aims to investigate
the influence of the starburst environment on the formation of stars and planets, and on the evolution of both low and high mass stars.
The primary targets of this project are Westerlund 1 and 2, the closest supermassive star clusters to the Sun.
Methods. The project is based primarily on recent observations conducted with the Chandra and JWST observatories. Specifically,
the Chandra survey of Westerlund 1 consists of 36 new ACIS-I observations, nearly co-pointed, for a total exposure time of 1 Msec.
Additionally, we included 8 archival Chandra/ACIS-S observations. This paper presents the resulting catalog of X-ray sources within
and around Westerlund 1. Sources were detected by combining various existing methods, and photon extraction and source validation
were carried out using the ACIS-Extract software.
Results. The EWOCS X-ray catalog comprises 5963 validated sources out of the 9420 initially provided to ACIS-Extract, reaching a
photon flux threshold of approximately 2 × 10−8 photons cm−2
s
−1
. The X-ray sources exhibit a highly concentrated spatial distribution,
with 1075 sources located within the central 1 arcmin. We have successfully detected X-ray emissions from 126 out of the 166 known
massive stars of the cluster, and we have collected over 71 000 photons from the magnetar CXO J164710.20-455217.
Equivariant neural networks and representation theory
Or: Beyond linear.
Abstract: Equivariant neural networks are neural networks that incorporate symmetries. The nonlinear activation functions in these networks result in interesting nonlinear equivariant maps between simple representations, and motivate the key player of this talk: piecewise linear representation theory.
Disclaimer: No one is perfect, so please mind that there might be mistakes and typos.
dtubbenhauer@gmail.com
Corrected slides: dtubbenhauer.com/talks.html
Compexometric titration/Chelatorphy titration/chelating titration
Classification
Metal ion ion indicators
Masking and demasking reagents
Estimation of Magnisium sulphate
Calcium gluconate
Complexometric Titration/ chelatometry titration/chelating titration, introduction, Types-
1.Direct Titration
2.Back Titration
3.Replacement Titration
4.Indirect Titration
Masking agent, Demasking agents
formation of complex
comparition between masking and demasking agents,
Indicators/Metal ion indicators/ Metallochromic indicators/pM indicators,
Visual Technique,PM indicators (metallochromic), Indicators of pH, Redox Indicators
Instrumental Techniques-Photometry
Potentiometry
Miscellaneous methods.
Complex titration with EDTA.
The binding of cosmological structures by massless topological defects
Assuming spherical symmetry and weak field, it is shown that if one solves the Poisson equation or the Einstein field
equations sourced by a topological defect, i.e. a singularity of a very specific form, the result is a localized gravitational
field capable of driving flat rotation (i.e. Keplerian circular orbits at a constant speed for all radii) of test masses on a thin
spherical shell without any underlying mass. Moreover, a large-scale structure which exploits this solution by assembling
concentrically a number of such topological defects can establish a flat stellar or galactic rotation curve, and can also deflect
light in the same manner as an equipotential (isothermal) sphere. Thus, the need for dark matter or modified gravity theory is
mitigated, at least in part.
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