Chapter 5:
Field-Effect Transistors
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
INTRODUCTION
• The field-effect transistor (FET) is a three-terminal
device.
• For the FET an electric field is established by the
charges present that will control the conduction
path of the output
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits
Differences:
• FETs are voltage controlled devices. BJTs are current controlled
devices.
• FETs have a higher input impedance. BJTs have higher gains.
• FETs are less sensitive to temperature variations and are more
easily integrated on ICs.
• FETs are generally more static sensitive than BJTs.
FETs vs. BJTs
3
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
•JFET: Junction FET
•MOSFET: Metal–Oxide–Semiconductor FET
D-MOSFET: Depletion MOSFET
E-MOSFET: Enhancement MOSFET
FET Types
4
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
JFET Construction
There are two types of JFETs
•n-channel
•p-channel
The n-channel is more widely used.
There are three terminals:
•Drain (D) and Source (S) are connected to the n-channel
•Gate (G) is connected to the p-type material
5
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
JFET Operation: The Basic Idea
JFET operation can be compared to a water spigot.
The source of water pressure is the
accumulation of electrons at the
negative pole of the drain-source
voltage.
The drain of water is the electron
deficiency (or holes) at the positive pole
of the applied voltage.
The control of flow of water is the gate
voltage that controls the width of the n-
channel and, therefore, the flow of
charges from source to drain.
6
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
JFET Operating Characteristics
There are three basic operating conditions for a JFET:
• VGS = 0, VDS increasing to some positive value
• VGS < 0, VDS at some positive value
• Voltage-controlled resistor
7
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
JFET Operating Characteristics: VGS = 0 V
• The depletion region between p-gate
and n-channel increases as electrons
from n-channel combine with holes
from p-gate.
• Increasing the depletion region,
decreases the size of the n-channel
which increases the resistance of the
n-channel.
• Even though the n-channel resistance
is increasing, the current (ID) from
source to drain through the n-
channel is increasing. This is because
VDS is increasing.
Three things happen when VGS = 0 and VDS is increased from 0 to a more positive
voltage
8
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
• Assuming a uniform resistance in the
n-channel, the resistance of the channel
can be broken down to the divisions.
• The result is that the upper region of
the p-type material will be reverse
biased by about 1.5 V, with the lower
region only reverse-biased by 0.5 V.
• The greater the applied reverse bias,
the wider the depletion region.
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
If VGS = 0 and VDS is further increased to
a more positive voltage, then the
depletion zone gets so large that it
pinches off the n-channel.
This suggests that the current in the n-
channel (ID) would drop to 0A, but it does
just the opposite–as VDS increases, so does
ID.
JFET Operating Characteristics: Pinch Off
10
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
At the pinch-off point:
• Any further increase in VDS does not
produce any increase in ID. VDS at
pinch-off is denoted as Vp.
• ID is at saturation or maximum. It is
referred to as IDSS.
• The ohmic value of the channel is
maximum.
JFET Operating Characteristics: Saturation
11
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
JFET Operating Characteristics
As VGS becomes more negative,
the depletion region increases.
12
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
As VGS becomes more negative:
• The JFET experiences
pinch-off at a lower voltage
(VP).
• ID decreases (ID < IDSS) even
though VDS is increased.
• Eventually ID reaches 0 A.
VGS at this point is called Vp
or VGS(off)..
JFET Operating Characteristics
Also note that at high levels of VDS the JFET reaches a breakdown situation. ID
increases uncontrollably if VDS > VDSmax.
13
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
2
P
GS
o
d
V
V
1
r
r










The region to the left of the
pinch-off point is called the
ohmic region.
The JFET can be used as a
variable resistor, where VGS
controls the drain-source
resistance (rd). As VGS becomes
more negative, the resistance
(rd) increases.
JFET Operating Characteristics:
Voltage-Controlled Resistor
14
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
p-Channel JFETS
The p-channel JFET behaves the
same as the n-channel JFET,
except the voltage polarities and
current directions are reversed.
15
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
p-Channel JFET Characteristics
Also note that at high levels of VDS the JFET reaches a breakdown situation: ID
increases uncontrollably if VDS > VDSmax.
As VGS increases more positively
• The depletion zone
increases
• ID decreases (ID < IDSS)
• Eventually ID = 0 A
16
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
N-Channel JFET Symbol
17
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
P-Channel JFET Symbol
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
The transfer characteristic of input-to-output is not as straightforward in
a JFET as it is in a BJT.
In a BJT,  indicates the relationship between IB (input) and IC (output).
In a JFET, the relationship of VGS (input) and ID (output) is a little more
complicated:
JFET Transfer Characteristics
19
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
JFET Transfer Curve
This graph shows the value of ID for a given value of VGS.
20
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Using IDSS and Vp (VGS(off)) values found in a specification sheet, the transfer
curve can be plotted according to these three steps:
Solving for VGS = 0V ID = IDSS
2
P
GS
DSS
D
V
V
1
I
I 









Step 1
Plotting the JFET Transfer Curve
21
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Solving for VGS = Vp (VGS(off)) ID = 0A
2
P
GS
DSS
D
V
V
1
I
I 









Step 2
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Solving for VGS = 0V to Vp
2
P
GS
DSS
D
V
V
1
I
I 









Step 3
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Sketch the transfer curve defined by IDSS = 12 mA and VP = 6 V.
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
MOSFETs
There are two types of MOSFETs:
• Depletion-Type
• Enhancement-Type
MOSFETs have characteristics similar to JFETs and additional
characteristics that make them very useful.
25
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Depletion-Type MOSFET Construction
The Drain (D) and Source (S) connect
to the to n-doped regions. These n-
doped regions are connected via an n-
channel. This n-channel is connected to
the Gate (G) via a thin insulating layer
of SiO2 silicon dioxide.
The n-doped material lies on a p-doped
substrate that may have an additional
terminal connection called Substrate
(SS).
26
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
The gate-to-source voltage is set to zero
volts by the direct connection from one
terminal to the other, and a voltage VDS
is applied across the drain-to-source
terminals.
The result is an attraction for the
positive potential at the drain by the
free electrons of the n-channel and a
current similar to that established
through the channel of the JFET.
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Basic MOSFET Operation
A depletion-type MOSFET can operate in two modes:
• Depletion mode
• Enhancement mode
28
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
D-Type MOSFET in Depletion Mode
• When VGS = 0 V, ID = IDSS
• When VGS < 0 V, ID < IDSS
• The formula used to plot the transfer
curve still applies:
Depletion Mode
The characteristics are similar
to a JFET.
2
P
GS
DSS
D
V
V
1
I
I 









29
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
D-Type MOSFET in Enhancement Mode
• VGS > 0 V
• ID increases above IDSS
• The formula used to plot
the transfer curve still
applies:
2
P
GS
DSS
D
V
V
1
I
I 









Enhancement Mode
Note that VGS is now a positive polarity
30
the application of a positive gate-to-source voltage has “enhanced” the level of free carriers in the channel compared to that
encountered with VGS = 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics
is often referred to as the enhancement region, with the region between cutoff and the saturation level of IDSS referred to as the
depletion region.
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Sketch the transfer characteristics for an n-channel depletion-type MOSFET with
IDSS = 10 mA and VP =4 V.
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
p-Channel D-Type MOSFET
32
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
D-Type MOSFET Symbols
33
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
E-Type MOSFET Construction
The Drain (D) and Source (S) connect to
the to n-doped regions (but note the
absence of a channel between the two n-
doped regions).
• The Gate (G) connects to the p-doped
substrate via a thin insulating layer of
SiO2
• There is no channel, and this is the
primary difference between the
construction of depletion-type and
enhancement-type
MOSFETs.
• The n-doped material lies on a p-doped
substrate that may have an additional
terminal connection called the
Substrate (SS)
34
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Basic Operation
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Basic Operation of the E-Type MOSFET
• VGS is always positive
• As VGS increases, ID
increases
• As VGS is kept constant
and VDS is increased,
then ID saturates (IDSS)
and the saturation level,
VDSsat is reached
The enhancement-type MOSFET operates only in the enhancement mode.
36
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
E-Type MOSFET Transfer Curve
To determine ID given VGS:
Where:
VT = threshold voltage
or voltage at which the
MOSFET turns on
2
T
GS
D )
V
V
(
k
I 

k, a constant, can be determined by using
values at a specific point and the formula:
2
T
GS(ON)
D(ON)
)
V
(V
I
k


VDSsat can be calculated by:
T
GS
Dsat V
V
V 

37
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
p-Channel E-Type MOSFETs
The p-channel enhancement-type MOSFET is similar to the n-
channel, except that the voltage polarities and current directions
are reversed.
38
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
MOSFET Symbols
39
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Handling MOSFETs
MOSFETs are very sensitive to static electricity. Because of the very thin
SiO2 layer between the external terminals and the layers of the device,
any small electrical discharge can create an unwanted conduction.
Protection
• Always transport in a static sensitive bag
• Always wear a static strap when handling MOSFETS
•
• Apply voltage limiting devices between the gate and source, such as
back-to-back Zeners to limit any transient voltage.
40
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
VMOS Devices
VMOS (vertical MOSFET)
increases the surface area of
the device.
Advantages
• VMOS devices handle
higher currents by
providing more surface
area to dissipate the heat.
• VMOS devices also have
faster switching times.
41
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Advantages
• Useful in logic circuit designs
• Higher input impedance
• Faster switching speeds
• Lower operating power levels
CMOS Devices
CMOS (complementary
MOSFET) uses a p-channel
and n-channel MOSFET;
often on the same substrate as
shown here.
42
Copyright ©2009 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Summary Table
43

87690-0135046920_pp5Chapter 5: Field-Effect Transistors.ppt

  • 1.
  • 2.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky INTRODUCTION • The field-effect transistor (FET) is a three-terminal device. • For the FET an electric field is established by the charges present that will control the conduction path of the output
  • 3.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Similarities: • Amplifiers • Switching devices • Impedance matching circuits Differences: • FETs are voltage controlled devices. BJTs are current controlled devices. • FETs have a higher input impedance. BJTs have higher gains. • FETs are less sensitive to temperature variations and are more easily integrated on ICs. • FETs are generally more static sensitive than BJTs. FETs vs. BJTs 3
  • 4.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky •JFET: Junction FET •MOSFET: Metal–Oxide–Semiconductor FET D-MOSFET: Depletion MOSFET E-MOSFET: Enhancement MOSFET FET Types 4
  • 5.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky JFET Construction There are two types of JFETs •n-channel •p-channel The n-channel is more widely used. There are three terminals: •Drain (D) and Source (S) are connected to the n-channel •Gate (G) is connected to the p-type material 5
  • 6.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky JFET Operation: The Basic Idea JFET operation can be compared to a water spigot. The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage. The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage. The control of flow of water is the gate voltage that controls the width of the n- channel and, therefore, the flow of charges from source to drain. 6
  • 7.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky JFET Operating Characteristics There are three basic operating conditions for a JFET: • VGS = 0, VDS increasing to some positive value • VGS < 0, VDS at some positive value • Voltage-controlled resistor 7
  • 8.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky JFET Operating Characteristics: VGS = 0 V • The depletion region between p-gate and n-channel increases as electrons from n-channel combine with holes from p-gate. • Increasing the depletion region, decreases the size of the n-channel which increases the resistance of the n-channel. • Even though the n-channel resistance is increasing, the current (ID) from source to drain through the n- channel is increasing. This is because VDS is increasing. Three things happen when VGS = 0 and VDS is increased from 0 to a more positive voltage 8
  • 9.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky • Assuming a uniform resistance in the n-channel, the resistance of the channel can be broken down to the divisions. • The result is that the upper region of the p-type material will be reverse biased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. • The greater the applied reverse bias, the wider the depletion region.
  • 10.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky If VGS = 0 and VDS is further increased to a more positive voltage, then the depletion zone gets so large that it pinches off the n-channel. This suggests that the current in the n- channel (ID) would drop to 0A, but it does just the opposite–as VDS increases, so does ID. JFET Operating Characteristics: Pinch Off 10
  • 11.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky At the pinch-off point: • Any further increase in VDS does not produce any increase in ID. VDS at pinch-off is denoted as Vp. • ID is at saturation or maximum. It is referred to as IDSS. • The ohmic value of the channel is maximum. JFET Operating Characteristics: Saturation 11
  • 12.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky JFET Operating Characteristics As VGS becomes more negative, the depletion region increases. 12
  • 13.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky As VGS becomes more negative: • The JFET experiences pinch-off at a lower voltage (VP). • ID decreases (ID < IDSS) even though VDS is increased. • Eventually ID reaches 0 A. VGS at this point is called Vp or VGS(off).. JFET Operating Characteristics Also note that at high levels of VDS the JFET reaches a breakdown situation. ID increases uncontrollably if VDS > VDSmax. 13
  • 14.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky 2 P GS o d V V 1 r r           The region to the left of the pinch-off point is called the ohmic region. The JFET can be used as a variable resistor, where VGS controls the drain-source resistance (rd). As VGS becomes more negative, the resistance (rd) increases. JFET Operating Characteristics: Voltage-Controlled Resistor 14
  • 15.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky p-Channel JFETS The p-channel JFET behaves the same as the n-channel JFET, except the voltage polarities and current directions are reversed. 15
  • 16.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky p-Channel JFET Characteristics Also note that at high levels of VDS the JFET reaches a breakdown situation: ID increases uncontrollably if VDS > VDSmax. As VGS increases more positively • The depletion zone increases • ID decreases (ID < IDSS) • Eventually ID = 0 A 16
  • 17.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky N-Channel JFET Symbol 17
  • 18.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky P-Channel JFET Symbol
  • 19.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky The transfer characteristic of input-to-output is not as straightforward in a JFET as it is in a BJT. In a BJT,  indicates the relationship between IB (input) and IC (output). In a JFET, the relationship of VGS (input) and ID (output) is a little more complicated: JFET Transfer Characteristics 19
  • 20.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky JFET Transfer Curve This graph shows the value of ID for a given value of VGS. 20
  • 21.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Using IDSS and Vp (VGS(off)) values found in a specification sheet, the transfer curve can be plotted according to these three steps: Solving for VGS = 0V ID = IDSS 2 P GS DSS D V V 1 I I           Step 1 Plotting the JFET Transfer Curve 21
  • 22.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Solving for VGS = Vp (VGS(off)) ID = 0A 2 P GS DSS D V V 1 I I           Step 2
  • 23.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Solving for VGS = 0V to Vp 2 P GS DSS D V V 1 I I           Step 3
  • 24.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Sketch the transfer curve defined by IDSS = 12 mA and VP = 6 V.
  • 25.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky MOSFETs There are two types of MOSFETs: • Depletion-Type • Enhancement-Type MOSFETs have characteristics similar to JFETs and additional characteristics that make them very useful. 25
  • 26.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Depletion-Type MOSFET Construction The Drain (D) and Source (S) connect to the to n-doped regions. These n- doped regions are connected via an n- channel. This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2 silicon dioxide. The n-doped material lies on a p-doped substrate that may have an additional terminal connection called Substrate (SS). 26
  • 27.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky The gate-to-source voltage is set to zero volts by the direct connection from one terminal to the other, and a voltage VDS is applied across the drain-to-source terminals. The result is an attraction for the positive potential at the drain by the free electrons of the n-channel and a current similar to that established through the channel of the JFET.
  • 28.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Basic MOSFET Operation A depletion-type MOSFET can operate in two modes: • Depletion mode • Enhancement mode 28
  • 29.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky D-Type MOSFET in Depletion Mode • When VGS = 0 V, ID = IDSS • When VGS < 0 V, ID < IDSS • The formula used to plot the transfer curve still applies: Depletion Mode The characteristics are similar to a JFET. 2 P GS DSS D V V 1 I I           29
  • 30.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky D-Type MOSFET in Enhancement Mode • VGS > 0 V • ID increases above IDSS • The formula used to plot the transfer curve still applies: 2 P GS DSS D V V 1 I I           Enhancement Mode Note that VGS is now a positive polarity 30 the application of a positive gate-to-source voltage has “enhanced” the level of free carriers in the channel compared to that encountered with VGS = 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region, with the region between cutoff and the saturation level of IDSS referred to as the depletion region.
  • 31.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Sketch the transfer characteristics for an n-channel depletion-type MOSFET with IDSS = 10 mA and VP =4 V.
  • 32.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky p-Channel D-Type MOSFET 32
  • 33.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky D-Type MOSFET Symbols 33
  • 34.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky E-Type MOSFET Construction The Drain (D) and Source (S) connect to the to n-doped regions (but note the absence of a channel between the two n- doped regions). • The Gate (G) connects to the p-doped substrate via a thin insulating layer of SiO2 • There is no channel, and this is the primary difference between the construction of depletion-type and enhancement-type MOSFETs. • The n-doped material lies on a p-doped substrate that may have an additional terminal connection called the Substrate (SS) 34
  • 35.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Basic Operation
  • 36.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Basic Operation of the E-Type MOSFET • VGS is always positive • As VGS increases, ID increases • As VGS is kept constant and VDS is increased, then ID saturates (IDSS) and the saturation level, VDSsat is reached The enhancement-type MOSFET operates only in the enhancement mode. 36
  • 37.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky E-Type MOSFET Transfer Curve To determine ID given VGS: Where: VT = threshold voltage or voltage at which the MOSFET turns on 2 T GS D ) V V ( k I   k, a constant, can be determined by using values at a specific point and the formula: 2 T GS(ON) D(ON) ) V (V I k   VDSsat can be calculated by: T GS Dsat V V V   37
  • 38.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky p-Channel E-Type MOSFETs The p-channel enhancement-type MOSFET is similar to the n- channel, except that the voltage polarities and current directions are reversed. 38
  • 39.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky MOSFET Symbols 39
  • 40.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Handling MOSFETs MOSFETs are very sensitive to static electricity. Because of the very thin SiO2 layer between the external terminals and the layers of the device, any small electrical discharge can create an unwanted conduction. Protection • Always transport in a static sensitive bag • Always wear a static strap when handling MOSFETS • • Apply voltage limiting devices between the gate and source, such as back-to-back Zeners to limit any transient voltage. 40
  • 41.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky VMOS Devices VMOS (vertical MOSFET) increases the surface area of the device. Advantages • VMOS devices handle higher currents by providing more surface area to dissipate the heat. • VMOS devices also have faster switching times. 41
  • 42.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Advantages • Useful in logic circuit designs • Higher input impedance • Faster switching speeds • Lower operating power levels CMOS Devices CMOS (complementary MOSFET) uses a p-channel and n-channel MOSFET; often on the same substrate as shown here. 42
  • 43.
    Copyright ©2009 byPearson Education, Inc. Upper Saddle River, New Jersey 07458 • All rights reserved. Electronic Devices and Circuit Theory, 10/e Robert L. Boylestad and Louis Nashelsky Summary Table 43