The document discusses FPGAs and their architecture. It covers FPGA programming using HDL languages and design flows. It also discusses FPGA DSP capabilities like arithmetic operations, FFTs, and filters. Basic FPGA elements are logic blocks, flip-flops, wires and I/O pads. Modern FPGAs add blocks for computations and storage. HDLs describe hardware structures and behaviors using extensive parallel operations. Common HDLs are synthesized into FPGAs using design tools to implement algorithms in programmable logic.

1. ESS | FPGA for Dummies | 2016-09-20 | Maurizio Donna
FPGA for
Dummies
Design flow

2. ESS | FPGA for Dummies | 2016-09-20 | Maurizio Donna
FPGA for Dummies
• FPGA Architecture:
 basic blocks (Logic, FFs, wires and IOs);
 additional modern elements;
• FPGA Programming:
HDL languages;
Design flow;
• FPGA DSP:
Arithmetic, FFT and filters;

3. ESS | FPGA for Dummies | 2016-09-20 | Maurizio Donna
FPGA for Dummies
• FPGA Architecture:
 basic blocks (Logic, FFs, wires and IOs);
 additional modern elements;
• FPGA Programming:
HDL languages;
Design flow;
• FPGA DSP:
Arithmetic, FFT and filters;

4. ESS | FPGA for Dummies | 2016-09-20 | Maurizio Donna
FPGA Architecture

5. ESS | FPGA for Dummies | 2016-09-20 | Maurizio Donna
FPGA Architecture
Contemporary FPGA architectures incorporate the
basic elements along with additional computational
and data storage blocks that increase the
computational density and efficiency of the device.
The combination of these elements provides the
FPGA with the flexibility to implement any software
algorithm running on a processor.

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Hardware Description Language -
Introduction
• HDL is a language that describes the hardware of digital
systems in a textual form.
• It resembles a programming language, but is specifically
oriented to describing HARDWARE STRUCTURES and
BEHAVIORS.
• The main difference with the traditional programming
languages is HDL’s representation of extensive parallel
operations whereas traditional ones represents mostly
serial operations.
• The most common use of a HDL is to provide an
alternative to schematics.

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System
Architect
HDL
Sources
Schematic
Sources IP
Simulation
Scripts
Test
Vectors
SIMULATE
GOLDEN
Model
FPGA
Designer
ProjectSYNTHESIZE
PLACE & ROUTE Constrain
BITSTREAM
HW
Platform

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Analog & Digital Signal
• Analog system: the
physical quantities or
signals may vary
continuously over a
specified range.
• Digital system: the
physical quantities or
signals can assume only
discrete values.
Analog signal Digital signal

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Binary Digital Signal
• An information variable represented by physical
quantity.
• For digital systems, the variable takes on discrete
values.
– Two level, or binary values are the most prevalent values.
• Binary values are represented abstractly by:
– Digits 0 and 1
– Words (symbols) False (F) and True (T)
– Words (symbols) Low (L) and High (H)
– And words On and Off
• Binary values are represented by values
or ranges of values of physical quantities.

10. ESS | FPGA for Dummies | 2016-09-20 | Maurizio Donna
Number System
• Base = 2 (binary sistem)
• 2 digits { 0, 1 },
called binary digits or “bits”
• Groups 4 bits = Nibble, 8 bits = Byte
• Base = 16
• 16 digits
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
A, B, C, D, E, F }
• Formal Notation

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Fixed point vs Floating point
 The CPUs uses floating point format
(32/64 bit)
 FPGA build their on computational core,
so you could have a Floating-Point IP
performing operation;
 Fpga structure support fixed point
arithmetic (distributed or on DSP block);

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Resource allocation
4 operation: +, -, *, <>=
Example of solution of differential equation:
 y” + 3*x*y’ + 3*y = 0;
 Interval [0, a], integration Δx;
 Initial values x(0)= 0, y(0)=y, y’(0)=u;
Solution using Forward Euler:
 xn+1 = xn + Δx;
 un+1 = un – Δx*(3*xn*un + 3*yn);
 yn+1 = yn + un*Δx;

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Equation graph

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Sequential graph

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1 operation per cicle

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2 operation per cicle

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Adder
Distributed adder uses
the LUT and the carry
chain inside the FPGA.
If the number of bit is
high (depends on the
specific component) the
delay o the carry chain
(critical path) become
too long and the
maximum speed is
limited

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Multiplier
Distributed multiplier also
uses the LUT (more) and
the carry chain inside the
FPGA.
Even more critical than
the adder structure.

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Comparators
Comparators (=) is quite
simple but it also has trade off
between number of bits and
speed.

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XILINX DSP48 block
• multiplier 27x18 bits
• pre-adder 27 bits: accept input from either the A or B inputs in addition to the D input.
• The output of the pre-adder can be squared.
• The ALU now accepts a fourth operand through the W multiplexer.
• The XOR block can operate as
– octal 12-bit XOR
– quad 24-bit XOR
– dual 48-bit XOR
– one 96-bit XOR.

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Others FPGA
Altera Stratix-II DSP block. LatticeECP DSP block

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DSP48 slices cascade

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FIR FILTER EXAMPLE

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Transposed FIR
The Transposed FIR Filter structure is easily mapped to the
DSP48 slice without additional external logic

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Systolic FIR
The Systolic FIR Filter offers the highest performance in a
DSP48 slice

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Coefficient & Data Memory
Memory is required for data and coefficient storage.
This may be a mixture of RAM and ROM internal to the FPGA.
RAM is used for the data samples and is implemented using a cyclic
RAM buffer.
For high coefficient count, the BRAM in the FPGA sit on the column on
the side of the DSP, to easily interconnect.
MAC engine FIR filter

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The Fourier Transform
• FFT is a mathematical procedure used to
determine the harmonic, or frequency,
content of a discrete signal sequence;
• DFT is the discrete equivalent of the
continuous Fourier Transform;

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Radix-2 FFT
• For the radix-2 FFT
algorithm, the
smallest transform
or butterfly (basic
computational unit)
used is the 2-point
DFT

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LUT implementation
Pipeline radix-2 butterfly in FPGA

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DSP implementation
Pipeline, complex multiplier with four parallel real multipliers

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System generator flow

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$1.9 bilion
$55.4 bilion
$2.4 bilion
$366.1 milion
$1.2 bilion
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Questions

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