FPGA based Heart Arrhythmia’s Detection Algorithm

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ACEEE Int. J. on Information Technology, Vol. 3, No. 1, March 2013

FPGA based Heart Arrhythmia’s Detection Algorithm
Sheikh Md. Rabiul Islam, A. F. M. Nokib Uddin, Md. Billal Hossain, Md. Imran Khan
Dept. of Electronics and Communication Engineering
Khulna University of Engineering &Technology
Khulna, Bangladesh
E-mail: robi@ece.kuet.ac.bd,nokib.ece@gmail.com, billal.0709018@gmail.com, imrankhankuet@gmail.com.

Abstract- Electrocardiogram (ECG) signal has been widely used a human heart for detection of diseases [6]. To acquire the
for heart diagnoses .In this paper, we presents the design of signal, ECG devices with varying number of electrodes (3–
Heart Arrhythmias Detector using Verilog HDL based on been 12) can be used. Multi lead systems exceeding 12 and up to
mapped on small commercially available FPGAs (Field 120 electrodes are also available [7].
Programmable Gate Arrays). Majority of the deaths occurs
The QRS complex is the largest deflection voltage of about
before emergency services can step in to intervene. In this
research work, we have implemented QRS detection device 10 - 20 mV but may vary in size depending on age and sex of
developed by Ahlstrom and Tompkins in Verilog HDL. The the human. The amplitude of the voltage of the QRS complex
generated source has been simulated for validation and tested may also give information on heart disease [8]. Duration of
on software Verilogger Pro6.5. We have collected data from the QRS complex indicates the time for the ventricles to
MIT-BIH Arrhythmia Database for test of proposed digital depolarize and can provide information on problems
system and this data have given MIT-BIH data as an input of conduction in the ventricles as the bundle branch block.
our proposed device using test bench software. We have The MIT-BIH [9] arrhythmia database is used for
compared our device output with MATLAB output and performance evaluation based on the study. The MIT-BIH
calculating the error percentage and got desire research key
database contains 48 disks, each containing two channels of
point of RR interval between the peaks of QRS signal. The
proposed system also investigated with different database of ECG signals for 30 min duration of 24 hours selected from the
MIT-BIH for detect different heart Arrhythmias and proposed recordings of 47 individuals. There are also data numbers
device give output exactly same according to our QRS detection 116.137 QRS complexes in the database [10]. The database
algorithm. record contains both timing information and class information
heartbeat checked by independent experts [11].
Index Terms -Verilog HDL, QRS, ECG, MIT-BIH, Heart Xilinx ISE [12],[13] is a software tool produced by Xilinx
Arrhythmia. for synthesis and analysis of HDL designs, which enables
the developer to synthesize designs, examine RTL diagrams,
I. INTRODUCTION simulate a design’s reaction to different stimuli, and configure
Heart arrhythmias occurs when the electrical impulses in the target device with the programmer. The building block
heart that coordinate your heartbeats don’t work properly, were designed, tested and evaluated using the ISE tool
causing your heart to beat too fast, too slow or irregularly available from Xilinx & VeriloggerPro6.5 (TestBencher
[1]. Arrhythmias can take place in a healthy heart and be of pro)[14].
minimal consequence but they may also indicate a serious This paper is structured as follows. Section II describes
problem that may lead to stroke or sudden cardiac death [2- the QRS detection algorithm. Section III part A describes
3]. Heart arrhythmia treatment can often control or eliminate about the Ahlstrom and Tompkins algorithm and section B
irregular heartbeats. There are hundreds of different types of for Arrhythmias detection process. In Section IV part A
heart arrhythmias among them common arrhythmias are atrial describes the bus architecture and section B is for describing
fibrillation (AF), Premature Atrial Contractions (PAC), Atrial modules. Section V shows simulation and synthesized result.
Tachycardia, Atrial Fibrillation, Atrial Flutter, Premature Finally Section VI for conclusion.
Ventricular Contractions (PVC), Ventricular Tachycardia (VT),
Ventricular Fibrillation. II. QRS DETECTION ALGORITHM
Electrocardiogram (ECG) is a diagnosis tool that reported Till now, various methods have been reported by researchers
the electrical activity of heart recorded by skin electrode. for detection of QRS complex [15-18], Algorithms [19-21] are
The morphology and heart rate meditates the cardiac health based amplitude and the first derivative .In [20] a point is
of human heart beat [4]. It is a noninvasive technique [5]. classified as QRS candidate when three consecutive points
Any disorder of heart rate change in the morphological of the first derivative exceed a positive threshold (ascending
pattern is a reading of cardiac arrhythmia, after measure could slope) followed within the next 100ms by two consecutive
be detected by analysis of ECG waveform. Whatever the points which exceed a negative threshold (descending slope).
magnitude and duration of the P-QRS-T wave contains useful Algorithms [22] and [23] are based on the first derivative
information about the nature of the disease that affects the only. Algorithms [24-26] are based on the first and second
heart in this regard the electric wave is due to depolarization derivatives. Ahlstrom and Tompkins in [24] proposed that
and polarization king of Na + and blood of the body ions the absolute values of the first derivative are smoothed and
human [5].The ECG signal provides important information of added with the absolute values of the second derivative.
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Balda [25] suggested searching values exceeding the TABLE I. HEART RATE AND R-R I NTERVAL FOR D IFFERENT HEART ARRHYTHMIA.
threshold in a weighted summation of the first and second
derivative, later this method was developed by Ahlstrom and
Tompkins [24]. Friesen [27] and Tompkins [28] also
investigated similar methods based on sensitivity of QRS
complex to noise. There is several QRS detection method
based on the digital filter [29-33], filter banks [34-35].

III. METHODOLOGY
A. Basic QRS Complexes Detection Algorithm
Among the so many algorithms we select first and second functions of a data bus to carry information and address bus
derivative based scheme developed by Ahlstrom and to determine where it should be sent and a control bus to
Tompkins [24] the rectified first derivative is calculated from determine its operation .The Bus architecture of the proposed
the ECG: digital system is shown in Figs.1-3.
Y0(n)=ABS[X(n+1)-X(n-1)] 3<n<8188
the rectified first derivative is then smoothed:
Y1(n)=[Y0(n-1)+2Y0(n)+Y0(n+1)]/4 3<n<8188
The rectified second derivative is calculated:
Y2(n)=ABS[X(n+2)-2X(n)+X(n-2)] 3<n<8188
The rectified smoothed first derivative is added to the
rectified second derivative:
Y3(n)=Y1(n)+Y2(n) 3<n<8188
The maximum value of this array is determined and scaled
to serve as primary and secondary thresholds:
Primary threshold=0.8*max[Y3(n)] 3<n<8188
Secondary threshold=0.1*max[Y3(n)] 3<n<8188
The array of the summed first and second derivative is
scanned until a point exceeds the primary thresholds. In order
to be classified as a QRS candidate, the next consecutive
point must all meet or exceed the secondary threshold. That
is the threshold and QRS detection algorithm is just like bellow: Fig. 1. Block diagram of the system including data bus.
Y3(i) >= primary threshold, and
Y3(i+1), Y3(i+2) . . . . . . Y3(i+6) > secondary threshold
After detecting the QRS complex we detect the R peak
and R-R interval. There are several types of noise (i.e. muscle
artifact, electrode motion artifact, white noise etc.) may
hamper the ECG signal as well as the performance also.
Performance of first and second derivative based method is
much better than the first derivative methods [36].
B. Arrhythmias Detection
For detection of Arrhythmias at first we need to know the
heart rate of different Arrhythmias. Bellow table shows the
heart rate for different arrhythmias. If the sampling frequency
Fs Hz then, Time for one sample Ts= second
If R-R interval (in sample) is N samples then,
R-R interval (in time) = Ts N second Fig. 2. Block diagram of the system including control bus and
After calculating R-R interval we can detect heart internal structure
Arrhythmia from Table. I. In our system input and output is unidirectional to data
bus. Input block take input data from data source and send it
IV. PROPOSED ARCHITECTURE to data bus. Output block take data from data bus and show
A. Bus Architecture the output data.RAM, register A, register B and ALU are
bidirectional that is it can send and receive data from data
A system bus is a single computer bus that connects the
bus. In control bus architecture shown in Fig.2, control block
major components of a computer system. It combines the
determines the operation of rest of the block using control
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TABLE II. C ONTROL BUS FROM CONTROL R OM TO DIFFERENT MODULES.

Fig. 3. Block diagram of the system including Address bus. “RAM” to save the data permanently.
bus except PC and PRO-PC. All other blocks are connected 5. Register A & B
with control bus. Those connections are unidirectional. These two 16 bit registers are used for to save the data
Connection between PRO-PC and PC represent the internal temporarily & send the data to ALU or RAM.
connection.In Fig.3 it shows the address bus architecture. 6. ALU
RAM, PTR and P block are connected with address bus. The ALU is the arithmetic logic unit which is designed for
functions of these blocks are described in section IV (B). doing addition, subtraction, shift left, shift right arithmetic
calculations. In our proposed design ALU
B. Description of Different Modules.
can process 16 bit data and save processed value to its
In our proposed design we have designed thirteen blocks. internal register and can send it to reg A, B and RAM.
All function of those blocks is described below: 7. PTR
1. Pro-Program Counter (PRO-PC) PTR inform P block about the initial position of its
It is a one kind of clock pulse generator and also a counter. parameter(X, Y0, Y1, Y2, and Y3) of the equation. Output of
It generates clock pulse for driving the Program counter (PC) PTR is 4bit.
from the main clock pulse. In this design it generates a pulse 8. P
with one positive edge against four main clock pulses. That is P block select the RAM address for each parameter
Pro-PC force PC to provide same output several times. Output (X(n),Y0(n),Y1(n),Y2(n),Y3(n)).Output of P block is 4 bit.
of Pro-PC is 2bit. 9. Output
2. Program Counter (PC) It is a register which stands for saving the output data.
A program counter is counter which count the clock. The We use 16 bit output register in our proposed design.
main objective of this block is control the “control” block. 10. RAM
Program counter take two bit input from Pro-PC and using RAM stands for random access memory. It is volatile
clock signal it count 0 to 138.So the output of Program counter memory to store temporary data.RAM is an array of register
is 8bit.At the first time of counting it counts 0 to 12 sequences bank which is accessible (read and write) according to address.
to take input six consecutive data sequentially. After that it We use 192 bit RAM which contain 12 memory unit each unit
counts 17 to 138 sequences to process six data and give have 16bit storage capability. From the data bus architecture
output to output register. If it count 138 sequence it will start shown in Figure.1 we can see that it can send and receive
re-counting from 13-138 again and again in order to take two data from Reg. A, B, INPUT, ALU. That is connection between
consecutive data input, process it and give output to output RAM and data bus is unidirectional. Table III shown that
register. location and value of RAM according to the PTR and P block
3. Control ROM output.
It is the ROM of our system. It take 8bit input from the
Program Counter and give 36 bit output which is called control V. SIMULATION RESULTS & SYNTHESIS
bus and connected almost all block to control their operation.
Block diagram of control bus given in Fig.2 in previous Synthesis is the process of constructing a gate level
section. Now bellow Table II shows the control bus structure. netlist from a register-transfer level model of a circuit described
Table II. Control Bus From Control Rom To Different Mod- in Verilog HDL. After synthesizing in Xilinx project navigator
ules. we got RTL schematic diagram of proposed design which is
4. Input shown in Fig.5. Fig.4 shows synthesized RTL schematic of
In our system we use 16 bit input register to receive input the top level of our proposed design. Simulation is the process
sampled value from the peripheral device & store the data of verifying the functional characteristics of models at any
temporarily. It can also send the data to the block called level of abstraction. To test if the RTL code meets the
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TABLE III. ADDRESS O F R AM FOR DIFFERENT PARAMETERS Ahlstrom and Tompkins algorithm. Fig.10, 11 and 12 stands
for normal ECG signal, Ventricular Tachyarrhythmia and Atrial
fibrillation respectively.In order to measure R-R interval, we
take 1100 samples for each signal. For normal ECG signal we
use 360Hz sampling frequency and for other we use 250Hz.In
Fig.10, R-R interval is 292 samples that is 0.76 (according to
equation 1) seconds, so heart rate is approximately 79bpm
that indicates it is normal ECG signal according to Table
I.Similarly for Fig.11, heart rate is 120 bpm (Beats Per Minute)
approximately which clearly indicates that is ventricular
Tachyarrhythmia. In Figure.12 we can see that the R-R
interval is not constant. As a result it can be concluded, it is
atrial fibrillation.
functional requirements of the specification shown if all the
RTL blocks are functionally correct. To archive this we need
to write test bench which generates clk, reset and required
test vectors. Figs. 6-9 shows test bench output for real ECG
data input which is listed in Table III.

Fig. 6. Output for first eight consecutive input data

Fig. 4. Block Diagram of our proposed design

Fig. 7. Ninth data input to testbench.

Fig. 8. Output for ninth input data.

Fig. 5. RTL schematics of our proposed design.
For higher accuracy we multiply a gain factor with normal
ECG data.In this work we used actual ECG records such as
MIT100 from MIT-BIH database whereas we have given it
as a input to testbench and collect output data as tabulated
in Table IV.There are small deviation between testbench output
and MATLAB output due to unablity to calculate floating
point.This deviation is neglegible.In Figs.10- 12 shows by
Fig. 9. Output for tenth input data.
MATLAB output for QRS complex and R peak detection using
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TABLE IV. C OMPARE BETWEEN VERILOG T ESTBENCH AND MATLAB O UTPUT The proposed model is loaded on XILINX FPGA board. It is
implemented upon XILINX SPARTAN XC2S150 FPGA board
processor. When it is implemented on FPGA board processor
then the clock frequency of the processor is 1MHZ. The
proposed model has the same power consumption, signal
bandwidth and CMOS technology is used on the XC2S150
processor.

CONCLUSIONS
We have coded the equations of Ahlstrom and Tompkins
method using Verilog Hardware Description Language. Try
to detect the peak of two consecutive ECG waveform, found
the time interval of R-R is detected. Compare with the time
interval of R-R of normal cardiac conditions, the abnormalities
of heart rate is determined. Some heart arrhythmias depends
not only the R-R interval but also P, T wave. Our system
can’t detect those kinds of arrhythmias. We use
VeriloggerPro6.5 (Test Bencher pro) demo version which has
a limitation that it cannot simulate over 1225 line and show
more than 26 consecutive outputs correctly. In future we will
try to update our system for calculating floating point data
and also use licence version of VHDL.

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data acquisition, processing and recording, “in Proc.1981 IEEE AUTHOR BIOGRAPHIES
Int. Conf. Industrial Elect. Contr. Instrument.,1981,pp.64-69
[23] W.P. Holsimger , “A QRS pre-processor based on digital Sheikh Md. Rabiul Islam received the B.Sc.in Engg.
differentiation” IEEE Trans. Biomed. Eng.,vol.BME- (ECE) from Khulna University, Khulna, Bangladesh
18,pp.212-217,1971 in December 2003, and M.Sc. in Telecommunication
[24] M.L. Ahlstrom and W J. Tompkins, “Automated high-speed Engineering from the University of Trento, Italy, in
analysis of holter taps with microcomputers,” IEEE Trans.
Biomed. Eng., vol. BME-30,pp.651-657,Oct.1983 October 2009. He joined as a Lecturer in the department of Elec-
[25] BALDA R. A. “The HP ECG analysis program” in tronics and Communication Engineering of Khulna University of
VANBEMNEL J. H. and WILLEMS J.L. (Ed): ‘Trends in Engineering & Technology, Khulna, in 2004, where he is currently
Computer- Process Electrocardiograms’ , (North Holland), pp. an Assistant Professor in the same department in the effect of
197-205, 1977 2008. He has published 15 Journals and six international confer-
[26] R. M. Rangayyan, “Biomedical signal analysis: a case-study ences.. His research interests include Numerical analysis, VLSI,
approach”, IEEE Press, 2001. wireless communications , signal & image processing, and biomedi-
[27] G. M. Friesen, T. C. Jannett, M. A. Jadallah, S. L. Yates, S. R. cal engineering.
Quint and H. T. Nagle, “A comparison of the noise sensitivity A. F. M. Nokib Uddin received a B.Sc. Engg. (ECE) of
of nine QRS detection algorithms”, IEEE Trans. Biomed. Eng., department of Electronics and Communication Engineering at
vol. 37, pp. 85-97, 1990. Khulna University of Engineering & Technology, Khulna_9203,
[28] W. J. Tompkins, “Biomedical digital signal processing”, Bangladesh.
Prentice-Hall, Upper Saddle River, NJ, 1995. Md.Billal Hossain received a B.Sc. Engg.(ECE) of department
[29] M. Okada, “A digital filter for the QRS complex detection,” of Electronics and Communication Engineering at Khulna University
IEEE Trans. Biomed. Eng., vol. 26, pp. 700-703, Dec. 1979. of Engineering & Technology, Khulna_9203, Bangladesh.
Md. Imran Khan received a B.Sc. Engg. (ECE)of department of
Electronics and Communication Engineering at Khulna University
of Engineering & Technology, Khulna_9203, Bangladesh

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FPGA based Heart Arrhythmia’s Detection Algorithm

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